1/* 2 * BK Id: SCCS/s.mmu.h 1.10 06/28/01 15:50:17 paulus 3 */ 4/* 5 * PowerPC memory management structures 6 */ 7 8#ifdef __KERNEL__ 9#ifndef _PPC_MMU_H_ 10#define _PPC_MMU_H_ 11 12#include <linux/config.h> 13 14#ifndef __ASSEMBLY__ 15 16/* Default "unsigned long" context */ 17typedef unsigned long mm_context_t; 18 19/* Hardware Page Table Entry */ 20typedef struct _PTE { 21#ifdef CONFIG_PPC64BRIDGE 22 unsigned long long vsid:52; 23 unsigned long api:5; 24 unsigned long :5; 25 unsigned long h:1; 26 unsigned long v:1; 27 unsigned long long rpn:52; 28#else /* CONFIG_PPC64BRIDGE */ 29 unsigned long v:1; /* Entry is valid */ 30 unsigned long vsid:24; /* Virtual segment identifier */ 31 unsigned long h:1; /* Hash algorithm indicator */ 32 unsigned long api:6; /* Abbreviated page index */ 33 unsigned long rpn:20; /* Real (physical) page number */ 34#endif /* CONFIG_PPC64BRIDGE */ 35 unsigned long :3; /* Unused */ 36 unsigned long r:1; /* Referenced */ 37 unsigned long c:1; /* Changed */ 38 unsigned long w:1; /* Write-thru cache mode */ 39 unsigned long i:1; /* Cache inhibited */ 40 unsigned long m:1; /* Memory coherence */ 41 unsigned long g:1; /* Guarded */ 42 unsigned long :1; /* Unused */ 43 unsigned long pp:2; /* Page protection */ 44} PTE; 45 46/* Values for PP (assumes Ks=0, Kp=1) */ 47#define PP_RWXX 0 /* Supervisor read/write, User none */ 48#define PP_RWRX 1 /* Supervisor read/write, User read */ 49#define PP_RWRW 2 /* Supervisor read/write, User read/write */ 50#define PP_RXRX 3 /* Supervisor read, User read */ 51 52/* Segment Register */ 53typedef struct _SEGREG { 54 unsigned long t:1; /* Normal or I/O type */ 55 unsigned long ks:1; /* Supervisor 'key' (normally 0) */ 56 unsigned long kp:1; /* User 'key' (normally 1) */ 57 unsigned long n:1; /* No-execute */ 58 unsigned long :4; /* Unused */ 59 unsigned long vsid:24; /* Virtual Segment Identifier */ 60} SEGREG; 61 62/* Block Address Translation (BAT) Registers */ 63typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */ 64 unsigned long bepi:15; /* Effective page index (virtual address) */ 65 unsigned long :8; /* unused */ 66 unsigned long w:1; 67 unsigned long i:1; /* Cache inhibit */ 68 unsigned long m:1; /* Memory coherence */ 69 unsigned long ks:1; /* Supervisor key (normally 0) */ 70 unsigned long kp:1; /* User key (normally 1) */ 71 unsigned long pp:2; /* Page access protections */ 72} P601_BATU; 73 74typedef struct _BATU { /* Upper part of BAT (all except 601) */ 75#ifdef CONFIG_PPC64BRIDGE 76 unsigned long long bepi:47; 77#else /* CONFIG_PPC64BRIDGE */ 78 unsigned long bepi:15; /* Effective page index (virtual address) */ 79#endif /* CONFIG_PPC64BRIDGE */ 80 unsigned long :4; /* Unused */ 81 unsigned long bl:11; /* Block size mask */ 82 unsigned long vs:1; /* Supervisor valid */ 83 unsigned long vp:1; /* User valid */ 84} BATU; 85 86typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */ 87 unsigned long brpn:15; /* Real page index (physical address) */ 88 unsigned long :10; /* Unused */ 89 unsigned long v:1; /* Valid bit */ 90 unsigned long bl:6; /* Block size mask */ 91} P601_BATL; 92 93typedef struct _BATL { /* Lower part of BAT (all except 601) */ 94#ifdef CONFIG_PPC64BRIDGE 95 unsigned long long brpn:47; 96#else /* CONFIG_PPC64BRIDGE */ 97 unsigned long brpn:15; /* Real page index (physical address) */ 98#endif /* CONFIG_PPC64BRIDGE */ 99 unsigned long :10; /* Unused */ 100 unsigned long w:1; /* Write-thru cache */ 101 unsigned long i:1; /* Cache inhibit */ 102 unsigned long m:1; /* Memory coherence */ 103 unsigned long g:1; /* Guarded (MBZ in IBAT) */ 104 unsigned long :1; /* Unused */ 105 unsigned long pp:2; /* Page access protections */ 106} BATL; 107 108typedef struct _BAT { 109 BATU batu; /* Upper register */ 110 BATL batl; /* Lower register */ 111} BAT; 112 113typedef struct _P601_BAT { 114 P601_BATU batu; /* Upper register */ 115 P601_BATL batl; /* Lower register */ 116} P601_BAT; 117 118extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ 119extern void _tlbia(void); /* invalidate all TLB entries */ 120 121#endif /* __ASSEMBLY__ */ 122 123/* Block size masks */ 124#define BL_128K 0x000 125#define BL_256K 0x001 126#define BL_512K 0x003 127#define BL_1M 0x007 128#define BL_2M 0x00F 129#define BL_4M 0x01F 130#define BL_8M 0x03F 131#define BL_16M 0x07F 132#define BL_32M 0x0FF 133#define BL_64M 0x1FF 134#define BL_128M 0x3FF 135#define BL_256M 0x7FF 136 137/* BAT Access Protection */ 138#define BPP_XX 0x00 /* No access */ 139#define BPP_RX 0x01 /* Read only */ 140#define BPP_RW 0x02 /* Read/write */ 141 142/* Control/status registers for the MPC8xx. 143 * A write operation to these registers causes serialized access. 144 * During software tablewalk, the registers used perform mask/shift-add 145 * operations when written/read. A TLB entry is created when the Mx_RPN 146 * is written, and the contents of several registers are used to 147 * create the entry. 148 */ 149#define MI_CTR 784 /* Instruction TLB control register */ 150#define MI_GPM 0x80000000 /* Set domain manager mode */ 151#define MI_PPM 0x40000000 /* Set subpage protection */ 152#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 153#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 154#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 155#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */ 156#define MI_RESETVAL 0x00000000 /* Value of register at reset */ 157 158/* These are the Ks and Kp from the PowerPC books. For proper operation, 159 * Ks = 0, Kp = 1. 160 */ 161#define MI_AP 786 162#define MI_Ks 0x80000000 /* Should not be set */ 163#define MI_Kp 0x40000000 /* Should always be set */ 164 165/* The effective page number register. When read, contains the information 166 * about the last instruction TLB miss. When MI_RPN is written, bits in 167 * this register are used to create the TLB entry. 168 */ 169#define MI_EPN 787 170#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */ 171#define MI_EVALID 0x00000200 /* Entry is valid */ 172#define MI_ASIDMASK 0x0000000f /* ASID match value */ 173 /* Reset value is undefined */ 174 175/* A "level 1" or "segment" or whatever you want to call it register. 176 * For the instruction TLB, it contains bits that get loaded into the 177 * TLB entry when the MI_RPN is written. 178 */ 179#define MI_TWC 789 180#define MI_APG 0x000001e0 /* Access protection group (0) */ 181#define MI_GUARDED 0x00000010 /* Guarded storage */ 182#define MI_PSMASK 0x0000000c /* Mask of page size bits */ 183#define MI_PS8MEG 0x0000000c /* 8M page size */ 184#define MI_PS512K 0x00000004 /* 512K page size */ 185#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */ 186#define MI_SVALID 0x00000001 /* Segment entry is valid */ 187 /* Reset value is undefined */ 188 189/* Real page number. Defined by the pte. Writing this register 190 * causes a TLB entry to be created for the instruction TLB, using 191 * additional information from the MI_EPN, and MI_TWC registers. 192 */ 193#define MI_RPN 790 194 195/* Define an RPN value for mapping kernel memory to large virtual 196 * pages for boot initialization. This has real page number of 0, 197 * large page size, shared page, cache enabled, and valid. 198 * Also mark all subpages valid and write access. 199 */ 200#define MI_BOOTINIT 0x000001fd 201 202#define MD_CTR 792 /* Data TLB control register */ 203#define MD_GPM 0x80000000 /* Set domain manager mode */ 204#define MD_PPM 0x40000000 /* Set subpage protection */ 205#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */ 206#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */ 207#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */ 208#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */ 209#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */ 210#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */ 211#define MD_RESETVAL 0x04000000 /* Value of register at reset */ 212 213#define M_CASID 793 /* Address space ID (context) to match */ 214#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */ 215 216 217/* These are the Ks and Kp from the PowerPC books. For proper operation, 218 * Ks = 0, Kp = 1. 219 */ 220#define MD_AP 794 221#define MD_Ks 0x80000000 /* Should not be set */ 222#define MD_Kp 0x40000000 /* Should always be set */ 223 224/* The effective page number register. When read, contains the information 225 * about the last instruction TLB miss. When MD_RPN is written, bits in 226 * this register are used to create the TLB entry. 227 */ 228#define MD_EPN 795 229#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */ 230#define MD_EVALID 0x00000200 /* Entry is valid */ 231#define MD_ASIDMASK 0x0000000f /* ASID match value */ 232 /* Reset value is undefined */ 233 234/* The pointer to the base address of the first level page table. 235 * During a software tablewalk, reading this register provides the address 236 * of the entry associated with MD_EPN. 237 */ 238#define M_TWB 796 239#define M_L1TB 0xfffff000 /* Level 1 table base address */ 240#define M_L1INDX 0x00000ffc /* Level 1 index, when read */ 241 /* Reset value is undefined */ 242 243/* A "level 1" or "segment" or whatever you want to call it register. 244 * For the data TLB, it contains bits that get loaded into the TLB entry 245 * when the MD_RPN is written. It is also provides the hardware assist 246 * for finding the PTE address during software tablewalk. 247 */ 248#define MD_TWC 797 249#define MD_L2TB 0xfffff000 /* Level 2 table base address */ 250#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */ 251#define MD_APG 0x000001e0 /* Access protection group (0) */ 252#define MD_GUARDED 0x00000010 /* Guarded storage */ 253#define MD_PSMASK 0x0000000c /* Mask of page size bits */ 254#define MD_PS8MEG 0x0000000c /* 8M page size */ 255#define MD_PS512K 0x00000004 /* 512K page size */ 256#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */ 257#define MD_WT 0x00000002 /* Use writethrough page attribute */ 258#define MD_SVALID 0x00000001 /* Segment entry is valid */ 259 /* Reset value is undefined */ 260 261 262/* Real page number. Defined by the pte. Writing this register 263 * causes a TLB entry to be created for the data TLB, using 264 * additional information from the MD_EPN, and MD_TWC registers. 265 */ 266#define MD_RPN 798 267 268/* This is a temporary storage register that could be used to save 269 * a processor working register during a tablewalk. 270 */ 271#define M_TW 799 272 273/* 274 * At present, all PowerPC 400-class processors share a similar TLB 275 * architecture. The instruction and data sides share a unified, 276 * 64-entry, fully-associative TLB which is maintained totally under 277 * software control. In addition, the instruction side has a 278 * hardware-managed, 4-entry, fully- associative TLB which serves as a 279 * first level to the shared TLB. These two TLBs are known as the UTLB 280 * and ITLB, respectively. 281 */ 282 283#define PPC4XX_TLB_SIZE 64 284 285/* 286 * TLB entries are defined by a "high" tag portion and a "low" data 287 * portion. On all architectures, the data portion is 32-bits. 288 * 289 * TLB entries are managed entirely under software control by reading, 290 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx 291 * instructions. 292 */ 293 294#define TLB_LO 1 295#define TLB_HI 0 296 297#define TLB_DATA TLB_LO 298#define TLB_TAG TLB_HI 299 300/* Tag portion */ 301 302#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ 303#define TLB_PAGESZ_MASK 0x00000380 304#define TLB_PAGESZ(x) (((x) & 0x7) << 7) 305#define PAGESZ_1K 0 306#define PAGESZ_4K 1 307#define PAGESZ_16K 2 308#define PAGESZ_64K 3 309#define PAGESZ_256K 4 310#define PAGESZ_1M 5 311#define PAGESZ_4M 6 312#define PAGESZ_16M 7 313#define TLB_VALID 0x00000040 /* Entry is valid */ 314 315/* Data portion */ 316 317#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ 318#define TLB_PERM_MASK 0x00000300 319#define TLB_EX 0x00000200 /* Instruction execution allowed */ 320#define TLB_WR 0x00000100 /* Writes permitted */ 321#define TLB_ZSEL_MASK 0x000000F0 322#define TLB_ZSEL(x) (((x) & 0xF) << 4) 323#define TLB_ATTR_MASK 0x0000000F 324#define TLB_W 0x00000008 /* Caching is write-through */ 325#define TLB_I 0x00000004 /* Caching is inhibited */ 326#define TLB_M 0x00000002 /* Memory is coherent */ 327#define TLB_G 0x00000001 /* Memory is guarded from prefetch */ 328 329#endif /* _PPC_MMU_H_ */ 330#endif /* __KERNEL__ */ 331