1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2002 by Ralf Baechle 7 */ 8#ifndef _ASM_WAR_H 9#define _ASM_WAR_H 10 11#include <linux/config.h> 12 13/* 14 * Pleassures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: 15 * 16 * 18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D, 17 * Hit_Invalidate_D and Create_Dirty_Excl_D should only be 18 * executed if there is no other dcache activity. If the dcache is 19 * accessed for another instruction immeidately preceding when these 20 * cache instructions are executing, it is possible that the dcache 21 * tag match outputs used by these cache instructions will be 22 * incorrect. These cache instructions should be preceded by at least 23 * four instructions that are not any kind of load or store 24 * instruction. 25 * 26 * This is not allowed: lw 27 * nop 28 * nop 29 * nop 30 * cache Hit_Writeback_Invalidate_D 31 * 32 * This is allowed: lw 33 * nop 34 * nop 35 * nop 36 * nop 37 * cache Hit_Writeback_Invalidate_D 38 */ 39#undef R4600_V1_HIT_DCACHE_WAR /* Not used yet in 64-bit kernel */ 40 41 42/* 43 * Writeback and invalidate the primary cache dcache before DMA. 44 * 45 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D, 46 * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only 47 * operate correctly if the internal data cache refill buffer is empty. These 48 * CACHE instructions should be separated from any potential data cache miss 49 * by a load instruction to an uncached address to empty the response buffer." 50 * (Revision 2.0 device errata from IDT available on http://www.idt.com/ 51 * in .pdf format.) 52 */ 53#undef R4600_V2_HIT_CACHEOP_WAR /* Not used yet in 64-bit kernel */ 54 55#ifdef CONFIG_CPU_R5432 56 57#define R5432_CP0_INTERRUPT_WAR 58 59#endif 60 61#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ 62 defined(CONFIG_SB1_PASS_2_WORKAROUNDS) 63 64#define BCM1250_M3_WAR 65 66#endif 67 68#endif /* _ASM_WAR_H */ 69