1/* 2 * cpu.h: Values of the PRId register used to match up 3 * various MIPS cpu types. 4 * 5 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 6 */ 7#ifndef _ASM_CPU_H 8#define _ASM_CPU_H 9 10#include <asm/cache.h> 11 12/* Assigned Company values for bits 23:16 of the PRId Register 13 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from 14 MTI, the PRId register is defined in this (backwards compatible) 15 way: 16 17 +----------------+----------------+----------------+----------------+ 18 | Company Options| Company ID | Processor ID | Revision | 19 +----------------+----------------+----------------+----------------+ 20 31 24 23 16 15 8 7 21 22 I don't have docs for all the previous processors, but my impression is 23 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64 24 spec. 25*/ 26 27#define PRID_COPT_MASK 0xff000000 28#define PRID_COMP_MASK 0x00ff0000 29#define PRID_IMP_MASK 0x0000ff00 30#define PRID_REV_MASK 0x000000ff 31 32#define PRID_COMP_LEGACY 0x000000 33#define PRID_COMP_MIPS 0x010000 34#define PRID_COMP_BROADCOM 0x020000 35#define PRID_COMP_ALCHEMY 0x030000 36#define PRID_COMP_SIBYTE 0x040000 37 38/* 39 * Assigned values for the product ID register. In order to detect a 40 * certain CPU type exactly eventually additional registers may need to 41 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY 42 */ 43#define PRID_IMP_R2000 0x0100 44#define PRID_IMP_AU1_REV1 0x0100 45#define PRID_IMP_AU1_REV2 0x0200 46#define PRID_IMP_R3000 0x0200 /* Same as R2000A */ 47#define PRID_IMP_R6000 0x0300 /* Same as R3000A */ 48#define PRID_IMP_R4000 0x0400 49#define PRID_IMP_R6000A 0x0600 50#define PRID_IMP_R10000 0x0900 51#define PRID_IMP_R4300 0x0b00 52#define PRID_IMP_VR41XX 0x0c00 53#define PRID_IMP_R12000 0x0e00 54#define PRID_IMP_R8000 0x1000 55#define PRID_IMP_R4600 0x2000 56#define PRID_IMP_R4700 0x2100 57#define PRID_IMP_TX39 0x2200 58#define PRID_IMP_R4640 0x2200 59#define PRID_IMP_R4650 0x2200 /* Same as R4640 */ 60#define PRID_IMP_R5000 0x2300 61#define PRID_IMP_TX49 0x2d00 62#define PRID_IMP_SONIC 0x2400 63#define PRID_IMP_MAGIC 0x2500 64#define PRID_IMP_RM7000 0x2700 65#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 66#define PRID_IMP_R5432 0x5400 67#define PRID_IMP_R5500 0x5500 68#define PRID_IMP_4KC 0x8000 69#define PRID_IMP_5KC 0x8100 70#define PRID_IMP_20KC 0x8200 71#define PRID_IMP_4KEC 0x8400 72#define PRID_IMP_4KSC 0x8600 73#define PRID_IMP_BCM4710 0x4000 74#define PRID_IMP_BCM3302 0x9000 75#define PRID_IMP_BCM3303 0x9100 76#define PRID_IMP_BCM3303 0x9100 77 78#define PRID_IMP_UNKNOWN 0xff00 79 80#define BCM330X(id) \ 81 (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \ 82 || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303))) 83 84/* 85 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 86 */ 87 88#define PRID_IMP_SB1 0x0100 89 90/* 91 * Definitions for 7:0 on legacy processors 92 */ 93 94 95#define PRID_REV_R4400 0x0040 96#define PRID_REV_R3000A 0x0030 97#define PRID_REV_R3000 0x0020 98#define PRID_REV_R2000A 0x0010 99#define PRID_REV_TX3912 0x0010 100#define PRID_REV_TX3922 0x0030 101#define PRID_REV_TX3927 0x0040 102#define PRID_REV_VR4111 0x0050 103#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */ 104#define PRID_REV_VR4121 0x0060 105#define PRID_REV_VR4122 0x0070 106#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */ 107#define PRID_REV_VR4131 0x0080 108 109/* 110 * FPU implementation/revision register (CP1 control register 0). 111 * 112 * +---------------------------------+----------------+----------------+ 113 * | 0 | Implementation | Revision | 114 * +---------------------------------+----------------+----------------+ 115 * 31 16 15 8 7 0 116 */ 117 118#define FPIR_IMP_NONE 0x0000 119 120#ifndef __ASSEMBLY__ 121 122extern void cpu_probe(void); 123extern void cpu_report(void); 124 125/* 126 * Capability and feature descriptor structure for MIPS CPU 127 */ 128struct mips_cpu { 129 unsigned int processor_id; 130 unsigned int fpu_id; 131 unsigned int cputype; 132 int isa_level; 133 int options; 134 int tlbsize; 135 struct cache_desc icache; /* Primary I-cache */ 136 struct cache_desc dcache; /* Primary D or combined I/D cache */ 137 struct cache_desc scache; /* Secondary cache */ 138 struct cache_desc tcache; /* Tertiary/split secondary cache */ 139}; 140 141extern struct mips_cpu mips_cpu; 142 143enum cputype { 144 CPU_UNKNOWN, 145 CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052, 146 CPU_R3081, CPU_R3081E, CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, 147 CPU_R4200, CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, 148 CPU_R6000, CPU_R6000A, CPU_R8000, CPU_R10000, CPU_R12000, CPU_R4300, 149 CPU_R4650, CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R4640, CPU_NEVADA, 150 CPU_RM7000, CPU_R5432, CPU_4KC, CPU_5KC, CPU_R4310, CPU_SB1, 151 CPU_TX3912, CPU_TX3922, CPU_TX3927, CPU_AU1000, CPU_4KEC, CPU_4KSC, 152 CPU_VR41XX, CPU_R5500, CPU_TX49XX, CPU_TX39XX, CPU_AU1500, CPU_20KC, 153 CPU_VR4111, CPU_VR4121, CPU_VR4122, CPU_VR4131, CPU_VR4181, CPU_VR4181A, 154 CPU_AU1100, CPU_BCM4710, CPU_BCM3302, CPU_LAST 155}; 156 157#endif /* !__ASSEMBLY__ */ 158 159/* 160 * ISA Level encodings 161 */ 162#define MIPS_CPU_ISA_I 0x00000001 163#define MIPS_CPU_ISA_II 0x00000002 164#define MIPS_CPU_ISA_III 0x00000003 165#define MIPS_CPU_ISA_IV 0x00000004 166#define MIPS_CPU_ISA_V 0x00000005 167#define MIPS_CPU_ISA_M32 0x00000020 168#define MIPS_CPU_ISA_M64 0x00000040 169 170/* 171 * CPU Option encodings 172 */ 173#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */ 174/* Leave a spare bit for variant MMU types... */ 175#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */ 176#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */ 177#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */ 178#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */ 179#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */ 180#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */ 181#define MIPS_CPU_MIPS16 0x00000100 /* code compression */ 182#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */ 183#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */ 184#define MIPS_CPU_CACHE_CDEX 0x00000800 /* Create_Dirty_Exclusive CACHE op */ 185#define MIPS_CPU_MCHECK 0x00001000 /* Machine check exception */ 186#define MIPS_CPU_EJTAG 0x00002000 /* EJTAG exception */ 187#define MIPS_CPU_NOFPUEX 0x00004000 /* no FPU exception */ 188 189#endif /* _ASM_CPU_H */ 190