1/* $Id: dvma.h,v 1.1.1.1 2008/10/15 03:29:06 james26_jang Exp $ 2 * include/asm-m68k/dma.h 3 * 4 * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu) 5 * 6 * Hacked to fit Sun3x needs by Thomas Bogendoerfer 7 */ 8 9#ifndef __M68K_DVMA_H 10#define __M68K_DVMA_H 11 12#include <linux/config.h> 13 14#define DVMA_PAGE_SHIFT 13 15#define DVMA_PAGE_SIZE (1UL << DVMA_PAGE_SHIFT) 16#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1)) 17#define DVMA_PAGE_ALIGN(addr) (((addr)+DVMA_PAGE_SIZE-1)&DVMA_PAGE_MASK) 18 19extern void dvma_init(void); 20extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr, 21 int len); 22 23#define dvma_malloc(x) dvma_malloc_align(x, 0) 24#define dvma_map(x, y) dvma_map_align(x, y, 0) 25 26extern unsigned long dvma_map_align(unsigned long kaddr, int len, 27 int align); 28extern void *dvma_malloc_align(unsigned long len, unsigned long align); 29 30extern void dvma_unmap(void *baddr); 31extern void dvma_free(void *vaddr); 32 33 34#ifdef CONFIG_SUN3 35/* sun3 dvma page support */ 36 37/* memory and pmegs potentially reserved for dvma */ 38#define DVMA_PMEG_START 10 39#define DVMA_PMEG_END 16 40#define DVMA_START 0xf00000 41#define DVMA_END 0xfe0000 42#define DVMA_SIZE (DVMA_END-DVMA_START) 43#define IOMMU_TOTAL_ENTRIES 128 44#define IOMMU_ENTRIES 120 45 46/* empirical kludge -- dvma regions only seem to work right on 0x10000 47 byte boundries */ 48#define DVMA_REGION_SIZE 0x10000 49#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \ 50 ~(DVMA_REGION_SIZE-1)) 51 52/* virt <-> phys conversions */ 53#define dvma_vtop(x) ((unsigned long)(x) & 0xffffff) 54#define dvma_ptov(x) ((unsigned long)(x) | 0xf000000) 55#define dvma_vtob(x) dvma_vtop(x) 56#define dvma_btov(x) dvma_ptov(x) 57 58extern inline int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len) 59{ 60 return 0; 61} 62 63extern unsigned long dvma_page(unsigned long kaddr, unsigned long vaddr); 64 65#else /* Sun3x */ 66 67/* sun3x dvma page support */ 68 69#define DVMA_START 0x0 70#define DVMA_END 0xf00000 71#define DVMA_SIZE (DVMA_END-DVMA_START) 72#define IOMMU_TOTAL_ENTRIES 2048 73/* the prom takes the top meg */ 74#define IOMMU_ENTRIES (IOMMU_TOTAL_ENTRIES - 0x80) 75 76#define dvma_vtob(x) ((unsigned long)(x) & 0x00ffffff) 77#define dvma_btov(x) ((unsigned long)(x) | 0xff000000) 78 79extern int dvma_map_cpu(unsigned long kaddr, unsigned long vaddr, int len); 80 81 82 83/* everything below this line is specific to dma used for the onboard 84 ESP scsi on sun3x */ 85 86/* Structure to describe the current status of DMA registers on the Sparc */ 87struct sparc_dma_registers { 88 __volatile__ unsigned long cond_reg; /* DMA condition register */ 89 __volatile__ unsigned long st_addr; /* Start address of this transfer */ 90 __volatile__ unsigned long cnt; /* How many bytes to transfer */ 91 __volatile__ unsigned long dma_test; /* DMA test register */ 92}; 93 94/* DVMA chip revisions */ 95enum dvma_rev { 96 dvmarev0, 97 dvmaesc1, 98 dvmarev1, 99 dvmarev2, 100 dvmarev3, 101 dvmarevplus, 102 dvmahme 103}; 104 105#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1) 106 107/* Linux DMA information structure, filled during probe. */ 108struct Linux_SBus_DMA { 109 struct Linux_SBus_DMA *next; 110 struct linux_sbus_device *SBus_dev; 111 struct sparc_dma_registers *regs; 112 113 /* Status, misc info */ 114 int node; /* Prom node for this DMA device */ 115 int running; /* Are we doing DMA now? */ 116 int allocated; /* Are we "owned" by anyone yet? */ 117 118 /* Transfer information. */ 119 unsigned long addr; /* Start address of current transfer */ 120 int nbytes; /* Size of current transfer */ 121 int realbytes; /* For splitting up large transfers, etc. */ 122 123 /* DMA revision */ 124 enum dvma_rev revision; 125}; 126 127extern struct Linux_SBus_DMA *dma_chain; 128 129/* Broken hardware... */ 130#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1) 131#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1) 132 133/* Fields in the cond_reg register */ 134/* First, the version identification bits */ 135#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ 136#define DMA_VERS0 0x00000000 /* Sunray DMA version */ 137#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ 138#define DMA_VERS1 0x80000000 /* DMA rev 1 */ 139#define DMA_VERS2 0xa0000000 /* DMA rev 2 */ 140#define DMA_VERHME 0xb0000000 /* DMA hme gate array */ 141#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ 142 143#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ 144#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ 145#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ 146#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ 147#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ 148#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ 149#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ 150#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ 151#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ 152#define DMA_ST_WRITE 0x00000100 /* write from device to memory */ 153#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ 154#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ 155#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */ 156#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */ 157#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ 158#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ 159#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ 160#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ 161#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ 162#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ 163#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ 164#define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */ 165#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ 166#define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */ 167#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */ 168#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */ 169#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */ 170#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ 171#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ 172#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ 173#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ 174#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ 175#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ 176#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ 177#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */ 178#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ 179#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ 180 181/* Values describing the burst-size property from the PROM */ 182#define DMA_BURST1 0x01 183#define DMA_BURST2 0x02 184#define DMA_BURST4 0x04 185#define DMA_BURST8 0x08 186#define DMA_BURST16 0x10 187#define DMA_BURST32 0x20 188#define DMA_BURST64 0x40 189#define DMA_BURSTBITS 0x7f 190 191/* Determine highest possible final transfer address given a base */ 192#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL)) 193 194/* Yes, I hack a lot of elisp in my spare time... */ 195#define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR)) 196#define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))) 197#define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE)) 198#define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE))) 199#define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB))) 200#define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB))) 201#define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV)) 202#define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr)) 203#define DMA_BEGINDMA_W(regs) \ 204 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB)))) 205#define DMA_BEGINDMA_R(regs) \ 206 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE))))) 207 208/* For certain DMA chips, we need to disable ints upon irq entry 209 * and turn them back on when we are done. So in any ESP interrupt 210 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT 211 * when leaving the handler. You have been warned... 212 */ 213#define DMA_IRQ_ENTRY(dma, dregs) do { \ 214 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \ 215 } while (0) 216 217#define DMA_IRQ_EXIT(dma, dregs) do { \ 218 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \ 219 } while(0) 220 221/* Reset the friggin' thing... */ 222#define DMA_RESET(dma) do { \ 223 struct sparc_dma_registers *regs = dma->regs; \ 224 /* Let the current FIFO drain itself */ \ 225 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \ 226 /* Reset the logic */ \ 227 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \ 228 __delay(400); /* let the bits set ;) */ \ 229 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \ 230 sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \ 231 /* Enable FAST transfers if available */ \ 232 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \ 233 dma->running = 0; \ 234} while(0) 235 236 237#endif /* !CONFIG_SUN3 */ 238 239#endif /* !(__M68K_DVMA_H) */ 240