1/* $Id: addrs.h,v 1.1.1.1 2008/10/15 03:29:03 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. 8 */ 9 10#ifndef _ASM_IA64_SN_SN1_ADDRS_H 11#define _ASM_IA64_SN_SN1_ADDRS_H 12 13#include <linux/config.h> 14 15#ifdef CONFIG_IA64_SGI_SN1 16/* 17 * SN1 (on a TRex) Address map 18 * 19 * This file contains a set of definitions and macros which are used 20 * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, 21 * and UNCAC) used by the SN1 architecture. It also contains addresses 22 * for "major" statically locatable PROM/Kernel data structures, such as 23 * the partition table, the configuration data structure, etc. 24 * We make an implicit assumption that the processor using this file 25 * follows the R12K's provisions for specifying uncached attributes; 26 * should this change, the base registers may very well become processor- 27 * dependent. 28 * 29 * For more information on the address spaces, see the "Local Resources" 30 * chapter of the Hub specification. 31 * 32 * NOTE: This header file is included both by C and by assembler source 33 * files. Please bracket any language-dependent definitions 34 * appropriately. 35 */ 36 37 38/* 39 * Some of the macros here need to be casted to appropriate types when used 40 * from C. They definitely must not be casted from assembly language so we 41 * use some new ANSI preprocessor stuff to paste these on where needed. 42 */ 43 44#define CAC_BASE 0xe000000000000000 45#define HSPEC_BASE 0xc0000b0000000000 46#define HSPEC_SWIZ_BASE 0xc000030000000000 47#define IO_BASE 0xc0000a0000000000 48#define IO_SWIZ_BASE 0xc000020000000000 49#define MSPEC_BASE 0xc000090000000000 50#define UNCAC_BASE 0xc000000000000000 51#define TO_PHYS_MASK 0x000000ffffffffff 52 53#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) 54#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) 55#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) 56#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) 57#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) 58 59 60/* 61 * The following couple of definitions will eventually need to be variables, 62 * since the amount of address space assigned to each node depends on 63 * whether the system is running in N-mode (more nodes with less memory) 64 * or M-mode (fewer nodes with more memory). We expect that it will 65 * be a while before we need to make this decision dynamically, though, 66 * so for now we just use defines bracketed by an ifdef. 67 */ 68 69#if defined(N_MODE) 70 71#define NODE_SIZE_BITS 32 72#define BWIN_SIZE_BITS 28 73 74#define NASID_BITS 8 75#define NASID_BITMASK (0xffLL) 76#define NASID_SHFT 32 77#define NASID_META_BITS 1 78#define NASID_LOCAL_BITS 7 79 80#define BDDIR_UPPER_MASK (UINT64_CAST 0x1ffffff << 4) 81#define BDECC_UPPER_MASK (UINT64_CAST 0x1fffffff ) 82 83#else /* !defined(N_MODE), assume that M-mode is desired */ 84 85#define NODE_SIZE_BITS 33 86#define BWIN_SIZE_BITS 29 87 88#define NASID_BITMASK (0x7fLL) 89#define NASID_BITS 7 90#define NASID_SHFT 33 91#define NASID_META_BITS 0 92#define NASID_LOCAL_BITS 7 93 94#define BDDIR_UPPER_MASK (UINT64_CAST 0x3ffffff << 4) 95#define BDECC_UPPER_MASK (UINT64_CAST 0x3fffffff) 96 97#endif /* defined(N_MODE) */ 98 99#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) 100 101#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) 102#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ 103 NASID_SHFT) & NASID_BITMASK) 104 105#ifndef __ASSEMBLY__ 106#define NODE_SWIN_BASE(nasid, widget) \ 107 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ 108 : RAW_NODE_SWIN_BASE(nasid, widget)) 109#else 110#define NODE_SWIN_BASE(nasid, widget) \ 111 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 112#endif /* __ASSEMBLY__ */ 113 114/* 115 * The following definitions pertain to the IO special address 116 * space. They define the location of the big and little windows 117 * of any given node. 118 */ 119 120#define BWIN_INDEX_BITS 3 121#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) 122#define BWIN_SIZEMASK (BWIN_SIZE - 1) 123#define BWIN_WIDGET_MASK 0x7 124#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) 125#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ 126 (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) 127 128#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) 129#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 130/* 131 * Verify if addr belongs to large window address of node with "nasid" 132 * 133 * 134 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical 135 * address 136 * 137 * 138 */ 139 140#define NODE_BWIN_ADDR(nasid, addr) \ 141 (((addr) >= NODE_BWIN_BASE0(nasid)) && \ 142 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ 143 BWIN_SIZE))) 144 145/* 146 * The following define the major position-independent aliases used 147 * in SN1. 148 * CALIAS -- Varies in size, points to the first n bytes of memory 149 * on the reader's node. 150 */ 151 152#define CALIAS_BASE CAC_BASE 153 154 155 156#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ 157 ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) 158 159#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) 160 161 162 163/* 164 * needed by symmon so it needs to be outside #if PROM 165 * (see also POD_ELSCSIZE) 166 */ 167#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x020e0000) 168#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x020e0800) 169#define IP27PROM_ELSC_BASE_C PHYS_TO_K0(0x020e1000) 170#define IP27PROM_ELSC_BASE_D PHYS_TO_K0(0x020e1800) 171#define IP27PROM_ELSC_SHFT 11 172#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT) 173 174#define FREEMEM_BASE PHYS_TO_K0(0x4000000) 175 176#define IO6PROM_STACK_SHFT 14 /* stack per cpu */ 177#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT) 178 179 180#define KL_UART_BASE LOCAL_HSPEC(HSPEC_UART_0) /* base of UART regs */ 181#define KL_UART_CMD LOCAL_HSPEC(HSPEC_UART_0) /* UART command reg */ 182#define KL_UART_DATA LOCAL_HSPEC(HSPEC_UART_1) /* UART data reg */ 183 184#if !__ASSEMBLY__ 185/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc 186 * CACHE_ERR_SP_PTR could either contain an address to the stack, or 187 * the stack could start at CACHE_ERR_SP_PTR 188 */ 189#define CACHE_ERR_EFRAME 0x400 190 191#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE) 192#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */ 193#define CACHE_ERR_IBASE_PTR (0x1000 - 40) 194#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) 195#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) 196 197#endif /* !__ASSEMBLY__ */ 198 199 200 201#define _ARCSPROM 202 203#ifdef _STANDALONE 204 205/* 206 * The PROM needs to pass the device base address and the 207 * device pci cfg space address to the device drivers during 208 * install. The COMPONENT->Key field is used for this purpose. 209 * Macros needed by SN1 device drivers to convert the 210 * COMPONENT->Key field to the respective base address. 211 * Key field looks as follows: 212 * 213 * +----------------------------------------------------+ 214 * |devnasid | widget |pciid |hubwidid|hstnasid | adap | 215 * | 2 | 1 | 1 | 1 | 2 | 1 | 216 * +----------------------------------------------------+ 217 * | | | | | | | 218 * 64 48 40 32 24 8 0 219 * 220 * These are used by standalone drivers till the io infrastructure 221 * is in place. 222 */ 223 224#ifndef __ASSEMBLY__ 225 226#define uchar unsigned char 227 228#define KEY_DEVNASID_SHFT 48 229#define KEY_WIDID_SHFT 40 230#define KEY_PCIID_SHFT 32 231#define KEY_HUBWID_SHFT 24 232#define KEY_HSTNASID_SHFT 8 233 234#define MK_SN0_KEY(nasid, widid, pciid) \ 235 ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\ 236 ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\ 237 ((__psunsigned_t)pciid) << KEY_PCIID_SHFT) 238 239#define ADD_HUBWID_KEY(key,hubwid)\ 240 (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT)) 241 242#define ADD_HSTNASID_KEY(key,hstnasid)\ 243 (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT)) 244 245#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT)) 246#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT)) 247#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT)) 248#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT)) 249#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT)) 250 251#define PCI_64_TARGID_SHFT 60 252 253#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ 254 GET_WIDID_FROM_KEY(key))\ 255 | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key))) 256 257#define GET_PCICFGBASE_FROM_KEY(key) \ 258 (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ 259 GET_WIDID_FROM_KEY(key))\ 260 | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key))) 261 262#define GET_WIDBASE_FROM_KEY(key) \ 263 (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ 264 GET_WIDID_FROM_KEY(key))) 265 266#define PUT_INSTALL_STATUS(c,s) c->Revision = s 267#define GET_INSTALL_STATUS(c) c->Revision 268 269#endif /* __ASSEMBLY__ */ 270 271#endif /* _STANDALONE */ 272#endif /* CONFIG_IA64_SGI_SN1 */ 273 274#endif /* _ASM_IA64_SN_SN1_ADDRS_H */ 275