1/* $Id: pci_defs.h,v 1.1.1.1 2008/10/15 03:29:03 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved. 8 */ 9#ifndef _ASM_SN_PCI_PCI_DEFS_H 10#define _ASM_SN_PCI_PCI_DEFS_H 11 12#include <linux/config.h> 13 14/* defines for the PCI bus architecture */ 15 16/* Bit layout of address fields for Type-1 17 * Configuration Space cycles. 18 */ 19#define PCI_TYPE0_SLOT_MASK 0xFFFFF800 20#define PCI_TYPE0_FUNC_MASK 0x00000700 21#define PCI_TYPE0_REG_MASK 0x000000FF 22 23#define PCI_TYPE0_SLOT_SHFT 11 24#define PCI_TYPE0_FUNC_SHFT 8 25#define PCI_TYPE0_REG_SHFT 0 26 27#define PCI_TYPE0_FUNC(a) (((a) & PCI_TYPE0_FUNC_MASK) >> PCI_TYPE0_FUNC_SHFT) 28#define PCI_TYPE0_REG(a) (((a) & PCI_TYPE0_REG_MASK) >> PCI_TYPE0_REG_SHFT) 29 30#define PCI_TYPE0(s,f,r) ((((1<<(s)) << PCI_TYPE0_SLOT_SHFT) & PCI_TYPE0_SLOT_MASK) |\ 31 (((f) << PCI_TYPE0_FUNC_SHFT) & PCI_TYPE0_FUNC_MASK) |\ 32 (((r) << PCI_TYPE0_REG_SHFT) & PCI_TYPE0_REG_MASK)) 33 34/* Bit layout of address fields for Type-1 35 * Configuration Space cycles. 36 * NOTE: I'm including the byte offset within 37 * the 32-bit word as part of the register 38 * number as an extension of the layout in 39 * the PCI spec. 40 */ 41#define PCI_TYPE1_BUS_MASK 0x00FF0000 42#define PCI_TYPE1_SLOT_MASK 0x0000F100 43#define PCI_TYPE1_FUNC_MASK 0x00000700 44#define PCI_TYPE1_REG_MASK 0x000000FF 45 46#define PCI_TYPE1_BUS_SHFT 16 47#define PCI_TYPE1_SLOT_SHFT 11 48#define PCI_TYPE1_FUNC_SHFT 8 49#define PCI_TYPE1_REG_SHFT 0 50 51#define PCI_TYPE1_BUS(a) (((a) & PCI_TYPE1_BUS_MASK) >> PCI_TYPE1_BUS_SHFT) 52#define PCI_TYPE1_SLOT(a) (((a) & PCI_TYPE1_SLOT_MASK) >> PCI_TYPE1_SLOT_SHFT) 53#define PCI_TYPE1_FUNC(a) (((a) & PCI_TYPE1_FUNC_MASK) >> PCI_TYPE1_FUNC_SHFT) 54#define PCI_TYPE1_REG(a) (((a) & PCI_TYPE1_REG_MASK) >> PCI_TYPE1_REG_SHFT) 55 56#define PCI_TYPE1(b,s,f,r) ((((b) << PCI_TYPE1_BUS_SHFT) & PCI_TYPE1_BUS_MASK) |\ 57 (((s) << PCI_TYPE1_SLOT_SHFT) & PCI_TYPE1_SLOT_MASK) |\ 58 (((f) << PCI_TYPE1_FUNC_SHFT) & PCI_TYPE1_FUNC_MASK) |\ 59 (((r) << PCI_TYPE1_REG_SHFT) & PCI_TYPE1_REG_MASK)) 60 61/* Byte offsets of registers in CFG space 62 */ 63#define PCI_CFG_VENDOR_ID 0x00 /* Vendor ID (2 bytes) */ 64#define PCI_CFG_DEVICE_ID 0x02 /* Device ID (2 bytes) */ 65 66#define PCI_CFG_COMMAND 0x04 /* Command (2 bytes) */ 67#define PCI_CFG_STATUS 0x06 /* Status (2 bytes) */ 68 69/* NOTE: if you are using a C "switch" statement to 70 * differentiate between the Config space registers, be 71 * aware that PCI_CFG_CLASS_CODE and PCI_CFG_BASE_CLASS 72 * are the same offset. 73 */ 74#define PCI_CFG_REV_ID 0x08 /* Revision Id (1 byte) */ 75#define PCI_CFG_CLASS_CODE 0x09 /* Class Code (3 bytes) */ 76#define PCI_CFG_BASE_CLASS 0x09 /* Base Class (1 byte) */ 77#define PCI_CFG_SUB_CLASS 0x0A /* Sub Class (1 byte) */ 78#define PCI_CFG_PROG_IF 0x0B /* Prog Interface (1 byte) */ 79 80#define PCI_CFG_CACHE_LINE 0x0C /* Cache line size (1 byte) */ 81#define PCI_CFG_LATENCY_TIMER 0x0D /* Latency Timer (1 byte) */ 82#define PCI_CFG_HEADER_TYPE 0x0E /* Header Type (1 byte) */ 83#define PCI_CFG_BIST 0x0F /* Built In Self Test */ 84 85#define PCI_CFG_BASE_ADDR_0 0x10 /* Base Address (4 bytes) */ 86#define PCI_CFG_BASE_ADDR_1 0x14 /* Base Address (4 bytes) */ 87#define PCI_CFG_BASE_ADDR_2 0x18 /* Base Address (4 bytes) */ 88#define PCI_CFG_BASE_ADDR_3 0x1C /* Base Address (4 bytes) */ 89#define PCI_CFG_BASE_ADDR_4 0x20 /* Base Address (4 bytes) */ 90#define PCI_CFG_BASE_ADDR_5 0x24 /* Base Address (4 bytes) */ 91 92#define PCI_CFG_BASE_ADDR_OFF 0x04 /* Base Address Offset (1..5)*/ 93#define PCI_CFG_BASE_ADDR(n) (PCI_CFG_BASE_ADDR_0 + (n)*PCI_CFG_BASE_ADDR_OFF) 94#define PCI_CFG_BASE_ADDRS 6 /* up to this many BASE regs */ 95 96#define PCI_CFG_CARDBUS_CIS 0x28 /* Cardbus CIS Pointer (4B) */ 97 98#define PCI_CFG_SUBSYS_VEND_ID 0x2C /* Subsystem Vendor ID (2B) */ 99#define PCI_CFG_SUBSYS_ID 0x2E /* Subsystem ID */ 100 101#define PCI_EXPANSION_ROM 0x30 /* Expansion Rom Base (4B) */ 102 103#define PCI_INTR_LINE 0x3C /* Interrupt Line (1B) */ 104#define PCI_INTR_PIN 0x3D /* Interrupt Pin (1B) */ 105#define PCI_MIN_GNT 0x3E /* Minimum Grant (1B) */ 106#define PCI_MAX_LAT 0x3F /* Maximum Latency (1B) */ 107 108#define PCI_CFG_VEND_SPECIFIC 0x40 /* first vendor specific reg */ 109 110/* layout for Type 0x01 headers */ 111 112#define PCI_CFG_PPB_BUS_PRI 0x18 /* immediate upstream bus # */ 113#define PCI_CFG_PPB_BUS_SEC 0x19 /* immediate downstream bus # */ 114#define PCI_CFG_PPB_BUS_SUB 0x1A /* last downstream bus # */ 115#define PCI_CFG_PPB_SEC_LAT 0x1B /* latency timer for SEC bus */ 116#define PCI_CFG_PPB_IOBASE 0x1C /* IO Base Addr bits 12..15 */ 117#define PCI_CFG_PPB_IOLIM 0x1D /* IO Limit Addr bits 12..15 */ 118#define PCI_CFG_PPB_SEC_STAT 0x1E /* Secondary Status */ 119#define PCI_CFG_PPB_MEMBASE 0x20 /* MEM Base Addr bits 16..31 */ 120#define PCI_CFG_PPB_MEMLIM 0x22 /* MEM Limit Addr bits 16..31 */ 121#define PCI_CFG_PPB_MEMPFBASE 0x24 /* PfMEM Base Addr bits 16..31 */ 122#define PCI_CFG_PPB_MEMPFLIM 0x26 /* PfMEM Limit Addr bits 16..31 */ 123#define PCI_CFG_PPB_MEMPFBASEHI 0x28 /* PfMEM Base Addr bits 32..63 */ 124#define PCI_CFG_PPB_MEMPFLIMHI 0x2C /* PfMEM Limit Addr bits 32..63 */ 125#define PCI_CFG_PPB_IOBASEHI 0x30 /* IO Base Addr bits 16..31 */ 126#define PCI_CFG_PPB_IOLIMHI 0x32 /* IO Limit Addr bits 16..31 */ 127#define PCI_CFG_PPB_SUB_VENDOR 0x34 /* Subsystem Vendor ID */ 128#define PCI_CFG_PPB_SUB_DEVICE 0x36 /* Subsystem Device ID */ 129#define PCI_CFG_PPB_INT_PIN 0x3D /* Interrupt Pin */ 130#define PCI_CFG_PPB_BRIDGE_CTRL 0x3E /* Bridge Control */ 131#define PCI_CFG_PPB_CHIP_CTRL 0x40 132#define PCI_CFG_PPB_DIAG_CTRL 0x41 133#define PCI_CFG_PPB_ARB_CTRL 0x42 134#define PCI_CFG_PPB_SERR_DISABLE 0x64 135#define PCI_CFG_PPB_CLK2_CTRL 0x68 136#define PCI_CFG_PPB_SERR_STATUS 0x6A 137 138/* Command Register layout (0x04) */ 139#define PCI_CMD_IO_SPACE 0x001 /* I/O Space device */ 140#define PCI_CMD_MEM_SPACE 0x002 /* Memory Space */ 141#define PCI_CMD_BUS_MASTER 0x004 /* Bus Master */ 142#define PCI_CMD_SPEC_CYCLES 0x008 /* Special Cycles */ 143#define PCI_CMD_MEMW_INV_ENAB 0x010 /* Memory Write Inv Enable */ 144#define PCI_CMD_VGA_PALETTE_SNP 0x020 /* VGA Palette Snoop */ 145#define PCI_CMD_PAR_ERR_RESP 0x040 /* Parity Error Response */ 146#define PCI_CMD_WAIT_CYCLE_CTL 0x080 /* Wait Cycle Control */ 147#define PCI_CMD_SERR_ENABLE 0x100 /* SERR# Enable */ 148#define PCI_CMD_F_BK_BK_ENABLE 0x200 /* Fast Back-to-Back Enable */ 149 150/* Status Register Layout (0x06) */ 151#define PCI_STAT_PAR_ERR_DET 0x8000 /* Detected Parity Error */ 152#define PCI_STAT_SYS_ERR 0x4000 /* Signaled System Error */ 153#define PCI_STAT_RCVD_MSTR_ABT 0x2000 /* Received Master Abort */ 154#define PCI_STAT_RCVD_TGT_ABT 0x1000 /* Received Target Abort */ 155#define PCI_STAT_SGNL_TGT_ABT 0x0800 /* Signaled Target Abort */ 156 157#define PCI_STAT_DEVSEL_TIMING 0x0600 /* DEVSEL Timing Mask */ 158#define DEVSEL_TIMING(_x) (((_x) >> 9) & 3) /* devsel tim macro */ 159#define DEVSEL_FAST 0 /* Fast timing */ 160#define DEVSEL_MEDIUM 1 /* Medium timing */ 161#define DEVSEL_SLOW 2 /* Slow timing */ 162 163#define PCI_STAT_DATA_PAR_ERR 0x0100 /* Data Parity Err Detected */ 164#define PCI_STAT_F_BK_BK_CAP 0x0080 /* Fast Back-to-Back Capable */ 165#define PCI_STAT_UDF_SUPP 0x0040 /* UDF Supported */ 166#define PCI_STAT_66MHZ_CAP 0x0020 /* 66 MHz Capable */ 167 168/* BIST Register Layout (0x0F) */ 169#define PCI_BIST_BIST_CAP 0x80 /* BIST Capable */ 170#define PCI_BIST_START_BIST 0x40 /* Start BIST */ 171#define PCI_BIST_CMPLTION_MASK 0x0F /* COMPLETION MASK */ 172#define PCI_BIST_CMPL_OK 0x00 /* 0 value is completion OK */ 173 174/* Base Address Register 0x10 */ 175#define PCI_BA_IO_SPACE 0x1 /* I/O Space Marker */ 176#define PCI_BA_MEM_LOCATION 0x6 /* 2 bits for location avail */ 177#define PCI_BA_MEM_32BIT 0x0 /* Anywhere in 32bit space */ 178#define PCI_BA_MEM_1MEG 0x2 /* Locate below 1 Meg */ 179#define PCI_BA_MEM_64BIT 0x4 /* Anywhere in 64bit space */ 180#define PCI_BA_PREFETCH 0x8 /* Prefetchable, no side effect */ 181 182/* PIO interface macros */ 183 184#ifndef IOC3_EMULATION 185 186#define PCI_INB(x) (*((volatile char*)x)) 187#define PCI_INH(x) (*((volatile short*)x)) 188#define PCI_INW(x) (*((volatile int*)x)) 189#define PCI_OUTB(x,y) (*((volatile char*)x) = y) 190#define PCI_OUTH(x,y) (*((volatile short*)x) = y) 191#define PCI_OUTW(x,y) (*((volatile int*)x) = y) 192 193#else 194 195extern uint pci_read(void * address, int type); 196extern void pci_write(void * address, int data, int type); 197 198#define BYTE 1 199#define HALF 2 200#define WORD 4 201 202#define PCI_INB(x) pci_read((void *)(x),BYTE) 203#define PCI_INH(x) pci_read((void *)(x),HALF) 204#define PCI_INW(x) pci_read((void *)(x),WORD) 205#define PCI_OUTB(x,y) pci_write((void *)(x),(y),BYTE) 206#define PCI_OUTH(x,y) pci_write((void *)(x),(y),HALF) 207#define PCI_OUTW(x,y) pci_write((void *)(x),(y),WORD) 208 209#endif /* !IOC3_EMULATION */ 210 /* effects on reads, merges */ 211 212#ifdef CONFIG_SGI_IP22 213#define BYTECOUNT_W_GIO 0xbf400000 214#endif 215 216 217#define CFG1_ADDR_REGISTER_MASK 0x000000fc 218#define CFG1_ADDR_FUNCTION_MASK 0x00000700 219#define CFG1_ADDR_DEVICE_MASK 0x0000f800 220#define CFG1_ADDR_BUS_MASK 0x00ff0000 221 222#define CFG1_REGISTER_SHIFT 2 223#define CFG1_FUNCTION_SHIFT 8 224#define CFG1_DEVICE_SHIFT 11 225#define CFG1_BUS_SHIFT 16 226 227#ifdef CONFIG_SGI_IP32 228#define PCI_CONFIG_BITS 0xfe0085ff 229#define PCI_CONTROL_MRMRA_ENABLE 0x00000800 230#define PCI_FIRST_IO_ADDR 0x1000 231#define PCI_IO_MAP_INCR 0x1000 232#endif /* CONFIG_SGI_IP32 */ 233 234#endif /* _ASM_SN_PCI_PCI_DEFS_H */ 235