1#ifndef __ALPHA_PCI_H 2#define __ALPHA_PCI_H 3 4#ifdef __KERNEL__ 5 6#include <linux/spinlock.h> 7#include <asm/scatterlist.h> 8#include <asm/machvec.h> 9 10/* 11 * The following structure is used to manage multiple PCI busses. 12 */ 13 14struct pci_dev; 15struct pci_bus; 16struct resource; 17struct pci_iommu_arena; 18struct page; 19 20/* A controller. Used to manage multiple PCI busses. */ 21 22struct pci_controller { 23 struct pci_controller *next; 24 struct pci_bus *bus; 25 struct resource *io_space; 26 struct resource *mem_space; 27 28 /* The following are for reporting to userland. The invariant is 29 that if we report a BWX-capable dense memory, we do not report 30 a sparse memory at all, even if it exists. */ 31 unsigned long sparse_mem_base; 32 unsigned long dense_mem_base; 33 unsigned long sparse_io_base; 34 unsigned long dense_io_base; 35 36 /* This one's for the kernel only. It's in KSEG somewhere. */ 37 unsigned long config_space_base; 38 39 unsigned int index; 40 unsigned int first_busno; 41 unsigned int last_busno; 42 43 struct pci_iommu_arena *sg_pci; 44 struct pci_iommu_arena *sg_isa; 45}; 46 47/* Override the logic in pci_scan_bus for skipping already-configured 48 bus numbers. */ 49 50#define pcibios_assign_all_busses() 1 51 52#define PCIBIOS_MIN_IO alpha_mv.min_io_address 53#define PCIBIOS_MIN_MEM alpha_mv.min_mem_address 54 55extern void pcibios_set_master(struct pci_dev *dev); 56 57extern inline void pcibios_penalize_isa_irq(int irq) 58{ 59 /* We don't do dynamic PCI IRQ allocation */ 60} 61 62/* IOMMU controls. */ 63 64/* The PCI address space does not equal the physical memory address space. 65 The networking and block device layers use this boolean for bounce buffer 66 decisions. */ 67#define PCI_DMA_BUS_IS_PHYS 0 68 69/* Allocate and map kernel buffer using consistant mode DMA for PCI 70 device. Returns non-NULL cpu-view pointer to the buffer if 71 successful and sets *DMA_ADDRP to the pci side dma address as well, 72 else DMA_ADDRP is undefined. */ 73 74extern void *pci_alloc_consistent(struct pci_dev *, size_t, dma_addr_t *); 75 76/* Free and unmap a consistant DMA buffer. CPU_ADDR and DMA_ADDR must 77 be values that were returned from pci_alloc_consistant. SIZE must 78 be the same as what as passed into pci_alloc_consistant. 79 References to the memory and mappings assosciated with CPU_ADDR or 80 DMA_ADDR past this call are illegal. */ 81 82extern void pci_free_consistent(struct pci_dev *, size_t, void *, dma_addr_t); 83 84/* Map a single buffer of the indicate size for PCI DMA in streaming 85 mode. The 32-bit PCI bus mastering address to use is returned. 86 Once the device is given the dma address, the device owns this memory 87 until either pci_unmap_single or pci_dma_sync_single is performed. */ 88 89extern dma_addr_t pci_map_single(struct pci_dev *, void *, size_t, int); 90 91/* Likewise, but for a page instead of an address. */ 92extern dma_addr_t pci_map_page(struct pci_dev *, struct page *, 93 unsigned long, size_t, int); 94 95/* Unmap a single streaming mode DMA translation. The DMA_ADDR and 96 SIZE must match what was provided for in a previous pci_map_single 97 call. All other usages are undefined. After this call, reads by 98 the cpu to the buffer are guarenteed to see whatever the device 99 wrote there. */ 100 101extern void pci_unmap_single(struct pci_dev *, dma_addr_t, size_t, int); 102extern void pci_unmap_page(struct pci_dev *, dma_addr_t, size_t, int); 103 104/* pci_unmap_{single,page} is not a nop, thus... */ 105#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ 106 dma_addr_t ADDR_NAME; 107#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ 108 __u32 LEN_NAME; 109#define pci_unmap_addr(PTR, ADDR_NAME) \ 110 ((PTR)->ADDR_NAME) 111#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ 112 (((PTR)->ADDR_NAME) = (VAL)) 113#define pci_unmap_len(PTR, LEN_NAME) \ 114 ((PTR)->LEN_NAME) 115#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ 116 (((PTR)->LEN_NAME) = (VAL)) 117 118/* Map a set of buffers described by scatterlist in streaming mode for 119 PCI DMA. This is the scather-gather version of the above 120 pci_map_single interface. Here the scatter gather list elements 121 are each tagged with the appropriate PCI dma address and length. 122 They are obtained via sg_dma_{address,length}(SG). 123 124 NOTE: An implementation may be able to use a smaller number of DMA 125 address/length pairs than there are SG table elements. (for 126 example via virtual mapping capabilities) The routine returns the 127 number of addr/length pairs actually used, at most nents. 128 129 Device ownership issues as mentioned above for pci_map_single are 130 the same here. */ 131 132extern int pci_map_sg(struct pci_dev *, struct scatterlist *, int, int); 133 134/* Unmap a set of streaming mode DMA translations. Again, cpu read 135 rules concerning calls here are the same as for pci_unmap_single() 136 above. */ 137 138extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int, int); 139 140/* Make physical memory consistant for a single streaming mode DMA 141 translation after a transfer. 142 143 If you perform a pci_map_single() but wish to interrogate the 144 buffer using the cpu, yet do not wish to teardown the PCI dma 145 mapping, you must call this function before doing so. At the next 146 point you give the PCI dma address back to the card, the device 147 again owns the buffer. */ 148 149static inline void 150pci_dma_sync_single(struct pci_dev *dev, dma_addr_t dma_addr, long size, 151 int direction) 152{ 153 /* Nothing to do. */ 154} 155 156/* Make physical memory consistant for a set of streaming mode DMA 157 translations after a transfer. The same as pci_dma_sync_single but 158 for a scatter-gather list, same rules and usage. */ 159 160static inline void 161pci_dma_sync_sg(struct pci_dev *dev, struct scatterlist *sg, int nents, 162 int direction) 163{ 164 /* Nothing to do. */ 165} 166 167/* Return whether the given PCI device DMA address mask can 168 be supported properly. For example, if your device can 169 only drive the low 24-bits during PCI bus mastering, then 170 you would pass 0x00ffffff as the mask to this function. */ 171 172extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask); 173 174/* True if the machine supports DAC addressing, and DEV can 175 make use of it given MASK. */ 176extern int pci_dac_dma_supported(struct pci_dev *hwdev, u64 mask); 177 178/* Convert to/from DAC dma address and struct page. */ 179extern dma64_addr_t pci_dac_page_to_dma(struct pci_dev *, struct page *, unsigned long, int); 180extern struct page *pci_dac_dma_to_page(struct pci_dev *, dma64_addr_t); 181extern unsigned long pci_dac_dma_to_offset(struct pci_dev *, dma64_addr_t); 182 183static __inline__ void 184pci_dac_dma_sync_single(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, int direction) 185{ 186 /* Nothing to do. */ 187} 188 189/* Return the index of the PCI controller for device PDEV. */ 190extern int pci_controller_num(struct pci_dev *pdev); 191#endif /* __KERNEL__ */ 192 193/* Values for the `which' argument to sys_pciconfig_iobase. */ 194#define IOBASE_HOSE 0 195#define IOBASE_SPARSE_MEM 1 196#define IOBASE_DENSE_MEM 2 197#define IOBASE_SPARSE_IO 3 198#define IOBASE_DENSE_IO 4 199#define IOBASE_ROOT_BUS 5 200#define IOBASE_FROM_HOSE 0x10000 201 202#endif /* __ALPHA_PCI_H */ 203