1/* 2 * $Id: pci.h,v 1.1.1.1 2008/10/15 03:27:30 james26_jang Exp $ 3 * 4 * PCI defines and function prototypes 5 * Copyright 1994, Drew Eckhardt 6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 7 * 8 * For more information, please consult the following manuals (look at 9 * http://www.pcisig.com/ for how to get them): 10 * 11 * PCI BIOS Specification 12 * PCI Local Bus Specification 13 * PCI to PCI Bridge Specification 14 * PCI System Design Guide 15 */ 16 17#ifndef LINUX_PCI_H 18#define LINUX_PCI_H 19 20/* 21 * Under PCI, each device has 256 bytes of configuration address space, 22 * of which the first 64 bytes are standardized as follows: 23 */ 24#define PCI_VENDOR_ID 0x00 /* 16 bits */ 25#define PCI_DEVICE_ID 0x02 /* 16 bits */ 26#define PCI_COMMAND 0x04 /* 16 bits */ 27#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 28#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 29#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 30#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 31#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 32#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 33#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 34#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 35#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 36#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 37 38#define PCI_STATUS 0x06 /* 16 bits */ 39#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 40#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 41#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 42#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 43#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 44#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 45#define PCI_STATUS_DEVSEL_FAST 0x000 46#define PCI_STATUS_DEVSEL_MEDIUM 0x200 47#define PCI_STATUS_DEVSEL_SLOW 0x400 48#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 49#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 50#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 51#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 52#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 53 54#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 55 revision */ 56#define PCI_REVISION_ID 0x08 /* Revision ID */ 57#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 58#define PCI_CLASS_DEVICE 0x0a /* Device class */ 59 60#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 61#define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 62#define PCI_HEADER_TYPE 0x0e /* 8 bits */ 63#define PCI_HEADER_TYPE_NORMAL 0 64#define PCI_HEADER_TYPE_BRIDGE 1 65#define PCI_HEADER_TYPE_CARDBUS 2 66 67#define PCI_BIST 0x0f /* 8 bits */ 68#define PCI_BIST_CODE_MASK 0x0f /* Return result */ 69#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 70#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 71 72/* 73 * Base addresses specify locations in memory or I/O space. 74 * Decoded size can be determined by writing a value of 75 * 0xffffffff to the register, and reading it back. Only 76 * 1 bits are decoded. 77 */ 78#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 79#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 80#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 81#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 82#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 83#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 84#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 85#define PCI_BASE_ADDRESS_SPACE_IO 0x01 86#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 87#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 88#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 89#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 90#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 91#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 92#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 93#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 94/* bit 1 is reserved if address_space = 1 */ 95 96/* Header type 0 (normal devices) */ 97#define PCI_CARDBUS_CIS 0x28 98#define PCI_SUBSYSTEM_VENDOR_ID 0x2c 99#define PCI_SUBSYSTEM_ID 0x2e 100#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 101#define PCI_ROM_ADDRESS_ENABLE 0x01 102#define PCI_ROM_ADDRESS_MASK (~0x7ffUL) 103 104#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 105 106/* 0x35-0x3b are reserved */ 107#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 108#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 109#define PCI_MIN_GNT 0x3e /* 8 bits */ 110#define PCI_MAX_LAT 0x3f /* 8 bits */ 111 112/* Header type 1 (PCI-to-PCI bridges) */ 113#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 114#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 115#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 116#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 117#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 118#define PCI_IO_LIMIT 0x1d 119#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */ 120#define PCI_IO_RANGE_TYPE_16 0x00 121#define PCI_IO_RANGE_TYPE_32 0x01 122#define PCI_IO_RANGE_MASK (~0x0fUL) 123#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 124#define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 125#define PCI_MEMORY_LIMIT 0x22 126#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 127#define PCI_MEMORY_RANGE_MASK (~0x0fUL) 128#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 129#define PCI_PREF_MEMORY_LIMIT 0x26 130#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 131#define PCI_PREF_RANGE_TYPE_32 0x00 132#define PCI_PREF_RANGE_TYPE_64 0x01 133#define PCI_PREF_RANGE_MASK (~0x0fUL) 134#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 135#define PCI_PREF_LIMIT_UPPER32 0x2c 136#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 137#define PCI_IO_LIMIT_UPPER16 0x32 138/* 0x34 same as for htype 0 */ 139/* 0x35-0x3b is reserved */ 140#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 141/* 0x3c-0x3d are same as for htype 0 */ 142#define PCI_BRIDGE_CONTROL 0x3e 143#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 144#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 145#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 146#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 147#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 148#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 149#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 150 151/* Header type 2 (CardBus bridges) */ 152#define PCI_CB_CAPABILITY_LIST 0x14 153/* 0x15 reserved */ 154#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 155#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 156#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 157#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 158#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 159#define PCI_CB_MEMORY_BASE_0 0x1c 160#define PCI_CB_MEMORY_LIMIT_0 0x20 161#define PCI_CB_MEMORY_BASE_1 0x24 162#define PCI_CB_MEMORY_LIMIT_1 0x28 163#define PCI_CB_IO_BASE_0 0x2c 164#define PCI_CB_IO_BASE_0_HI 0x2e 165#define PCI_CB_IO_LIMIT_0 0x30 166#define PCI_CB_IO_LIMIT_0_HI 0x32 167#define PCI_CB_IO_BASE_1 0x34 168#define PCI_CB_IO_BASE_1_HI 0x36 169#define PCI_CB_IO_LIMIT_1 0x38 170#define PCI_CB_IO_LIMIT_1_HI 0x3a 171#define PCI_CB_IO_RANGE_MASK (~0x03UL) 172/* 0x3c-0x3d are same as for htype 0 */ 173#define PCI_CB_BRIDGE_CONTROL 0x3e 174#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 175#define PCI_CB_BRIDGE_CTL_SERR 0x02 176#define PCI_CB_BRIDGE_CTL_ISA 0x04 177#define PCI_CB_BRIDGE_CTL_VGA 0x08 178#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 179#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 180#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 181#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 182#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 183#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 184#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 185#define PCI_CB_SUBSYSTEM_ID 0x42 186#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 187/* 0x48-0x7f reserved */ 188 189/* Capability lists */ 190 191#define PCI_CAP_LIST_ID 0 /* Capability ID */ 192#define PCI_CAP_ID_PM 0x01 /* Power Management */ 193#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 194#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 195#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 196#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 197#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 198#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 199#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 200#define PCI_CAP_SIZEOF 4 201 202/* Power Management Registers */ 203 204#define PCI_PM_PMC 2 /* PM Capabilities Register */ 205#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 206#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 207#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */ 208#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 209#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */ 210#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 211#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 212#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 213#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */ 214#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */ 215#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */ 216#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */ 217#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */ 218#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */ 219#define PCI_PM_CTRL 4 /* PM control and status register */ 220#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 221#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 222#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 223#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 224#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 225#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 226#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 227#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 228#define PCI_PM_DATA_REGISTER 7 /* (??) */ 229#define PCI_PM_SIZEOF 8 230 231/* AGP registers */ 232 233#define PCI_AGP_VERSION 2 /* BCD version number */ 234#define PCI_AGP_RFU 3 /* Rest of capability flags */ 235#define PCI_AGP_STATUS 4 /* Status register */ 236#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 237#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 238#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 239#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 240#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 241#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 242#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 243#define PCI_AGP_COMMAND 8 /* Control register */ 244#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 245#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 246#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 247#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 248#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 249#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 250#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */ 251#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */ 252#define PCI_AGP_SIZEOF 12 253 254/* Slot Identification */ 255 256#define PCI_SID_ESR 2 /* Expansion Slot Register */ 257#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 258#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 259#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 260 261/* Message Signalled Interrupts registers */ 262 263#define PCI_MSI_FLAGS 2 /* Various flags */ 264#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 265#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 266#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 267#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 268#define PCI_MSI_RFU 3 /* Rest of capability flags */ 269#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 270#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 271#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 272#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 273 274/* Include the ID list */ 275 276#include <linux/pci_ids.h> 277 278/* 279 * The PCI interface treats multi-function devices as independent 280 * devices. The slot/function address of each device is encoded 281 * in a single byte as follows: 282 * 283 * 7:3 = slot 284 * 2:0 = function 285 */ 286#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) 287#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 288#define PCI_FUNC(devfn) ((devfn) & 0x07) 289 290/* Ioctls for /proc/bus/pci/X/Y nodes. */ 291#define PCIIOC_BASE ('P' << 24 | 'C' << 16 | 'I' << 8) 292#define PCIIOC_CONTROLLER (PCIIOC_BASE | 0x00) /* Get controller for PCI device. */ 293#define PCIIOC_MMAP_IS_IO (PCIIOC_BASE | 0x01) /* Set mmap state to I/O space. */ 294#define PCIIOC_MMAP_IS_MEM (PCIIOC_BASE | 0x02) /* Set mmap state to MEM space. */ 295#define PCIIOC_WRITE_COMBINE (PCIIOC_BASE | 0x03) /* Enable/disable write-combining. */ 296 297#ifdef __KERNEL__ 298 299#include <linux/types.h> 300#include <linux/config.h> 301#include <linux/ioport.h> 302#include <linux/list.h> 303#include <linux/errno.h> 304 305/* File state for mmap()s on /proc/bus/pci/X/Y */ 306enum pci_mmap_state { 307 pci_mmap_io, 308 pci_mmap_mem 309}; 310 311/* This defines the direction arg to the DMA mapping routines. */ 312#define PCI_DMA_BIDIRECTIONAL 0 313#define PCI_DMA_TODEVICE 1 314#define PCI_DMA_FROMDEVICE 2 315#define PCI_DMA_NONE 3 316 317#define DEVICE_COUNT_COMPATIBLE 4 318#define DEVICE_COUNT_IRQ 2 319#define DEVICE_COUNT_DMA 2 320#define DEVICE_COUNT_RESOURCE 12 321 322#define PCI_ANY_ID (~0) 323 324#define pci_present pcibios_present 325 326 327#define pci_for_each_dev_reverse(dev) \ 328 for(dev = pci_dev_g(pci_devices.prev); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.prev)) 329 330#define pci_for_each_bus(bus) \ 331for(bus = pci_bus_b(pci_root_buses.next); bus != pci_bus_b(&pci_root_buses); bus = pci_bus_b(bus->node.next)) 332 333/* 334 * The pci_dev structure is used to describe both PCI and ISAPnP devices. 335 */ 336struct pci_dev { 337 struct list_head global_list; /* node in list of all PCI devices */ 338 struct list_head bus_list; /* node in per-bus list */ 339 struct pci_bus *bus; /* bus this device is on */ 340 struct pci_bus *subordinate; /* bus this device bridges to */ 341 342 void *sysdata; /* hook for sys-specific extension */ 343 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 344 345 unsigned int devfn; /* encoded device & function index */ 346 unsigned short vendor; 347 unsigned short device; 348 unsigned short subsystem_vendor; 349 unsigned short subsystem_device; 350 unsigned int class; /* 3 bytes: (base,sub,prog-if) */ 351 u8 hdr_type; /* PCI header type (`multi' flag masked out) */ 352 u8 rom_base_reg; /* which config register controls the ROM */ 353 354 struct pci_driver *driver; /* which driver has allocated this device */ 355 void *driver_data; /* data private to the driver */ 356 u64 dma_mask; /* Mask of the bits of bus address this 357 device implements. Normally this is 358 0xffffffff. You only need to change 359 this if your device has broken DMA 360 or supports 64-bit transfers. */ 361 362 u32 current_state; /* Current operating state. In ACPI-speak, 363 this is D0-D3, D0 being fully functional, 364 and D3 being off. */ 365 366 /* device is compatible with these IDs */ 367 unsigned short vendor_compatible[DEVICE_COUNT_COMPATIBLE]; 368 unsigned short device_compatible[DEVICE_COUNT_COMPATIBLE]; 369 370 /* 371 * Instead of touching interrupt line and base address registers 372 * directly, use the values stored here. They might be different! 373 */ 374 unsigned int irq; 375 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 376 struct resource dma_resource[DEVICE_COUNT_DMA]; 377 struct resource irq_resource[DEVICE_COUNT_IRQ]; 378 379 char name[90]; /* device name */ 380 char slot_name[8]; /* slot name */ 381 int active; /* ISAPnP: device is active */ 382 int ro; /* ISAPnP: read only */ 383 unsigned short regs; /* ISAPnP: supported registers */ 384 385 /* These fields are used by common fixups */ 386 unsigned short transparent:1; /* Transparent PCI bridge */ 387 388 int (*prepare)(struct pci_dev *dev); /* ISAPnP hooks */ 389 int (*activate)(struct pci_dev *dev); 390 int (*deactivate)(struct pci_dev *dev); 391}; 392 393#define pci_dev_g(n) list_entry(n, struct pci_dev, global_list) 394#define pci_dev_b(n) list_entry(n, struct pci_dev, bus_list) 395 396/* 397 * For PCI devices, the region numbers are assigned this way: 398 * 399 * 0-5 standard PCI regions 400 * 6 expansion ROM 401 * 7-10 bridges: address space assigned to buses behind the bridge 402 */ 403 404#define PCI_ROM_RESOURCE 6 405#define PCI_BRIDGE_RESOURCES 7 406#define PCI_NUM_RESOURCES 11 407 408#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 409 410struct pci_bus { 411 struct list_head node; /* node in list of buses */ 412 struct pci_bus *parent; /* parent bus this bridge is on */ 413 struct list_head children; /* list of child buses */ 414 struct list_head devices; /* list of devices on this bus */ 415 struct pci_dev *self; /* bridge device as seen by parent */ 416 struct resource *resource[4]; /* address space routed to this bus */ 417 418 struct pci_ops *ops; /* configuration access functions */ 419 void *sysdata; /* hook for sys-specific extension */ 420 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 421 422 unsigned char number; /* bus number */ 423 unsigned char primary; /* number of primary bridge */ 424 unsigned char secondary; /* number of secondary bridge */ 425 unsigned char subordinate; /* max number of subordinate buses */ 426 427 char name[48]; 428 unsigned short vendor; 429 unsigned short device; 430 unsigned int serial; /* serial number */ 431 unsigned char pnpver; /* Plug & Play version */ 432 unsigned char productver; /* product version */ 433 unsigned char checksum; /* if zero - checksum passed */ 434 unsigned char pad1; 435}; 436 437#define pci_bus_b(n) list_entry(n, struct pci_bus, node) 438 439extern struct list_head pci_root_buses; /* list of all known PCI buses */ 440extern struct list_head pci_devices; /* list of all devices */ 441 442extern struct proc_dir_entry *proc_bus_pci_dir; 443/* 444 * Error values that may be returned by PCI functions. 445 */ 446#define PCIBIOS_SUCCESSFUL 0x00 447#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 448#define PCIBIOS_BAD_VENDOR_ID 0x83 449#define PCIBIOS_DEVICE_NOT_FOUND 0x86 450#define PCIBIOS_BAD_REGISTER_NUMBER 0x87 451#define PCIBIOS_SET_FAILED 0x88 452#define PCIBIOS_BUFFER_TOO_SMALL 0x89 453 454/* Low-level architecture-dependent routines */ 455 456struct pci_ops { 457 int (*read_byte)(struct pci_dev *, int where, u8 *val); 458 int (*read_word)(struct pci_dev *, int where, u16 *val); 459 int (*read_dword)(struct pci_dev *, int where, u32 *val); 460 int (*write_byte)(struct pci_dev *, int where, u8 val); 461 int (*write_word)(struct pci_dev *, int where, u16 val); 462 int (*write_dword)(struct pci_dev *, int where, u32 val); 463}; 464 465struct pbus_set_ranges_data 466{ 467 unsigned long io_start, io_end; 468 unsigned long mem_start, mem_end; 469 unsigned long prefetch_start, prefetch_end; 470}; 471 472struct pci_device_id { 473 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 474 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 475 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 476 unsigned long driver_data; /* Data private to the driver */ 477}; 478 479struct pci_driver { 480 struct list_head node; 481 char *name; 482 const struct pci_device_id *id_table; /* NULL if wants all devices */ 483 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 484 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 485 int (*save_state) (struct pci_dev *dev, u32 state); /* Save Device Context */ 486 int (*suspend) (struct pci_dev *dev, u32 state); /* Device suspended */ 487 int (*resume) (struct pci_dev *dev); /* Device woken up */ 488 int (*enable_wake) (struct pci_dev *dev, u32 state, int enable); /* Enable wake event */ 489}; 490 491 492/* these external functions are only available when PCI support is enabled */ 493#ifdef CONFIG_PCI 494 495#define pci_for_each_dev(dev) \ 496 for(dev = pci_dev_g(pci_devices.next); dev != pci_dev_g(&pci_devices); dev = pci_dev_g(dev->global_list.next)) 497 498void pcibios_init(void); 499void pcibios_fixup_bus(struct pci_bus *); 500int pcibios_enable_device(struct pci_dev *, int mask); 501char *pcibios_setup (char *str); 502 503/* Used only when drivers/pci/setup.c is used */ 504void pcibios_align_resource(void *, struct resource *, 505 unsigned long, unsigned long); 506void pcibios_update_resource(struct pci_dev *, struct resource *, 507 struct resource *, int); 508void pcibios_update_irq(struct pci_dev *, int irq); 509void pcibios_fixup_pbus_ranges(struct pci_bus *, struct pbus_set_ranges_data *); 510 511/* Backward compatibility, don't use in new code! */ 512 513int pcibios_present(void); 514int pcibios_read_config_byte (unsigned char bus, unsigned char dev_fn, 515 unsigned char where, unsigned char *val); 516int pcibios_read_config_word (unsigned char bus, unsigned char dev_fn, 517 unsigned char where, unsigned short *val); 518int pcibios_read_config_dword (unsigned char bus, unsigned char dev_fn, 519 unsigned char where, unsigned int *val); 520int pcibios_write_config_byte (unsigned char bus, unsigned char dev_fn, 521 unsigned char where, unsigned char val); 522int pcibios_write_config_word (unsigned char bus, unsigned char dev_fn, 523 unsigned char where, unsigned short val); 524int pcibios_write_config_dword (unsigned char bus, unsigned char dev_fn, 525 unsigned char where, unsigned int val); 526int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn); 527int pcibios_find_device (unsigned short vendor, unsigned short dev_id, 528 unsigned short index, unsigned char *bus, 529 unsigned char *dev_fn); 530 531/* Generic PCI functions used internally */ 532 533void pci_init(void); 534int pci_bus_exists(const struct list_head *list, int nr); 535struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata); 536struct pci_bus *pci_alloc_primary_bus(int bus); 537struct pci_dev *pci_scan_slot(struct pci_dev *temp); 538int pci_proc_attach_device(struct pci_dev *dev); 539int pci_proc_detach_device(struct pci_dev *dev); 540int pci_proc_attach_bus(struct pci_bus *bus); 541int pci_proc_detach_bus(struct pci_bus *bus); 542void pci_name_device(struct pci_dev *dev); 543char *pci_class_name(u32 class); 544void pci_read_bridge_bases(struct pci_bus *child); 545struct resource *pci_find_parent_resource(const struct pci_dev *dev, struct resource *res); 546int pci_setup_device(struct pci_dev *dev); 547int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge); 548 549/* Generic PCI functions exported to card drivers */ 550 551struct pci_dev *pci_find_device (unsigned int vendor, unsigned int device, const struct pci_dev *from); 552struct pci_dev *pci_find_subsys (unsigned int vendor, unsigned int device, 553 unsigned int ss_vendor, unsigned int ss_device, 554 const struct pci_dev *from); 555struct pci_dev *pci_find_class (unsigned int class, const struct pci_dev *from); 556struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn); 557int pci_find_capability (struct pci_dev *dev, int cap); 558 559int pci_read_config_byte(struct pci_dev *dev, int where, u8 *val); 560int pci_read_config_word(struct pci_dev *dev, int where, u16 *val); 561int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val); 562int pci_write_config_byte(struct pci_dev *dev, int where, u8 val); 563int pci_write_config_word(struct pci_dev *dev, int where, u16 val); 564int pci_write_config_dword(struct pci_dev *dev, int where, u32 val); 565 566int pci_enable_device(struct pci_dev *dev); 567int pci_enable_device_bars(struct pci_dev *dev, int mask); 568void pci_disable_device(struct pci_dev *dev); 569void pci_set_master(struct pci_dev *dev); 570#define HAVE_PCI_SET_MWI 571int pci_set_mwi(struct pci_dev *dev); 572void pci_clear_mwi(struct pci_dev *dev); 573int pdev_set_mwi(struct pci_dev *dev); 574int pci_set_dma_mask(struct pci_dev *dev, u64 mask); 575int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask); 576int pci_assign_resource(struct pci_dev *dev, int i); 577 578/* Power management related routines */ 579int pci_save_state(struct pci_dev *dev, u32 *buffer); 580int pci_restore_state(struct pci_dev *dev, u32 *buffer); 581int pci_set_power_state(struct pci_dev *dev, int state); 582int pci_enable_wake(struct pci_dev *dev, u32 state, int enable); 583 584/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 585 586int pci_claim_resource(struct pci_dev *, int); 587void pci_assign_unassigned_resources(void); 588void pdev_enable_device(struct pci_dev *); 589void pdev_sort_resources(struct pci_dev *, struct resource_list *); 590unsigned long pci_bridge_check_io(struct pci_dev *); 591void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), 592 int (*)(struct pci_dev *, u8, u8)); 593#define HAVE_PCI_REQ_REGIONS 2 594int pci_request_regions(struct pci_dev *, char *); 595void pci_release_regions(struct pci_dev *); 596int pci_request_region(struct pci_dev *, int, char *); 597void pci_release_region(struct pci_dev *, int); 598 599/* New-style probing supporting hot-pluggable devices */ 600int pci_register_driver(struct pci_driver *); 601void pci_unregister_driver(struct pci_driver *); 602void pci_insert_device(struct pci_dev *, struct pci_bus *); 603void pci_remove_device(struct pci_dev *); 604struct pci_driver *pci_dev_driver(const struct pci_dev *); 605const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev); 606void pci_announce_device_to_drivers(struct pci_dev *); 607unsigned int pci_do_scan_bus(struct pci_bus *bus); 608struct pci_bus * pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr); 609 610/* kmem_cache style wrapper around pci_alloc_consistent() */ 611struct pci_pool *pci_pool_create (const char *name, struct pci_dev *dev, 612 size_t size, size_t align, size_t allocation, int flags); 613void pci_pool_destroy (struct pci_pool *pool); 614 615void *pci_pool_alloc (struct pci_pool *pool, int flags, dma_addr_t *handle); 616void pci_pool_free (struct pci_pool *pool, void *vaddr, dma_addr_t addr); 617 618#endif /* CONFIG_PCI */ 619 620/* Include architecture-dependent settings and functions */ 621 622#include <asm/pci.h> 623 624/* 625 * If the system does not have PCI, clearly these return errors. Define 626 * these as simple inline functions to avoid hair in drivers. 627 */ 628 629#ifndef CONFIG_PCI 630static inline int pcibios_present(void) { return 0; } 631static inline int pcibios_find_class (unsigned int class_code, unsigned short index, unsigned char *bus, unsigned char *dev_fn) 632{ return PCIBIOS_DEVICE_NOT_FOUND; } 633 634#define _PCI_NOP(o,s,t) \ 635 static inline int pcibios_##o##_config_##s (u8 bus, u8 dfn, u8 where, t val) \ 636 { return PCIBIOS_FUNC_NOT_SUPPORTED; } \ 637 static inline int pci_##o##_config_##s (struct pci_dev *dev, int where, t val) \ 638 { return PCIBIOS_FUNC_NOT_SUPPORTED; } 639#define _PCI_NOP_ALL(o,x) _PCI_NOP(o,byte,u8 x) \ 640 _PCI_NOP(o,word,u16 x) \ 641 _PCI_NOP(o,dword,u32 x) 642_PCI_NOP_ALL(read, *) 643_PCI_NOP_ALL(write,) 644 645static inline struct pci_dev *pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from) 646{ return NULL; } 647 648static inline struct pci_dev *pci_find_class(unsigned int class, const struct pci_dev *from) 649{ return NULL; } 650 651static inline struct pci_dev *pci_find_slot(unsigned int bus, unsigned int devfn) 652{ return NULL; } 653 654static inline struct pci_dev *pci_find_subsys(unsigned int vendor, unsigned int device, 655unsigned int ss_vendor, unsigned int ss_device, const struct pci_dev *from) 656{ return NULL; } 657 658static inline void pci_set_master(struct pci_dev *dev) { } 659static inline int pci_enable_device_bars(struct pci_dev *dev, int mask) { return -EBUSY; } 660static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } 661static inline void pci_disable_device(struct pci_dev *dev) { } 662static inline int pci_module_init(struct pci_driver *drv) { return -ENODEV; } 663static inline int pci_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } 664static inline int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) { return -EIO; } 665static inline int pci_assign_resource(struct pci_dev *dev, int i) { return -EBUSY;} 666static inline int pci_register_driver(struct pci_driver *drv) { return 0;} 667static inline void pci_unregister_driver(struct pci_driver *drv) { } 668static inline int scsi_to_pci_dma_dir(unsigned char scsi_dir) { return scsi_dir; } 669static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; } 670static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; } 671 672/* Power management related routines */ 673static inline int pci_save_state(struct pci_dev *dev, u32 *buffer) { return 0; } 674static inline int pci_restore_state(struct pci_dev *dev, u32 *buffer) { return 0; } 675static inline int pci_set_power_state(struct pci_dev *dev, int state) { return 0; } 676static inline int pci_enable_wake(struct pci_dev *dev, u32 state, int enable) { return 0; } 677 678#define pci_for_each_dev(dev) \ 679 for(dev = NULL; 0; ) 680 681#else 682 683/* 684 * a helper function which helps ensure correct pci_driver 685 * setup and cleanup for commonly-encountered hotplug/modular cases 686 * 687 * This MUST stay in a header, as it checks for -DMODULE 688 */ 689static inline int pci_module_init(struct pci_driver *drv) 690{ 691 int rc = pci_register_driver (drv); 692 693 if (rc > 0) 694 return 0; 695 696 /* iff CONFIG_HOTPLUG and built into kernel, we should 697 * leave the driver around for future hotplug events. 698 * For the module case, a hotplug daemon of some sort 699 * should load a module in response to an insert event. */ 700#if defined(CONFIG_HOTPLUG) && !defined(MODULE) 701 if (rc == 0) 702 return 0; 703#else 704 if (rc == 0) 705 rc = -ENODEV; 706#endif 707 708 /* if we get here, we need to clean up pci driver instance 709 * and return some sort of error */ 710 pci_unregister_driver (drv); 711 712 return rc; 713} 714 715#endif /* !CONFIG_PCI */ 716 717/* these helpers provide future and backwards compatibility 718 * for accessing popular PCI BAR info */ 719#define pci_resource_start(dev,bar) ((dev)->resource[(bar)].start) 720#define pci_resource_end(dev,bar) ((dev)->resource[(bar)].end) 721#define pci_resource_flags(dev,bar) ((dev)->resource[(bar)].flags) 722#define pci_resource_len(dev,bar) \ 723 ((pci_resource_start((dev),(bar)) == 0 && \ 724 pci_resource_end((dev),(bar)) == \ 725 pci_resource_start((dev),(bar))) ? 0 : \ 726 \ 727 (pci_resource_end((dev),(bar)) - \ 728 pci_resource_start((dev),(bar)) + 1)) 729 730/* Similar to the helpers above, these manipulate per-pci_dev 731 * driver-specific data. Currently stored as pci_dev::driver_data, 732 * a void pointer, but it is not present on older kernels. 733 */ 734static inline void *pci_get_drvdata (struct pci_dev *pdev) 735{ 736 return pdev->driver_data; 737} 738 739static inline void pci_set_drvdata (struct pci_dev *pdev, void *data) 740{ 741 pdev->driver_data = data; 742} 743 744/* 745 * The world is not perfect and supplies us with broken PCI devices. 746 * For at least a part of these bugs we need a work-around, so both 747 * generic (drivers/pci/quirks.c) and per-architecture code can define 748 * fixup hooks to be called for particular buggy devices. 749 */ 750 751struct pci_fixup { 752 int pass; 753 u16 vendor, device; /* You can use PCI_ANY_ID here of course */ 754 void (*hook)(struct pci_dev *dev); 755}; 756 757extern struct pci_fixup pcibios_fixups[]; 758 759#define PCI_FIXUP_HEADER 1 /* Called immediately after reading configuration header */ 760#define PCI_FIXUP_FINAL 2 /* Final phase of device fixups */ 761 762void pci_fixup_device(int pass, struct pci_dev *dev); 763 764extern int pci_pci_problems; 765#define PCIPCI_FAIL 1 766#define PCIPCI_TRITON 2 767#define PCIPCI_NATOMA 4 768#define PCIPCI_VIAETBF 8 769#define PCIPCI_VSFX 16 770 771#endif /* __KERNEL__ */ 772#endif /* LINUX_PCI_H */ 773