1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * SCD Constants and Macros File: sb1250_scd.h 5 * 6 * This module contains constants and macros useful for 7 * manipulating the System Control and Debug module on the 1250. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 ********************************************************************* */ 33 34#ifndef _SB1250_SCD_H 35#define _SB1250_SCD_H 36 37#include "sb1250_defs.h" 38 39/* ********************************************************************* 40 * System control/debug registers 41 ********************************************************************* */ 42 43/* 44 * System Revision Register (Table 4-1) 45 */ 46 47#define M_SYS_RESERVED _SB_MAKEMASK(8,0) 48 49#define S_SYS_REVISION _SB_MAKE64(8) 50#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) 51#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) 52#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) 53 54#if SIBYTE_HDR_FEATURE_CHIP(1250) 55#define K_SYS_REVISION_BCM1250_PASS1 1 56#define K_SYS_REVISION_BCM1250_PASS2 3 57#define K_SYS_REVISION_BCM1250_PASS2_2 16 58#define K_SYS_REVISION_BCM1250_PASS3 32 59 60#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 61#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 62#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 63#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 64#endif /* 1250 */ 65 66#if SIBYTE_HDR_FEATURE_CHIP(112x) 67#define K_SYS_REVISION_BCM112x_A1 32 68#define K_SYS_REVISION_BCM112x_A2 33 69#endif /* 112x */ 70 71#define S_SYS_PART _SB_MAKE64(16) 72#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) 73#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) 74#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) 75 76#define K_SYS_PART_SB1250 0x1250 77#define K_SYS_PART_BCM1120 0x1121 78#define K_SYS_PART_BCM1125 0x1123 79#define K_SYS_PART_BCM1125H 0x1124 80 81/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ 82#define S_SYS_SOC_TYPE _SB_MAKE64(16) 83#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) 84#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) 85#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) 86 87#define K_SYS_SOC_TYPE_BCM1250 0x0 88#define K_SYS_SOC_TYPE_BCM1120 0x1 89#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ 90#define K_SYS_SOC_TYPE_BCM1125 0x3 91#define K_SYS_SOC_TYPE_BCM1125H 0x4 92#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ 93 94/* 95 * Calculate correct SOC type given a copy of system revision register. 96 * 97 * (For the assembler version, sysrev and dest may be the same register. 98 * Also, it clobbers AT.) 99 */ 100#ifdef __ASSEMBLER__ 101#define SYS_SOC_TYPE(dest, sysrev) \ 102 .set push ; \ 103 .set reorder ; \ 104 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ 105 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ 106 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ 107 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ 108 b 992f ; \ 109991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ 110992: \ 111 .set pop 112#else 113#define SYS_SOC_TYPE(sysrev) \ 114 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ 115 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ 116 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) 117#endif 118 119#define S_SYS_WID _SB_MAKE64(32) 120#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) 121#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) 122#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) 123 124/* 125 * System Config Register (Table 4-2) 126 * Register: SCD_SYSTEM_CFG 127 */ 128 129#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) 130#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) 131#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) 132#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) 133 134#define S_SYS_PLL_DIV _SB_MAKE64(7) 135#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) 136#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) 137#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) 138 139#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) 140#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) 141#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) 142#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) 143#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) 144 145#define S_SYS_BOOT_MODE _SB_MAKE64(17) 146#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) 147#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) 148#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) 149#define K_SYS_BOOT_MODE_ROM32 0 150#define K_SYS_BOOT_MODE_ROM8 1 151#define K_SYS_BOOT_MODE_SMBUS_SMALL 2 152#define K_SYS_BOOT_MODE_SMBUS_BIG 3 153 154#define M_SYS_PCI_HOST _SB_MAKEMASK1(19) 155#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) 156#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) 157#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) 158#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) 159#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) 160#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) 161 162#define S_SYS_CONFIG 26 163#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) 164#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) 165#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) 166 167/* The following bits are writeable by JTAG only. */ 168 169#define M_SYS_CLKSTOP _SB_MAKEMASK1(32) 170#define M_SYS_CLKSTEP _SB_MAKEMASK1(33) 171 172#define S_SYS_CLKCOUNT 34 173#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) 174#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) 175#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) 176 177#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) 178 179#define S_SYS_PLL_IREF 43 180#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) 181 182#define S_SYS_PLL_VCO 45 183#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) 184 185#define S_SYS_PLL_VREG 47 186#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) 187 188#define M_SYS_MEM_RESET _SB_MAKEMASK1(49) 189#define M_SYS_L2C_RESET _SB_MAKEMASK1(50) 190#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) 191#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) 192#define M_SYS_SCD_RESET _SB_MAKEMASK1(53) 193 194/* End of bits writable by JTAG only. */ 195 196#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) 197#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) 198 199#define M_SYS_UNICPU0 _SB_MAKEMASK1(56) 200#define M_SYS_UNICPU1 _SB_MAKEMASK1(57) 201 202#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) 203#define M_SYS_EXT_RESET _SB_MAKEMASK1(59) 204#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) 205 206#define M_SYS_MISR_MODE _SB_MAKEMASK1(61) 207#define M_SYS_MISR_RESET _SB_MAKEMASK1(62) 208 209#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 210#define M_SYS_SW_FLAG _SB_MAKEMASK1(63) 211#endif /* 1250 PASS2 || 112x PASS1 */ 212 213 214/* 215 * Mailbox Registers (Table 4-3) 216 * Registers: SCD_MBOX_CPU_x 217 */ 218 219#define S_MBOX_INT_3 0 220#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) 221#define S_MBOX_INT_2 16 222#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) 223#define S_MBOX_INT_1 32 224#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) 225#define S_MBOX_INT_0 48 226#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) 227 228/* 229 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) 230 * Registers: SCD_WDOG_INIT_CNT_x 231 */ 232 233#define V_SCD_WDOG_FREQ 1000000 234 235#define S_SCD_WDOG_INIT 0 236#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) 237 238#define S_SCD_WDOG_CNT 0 239#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) 240 241#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) 242 243/* 244 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) 245 */ 246 247#define V_SCD_TIMER_FREQ 1000000 248 249#define S_SCD_TIMER_INIT 0 250#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) 251#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) 252#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) 253 254#define S_SCD_TIMER_CNT 0 255#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) 256#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) 257#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) 258 259#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) 260#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) 261#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE 262 263/* 264 * System Performance Counters 265 */ 266 267#define S_SPC_CFG_SRC0 0 268#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) 269#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) 270#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) 271 272#define S_SPC_CFG_SRC1 8 273#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) 274#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) 275#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) 276 277#define S_SPC_CFG_SRC2 16 278#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) 279#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) 280#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) 281 282#define S_SPC_CFG_SRC3 24 283#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) 284#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) 285#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) 286 287#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) 288#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) 289 290 291/* 292 * Bus Watcher 293 */ 294 295#define S_SCD_BERR_TID 8 296#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) 297#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) 298#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) 299 300#define S_SCD_BERR_RID 18 301#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) 302#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) 303#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) 304 305#define S_SCD_BERR_DCODE 22 306#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) 307#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) 308#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) 309 310#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) 311 312 313#define S_SCD_L2ECC_CORR_D 0 314#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) 315#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) 316#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) 317 318#define S_SCD_L2ECC_BAD_D 8 319#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) 320#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) 321#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) 322 323#define S_SCD_L2ECC_CORR_T 16 324#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) 325#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) 326#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) 327 328#define S_SCD_L2ECC_BAD_T 24 329#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) 330#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) 331#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) 332 333#define S_SCD_MEM_ECC_CORR 0 334#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) 335#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) 336#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) 337 338#define S_SCD_MEM_ECC_BAD 8 339#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) 340#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) 341#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) 342 343#define S_SCD_MEM_BUSERR 16 344#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) 345#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) 346#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) 347 348 349/* 350 * Address Trap Registers 351 */ 352 353#define M_ATRAP_INDEX _SB_MAKEMASK(4,0) 354#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) 355 356#define S_ATRAP_CFG_CNT 0 357#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) 358#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) 359#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) 360 361#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) 362#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) 363#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) 364#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) 365#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) 366 367#define S_ATRAP_CFG_AGENTID 8 368#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) 369#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) 370#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) 371 372#define K_BUS_AGENT_CPU0 0 373#define K_BUS_AGENT_CPU1 1 374#define K_BUS_AGENT_IOB0 2 375#define K_BUS_AGENT_IOB1 3 376#define K_BUS_AGENT_SCD 4 377#define K_BUS_AGENT_RESERVED 5 378#define K_BUS_AGENT_L2C 6 379#define K_BUS_AGENT_MC 7 380 381#define S_ATRAP_CFG_CATTR 12 382#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) 383#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) 384#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) 385 386#define K_ATRAP_CFG_CATTR_IGNORE 0 387#define K_ATRAP_CFG_CATTR_UNC 1 388#define K_ATRAP_CFG_CATTR_CACHEABLE 2 389#define K_ATRAP_CFG_CATTR_NONCOH 3 390#define K_ATRAP_CFG_CATTR_COHERENT 4 391#define K_ATRAP_CFG_CATTR_NOTUNC 5 392#define K_ATRAP_CFG_CATTR_NOTNONCOH 6 393#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 394 395/* 396 * Trace Buffer Config register 397 */ 398 399#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) 400#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) 401#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) 402#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) 403#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) 404#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) 405#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) 406#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) 407#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 408#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) 409#endif /* 1250 PASS2 || 112x PASS1 */ 410 411#define S_SCD_TRACE_CFG_CUR_ADDR 10 412#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) 413#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) 414#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) 415 416/* 417 * Trace Event registers 418 */ 419 420#define S_SCD_TREVT_ADDR_MATCH 0 421#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) 422#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) 423#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) 424 425#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) 426#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) 427#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) 428#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) 429#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) 430#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) 431#define M_SCD_TREVT_READ _SB_MAKEMASK1(11) 432 433#define S_SCD_TREVT_REQID 12 434#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) 435#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) 436#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) 437 438#define S_SCD_TREVT_RESPID 16 439#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) 440#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) 441#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) 442 443#define S_SCD_TREVT_DATAID 20 444#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) 445#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) 446#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) 447 448#define S_SCD_TREVT_COUNT 24 449#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) 450#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) 451#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) 452 453/* 454 * Trace Sequence registers 455 */ 456 457#define S_SCD_TRSEQ_EVENT4 0 458#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) 459#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) 460#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) 461 462#define S_SCD_TRSEQ_EVENT3 4 463#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) 464#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) 465#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) 466 467#define S_SCD_TRSEQ_EVENT2 8 468#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) 469#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) 470#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) 471 472#define S_SCD_TRSEQ_EVENT1 12 473#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) 474#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) 475#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) 476 477#define K_SCD_TRSEQ_E0 0 478#define K_SCD_TRSEQ_E1 1 479#define K_SCD_TRSEQ_E2 2 480#define K_SCD_TRSEQ_E3 3 481#define K_SCD_TRSEQ_E0_E1 4 482#define K_SCD_TRSEQ_E1_E2 5 483#define K_SCD_TRSEQ_E2_E3 6 484#define K_SCD_TRSEQ_E0_E1_E2 7 485#define K_SCD_TRSEQ_E0_E1_E2_E3 8 486#define K_SCD_TRSEQ_E0E1 9 487#define K_SCD_TRSEQ_E0E1E2 10 488#define K_SCD_TRSEQ_E0E1E2E3 11 489#define K_SCD_TRSEQ_E0E1_E2 12 490#define K_SCD_TRSEQ_E0E1_E2E3 13 491#define K_SCD_TRSEQ_E0E1_E2_E3 14 492#define K_SCD_TRSEQ_IGNORED 15 493 494#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ 495 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ 496 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ 497 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) 498 499#define S_SCD_TRSEQ_FUNCTION 16 500#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) 501#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) 502#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) 503 504#define K_SCD_TRSEQ_FUNC_NOP 0 505#define K_SCD_TRSEQ_FUNC_START 1 506#define K_SCD_TRSEQ_FUNC_STOP 2 507#define K_SCD_TRSEQ_FUNC_FREEZE 3 508 509#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) 510#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) 511#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) 512#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) 513 514#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) 515#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) 516#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) 517#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) 518#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) 519 520#endif 521