1/* 2 * asmmacro.h: Assembler macros to make things easier to read. 3 * 4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 5 * Copyright (C) 1998 Ralf Baechle 6 */ 7#ifndef _ASM_ASMMACRO_H 8#define _ASM_ASMMACRO_H 9 10#include <linux/config.h> 11#include <asm/offset.h> 12 13#ifdef CONFIG_CPU_SB1 14#define FPU_ENABLE_HAZARD \ 15 .set push; \ 16 .set noreorder; \ 17 .set mips2; \ 18 SSNOP; \ 19 bnezl $0, .+4; \ 20 SSNOP; \ 21 .set pop 22#else 23#define FPU_ENABLE_HAZARD 24#endif 25 26#define FPU_SAVE_DOUBLE(thread, tmp) \ 27 cfc1 tmp, fcr31; \ 28 sdc1 $f0, (THREAD_FPU + 0x000)(thread); \ 29 sdc1 $f2, (THREAD_FPU + 0x010)(thread); \ 30 sdc1 $f4, (THREAD_FPU + 0x020)(thread); \ 31 sdc1 $f6, (THREAD_FPU + 0x030)(thread); \ 32 sdc1 $f8, (THREAD_FPU + 0x040)(thread); \ 33 sdc1 $f10, (THREAD_FPU + 0x050)(thread); \ 34 sdc1 $f12, (THREAD_FPU + 0x060)(thread); \ 35 sdc1 $f14, (THREAD_FPU + 0x070)(thread); \ 36 sdc1 $f16, (THREAD_FPU + 0x080)(thread); \ 37 sdc1 $f18, (THREAD_FPU + 0x090)(thread); \ 38 sdc1 $f20, (THREAD_FPU + 0x0a0)(thread); \ 39 sdc1 $f22, (THREAD_FPU + 0x0b0)(thread); \ 40 sdc1 $f24, (THREAD_FPU + 0x0c0)(thread); \ 41 sdc1 $f26, (THREAD_FPU + 0x0d0)(thread); \ 42 sdc1 $f28, (THREAD_FPU + 0x0e0)(thread); \ 43 sdc1 $f30, (THREAD_FPU + 0x0f0)(thread); \ 44 sw tmp, (THREAD_FPU + 0x100)(thread) 45 46#if defined(__MIPSEL__) 47#define FPU_SAVE_SINGLE(thread,tmp) \ 48 cfc1 tmp, fcr31; \ 49 swc1 $f0, (THREAD_FPU + 0x000)(thread); \ 50 swc1 $f1, (THREAD_FPU + 0x004)(thread); \ 51 swc1 $f2, (THREAD_FPU + 0x010)(thread); \ 52 swc1 $f3, (THREAD_FPU + 0x014)(thread); \ 53 swc1 $f4, (THREAD_FPU + 0x020)(thread); \ 54 swc1 $f5, (THREAD_FPU + 0x024)(thread); \ 55 swc1 $f6, (THREAD_FPU + 0x030)(thread); \ 56 swc1 $f7, (THREAD_FPU + 0x034)(thread); \ 57 swc1 $f8, (THREAD_FPU + 0x040)(thread); \ 58 swc1 $f9, (THREAD_FPU + 0x044)(thread); \ 59 swc1 $f10, (THREAD_FPU + 0x050)(thread); \ 60 swc1 $f11, (THREAD_FPU + 0x054)(thread); \ 61 swc1 $f12, (THREAD_FPU + 0x060)(thread); \ 62 swc1 $f13, (THREAD_FPU + 0x064)(thread); \ 63 swc1 $f14, (THREAD_FPU + 0x070)(thread); \ 64 swc1 $f15, (THREAD_FPU + 0x074)(thread); \ 65 swc1 $f16, (THREAD_FPU + 0x080)(thread); \ 66 swc1 $f17, (THREAD_FPU + 0x084)(thread); \ 67 swc1 $f18, (THREAD_FPU + 0x090)(thread); \ 68 swc1 $f19, (THREAD_FPU + 0x094)(thread); \ 69 swc1 $f20, (THREAD_FPU + 0x0a0)(thread); \ 70 swc1 $f21, (THREAD_FPU + 0x0a4)(thread); \ 71 swc1 $f22, (THREAD_FPU + 0x0b0)(thread); \ 72 swc1 $f23, (THREAD_FPU + 0x0b4)(thread); \ 73 swc1 $f24, (THREAD_FPU + 0x0c0)(thread); \ 74 swc1 $f25, (THREAD_FPU + 0x0c4)(thread); \ 75 swc1 $f26, (THREAD_FPU + 0x0d0)(thread); \ 76 swc1 $f27, (THREAD_FPU + 0x0d4)(thread); \ 77 swc1 $f28, (THREAD_FPU + 0x0e0)(thread); \ 78 swc1 $f29, (THREAD_FPU + 0x0e4)(thread); \ 79 swc1 $f30, (THREAD_FPU + 0x0f0)(thread); \ 80 swc1 $f31, (THREAD_FPU + 0x0f4)(thread); \ 81 sw tmp, (THREAD_FPU + 0x100)(thread) 82#elif defined(__MIPSEB__) 83#define FPU_SAVE_SINGLE(thread,tmp) \ 84 cfc1 tmp, fcr31; \ 85 swc1 $f0, (THREAD_FPU + 0x004)(thread); \ 86 swc1 $f1, (THREAD_FPU + 0x000)(thread); \ 87 swc1 $f2, (THREAD_FPU + 0x014)(thread); \ 88 swc1 $f3, (THREAD_FPU + 0x010)(thread); \ 89 swc1 $f4, (THREAD_FPU + 0x024)(thread); \ 90 swc1 $f5, (THREAD_FPU + 0x020)(thread); \ 91 swc1 $f6, (THREAD_FPU + 0x034)(thread); \ 92 swc1 $f7, (THREAD_FPU + 0x030)(thread); \ 93 swc1 $f8, (THREAD_FPU + 0x044)(thread); \ 94 swc1 $f9, (THREAD_FPU + 0x040)(thread); \ 95 swc1 $f10, (THREAD_FPU + 0x054)(thread); \ 96 swc1 $f11, (THREAD_FPU + 0x050)(thread); \ 97 swc1 $f12, (THREAD_FPU + 0x064)(thread); \ 98 swc1 $f13, (THREAD_FPU + 0x060)(thread); \ 99 swc1 $f14, (THREAD_FPU + 0x074)(thread); \ 100 swc1 $f15, (THREAD_FPU + 0x070)(thread); \ 101 swc1 $f16, (THREAD_FPU + 0x084)(thread); \ 102 swc1 $f17, (THREAD_FPU + 0x080)(thread); \ 103 swc1 $f18, (THREAD_FPU + 0x094)(thread); \ 104 swc1 $f19, (THREAD_FPU + 0x090)(thread); \ 105 swc1 $f20, (THREAD_FPU + 0x0a4)(thread); \ 106 swc1 $f21, (THREAD_FPU + 0x0a0)(thread); \ 107 swc1 $f22, (THREAD_FPU + 0x0b4)(thread); \ 108 swc1 $f23, (THREAD_FPU + 0x0b0)(thread); \ 109 swc1 $f24, (THREAD_FPU + 0x0c4)(thread); \ 110 swc1 $f25, (THREAD_FPU + 0x0c0)(thread); \ 111 swc1 $f26, (THREAD_FPU + 0x0d4)(thread); \ 112 swc1 $f27, (THREAD_FPU + 0x0d0)(thread); \ 113 swc1 $f28, (THREAD_FPU + 0x0e4)(thread); \ 114 swc1 $f29, (THREAD_FPU + 0x0e0)(thread); \ 115 swc1 $f30, (THREAD_FPU + 0x0f4)(thread); \ 116 swc1 $f31, (THREAD_FPU + 0x0f0)(thread); \ 117 sw tmp, (THREAD_FPU + 0x100)(thread) 118#else 119#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" 120#endif 121 122#define FPU_RESTORE_DOUBLE(thread, tmp) \ 123 lw tmp, (THREAD_FPU + 0x100)(thread); \ 124 ldc1 $f0, (THREAD_FPU + 0x000)(thread); \ 125 ldc1 $f2, (THREAD_FPU + 0x010)(thread); \ 126 ldc1 $f4, (THREAD_FPU + 0x020)(thread); \ 127 ldc1 $f6, (THREAD_FPU + 0x030)(thread); \ 128 ldc1 $f8, (THREAD_FPU + 0x040)(thread); \ 129 ldc1 $f10, (THREAD_FPU + 0x050)(thread); \ 130 ldc1 $f12, (THREAD_FPU + 0x060)(thread); \ 131 ldc1 $f14, (THREAD_FPU + 0x070)(thread); \ 132 ldc1 $f16, (THREAD_FPU + 0x080)(thread); \ 133 ldc1 $f18, (THREAD_FPU + 0x090)(thread); \ 134 ldc1 $f20, (THREAD_FPU + 0x0a0)(thread); \ 135 ldc1 $f22, (THREAD_FPU + 0x0b0)(thread); \ 136 ldc1 $f24, (THREAD_FPU + 0x0c0)(thread); \ 137 ldc1 $f26, (THREAD_FPU + 0x0d0)(thread); \ 138 ldc1 $f28, (THREAD_FPU + 0x0e0)(thread); \ 139 ldc1 $f30, (THREAD_FPU + 0x0f0)(thread); \ 140 ctc1 tmp, fcr31 141 142#if defined(__MIPSEL__) 143#define FPU_RESTORE_SINGLE(thread,tmp) \ 144 lw tmp, (THREAD_FPU + 0x100)(thread); \ 145 lwc1 $f0, (THREAD_FPU + 0x000)(thread); \ 146 lwc1 $f1, (THREAD_FPU + 0x004)(thread); \ 147 lwc1 $f2, (THREAD_FPU + 0x010)(thread); \ 148 lwc1 $f3, (THREAD_FPU + 0x014)(thread); \ 149 lwc1 $f4, (THREAD_FPU + 0x020)(thread); \ 150 lwc1 $f5, (THREAD_FPU + 0x024)(thread); \ 151 lwc1 $f6, (THREAD_FPU + 0x030)(thread); \ 152 lwc1 $f7, (THREAD_FPU + 0x034)(thread); \ 153 lwc1 $f8, (THREAD_FPU + 0x040)(thread); \ 154 lwc1 $f9, (THREAD_FPU + 0x044)(thread); \ 155 lwc1 $f10, (THREAD_FPU + 0x050)(thread); \ 156 lwc1 $f11, (THREAD_FPU + 0x054)(thread); \ 157 lwc1 $f12, (THREAD_FPU + 0x060)(thread); \ 158 lwc1 $f13, (THREAD_FPU + 0x064)(thread); \ 159 lwc1 $f14, (THREAD_FPU + 0x070)(thread); \ 160 lwc1 $f15, (THREAD_FPU + 0x074)(thread); \ 161 lwc1 $f16, (THREAD_FPU + 0x080)(thread); \ 162 lwc1 $f17, (THREAD_FPU + 0x084)(thread); \ 163 lwc1 $f18, (THREAD_FPU + 0x090)(thread); \ 164 lwc1 $f19, (THREAD_FPU + 0x094)(thread); \ 165 lwc1 $f20, (THREAD_FPU + 0x0a0)(thread); \ 166 lwc1 $f21, (THREAD_FPU + 0x0a4)(thread); \ 167 lwc1 $f22, (THREAD_FPU + 0x0b0)(thread); \ 168 lwc1 $f23, (THREAD_FPU + 0x0b4)(thread); \ 169 lwc1 $f24, (THREAD_FPU + 0x0c0)(thread); \ 170 lwc1 $f25, (THREAD_FPU + 0x0c4)(thread); \ 171 lwc1 $f26, (THREAD_FPU + 0x0d0)(thread); \ 172 lwc1 $f27, (THREAD_FPU + 0x0d4)(thread); \ 173 lwc1 $f28, (THREAD_FPU + 0x0e0)(thread); \ 174 lwc1 $f29, (THREAD_FPU + 0x0e4)(thread); \ 175 lwc1 $f30, (THREAD_FPU + 0x0f0)(thread); \ 176 lwc1 $f31, (THREAD_FPU + 0x0f4)(thread); \ 177 ctc1 tmp, fcr31 178#elif defined(__MIPSEB__) 179#define FPU_RESTORE_SINGLE(thread,tmp) \ 180 lw tmp, (THREAD_FPU + 0x100)(thread); \ 181 lwc1 $f0, (THREAD_FPU + 0x004)(thread); \ 182 lwc1 $f1, (THREAD_FPU + 0x000)(thread); \ 183 lwc1 $f2, (THREAD_FPU + 0x014)(thread); \ 184 lwc1 $f3, (THREAD_FPU + 0x010)(thread); \ 185 lwc1 $f4, (THREAD_FPU + 0x024)(thread); \ 186 lwc1 $f5, (THREAD_FPU + 0x020)(thread); \ 187 lwc1 $f6, (THREAD_FPU + 0x034)(thread); \ 188 lwc1 $f7, (THREAD_FPU + 0x030)(thread); \ 189 lwc1 $f8, (THREAD_FPU + 0x044)(thread); \ 190 lwc1 $f9, (THREAD_FPU + 0x040)(thread); \ 191 lwc1 $f10, (THREAD_FPU + 0x054)(thread); \ 192 lwc1 $f11, (THREAD_FPU + 0x050)(thread); \ 193 lwc1 $f12, (THREAD_FPU + 0x064)(thread); \ 194 lwc1 $f13, (THREAD_FPU + 0x060)(thread); \ 195 lwc1 $f14, (THREAD_FPU + 0x074)(thread); \ 196 lwc1 $f15, (THREAD_FPU + 0x070)(thread); \ 197 lwc1 $f16, (THREAD_FPU + 0x084)(thread); \ 198 lwc1 $f17, (THREAD_FPU + 0x080)(thread); \ 199 lwc1 $f18, (THREAD_FPU + 0x094)(thread); \ 200 lwc1 $f19, (THREAD_FPU + 0x090)(thread); \ 201 lwc1 $f20, (THREAD_FPU + 0x0a4)(thread); \ 202 lwc1 $f21, (THREAD_FPU + 0x0a0)(thread); \ 203 lwc1 $f22, (THREAD_FPU + 0x0b4)(thread); \ 204 lwc1 $f23, (THREAD_FPU + 0x0b0)(thread); \ 205 lwc1 $f24, (THREAD_FPU + 0x0c4)(thread); \ 206 lwc1 $f25, (THREAD_FPU + 0x0c0)(thread); \ 207 lwc1 $f26, (THREAD_FPU + 0x0d4)(thread); \ 208 lwc1 $f27, (THREAD_FPU + 0x0d0)(thread); \ 209 lwc1 $f28, (THREAD_FPU + 0x0e4)(thread); \ 210 lwc1 $f29, (THREAD_FPU + 0x0e0)(thread); \ 211 lwc1 $f30, (THREAD_FPU + 0x0f4)(thread); \ 212 lwc1 $f31, (THREAD_FPU + 0x0f0)(thread); \ 213 ctc1 tmp, fcr31 214#else 215#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" 216#endif 217 218#define CPU_SAVE_NONSCRATCH(thread) \ 219 sw s0, THREAD_REG16(thread); \ 220 sw s1, THREAD_REG17(thread); \ 221 sw s2, THREAD_REG18(thread); \ 222 sw s3, THREAD_REG19(thread); \ 223 sw s4, THREAD_REG20(thread); \ 224 sw s5, THREAD_REG21(thread); \ 225 sw s6, THREAD_REG22(thread); \ 226 sw s7, THREAD_REG23(thread); \ 227 sw sp, THREAD_REG29(thread); \ 228 sw fp, THREAD_REG30(thread) 229 230#define CPU_RESTORE_NONSCRATCH(thread) \ 231 lw s0, THREAD_REG16(thread); \ 232 lw s1, THREAD_REG17(thread); \ 233 lw s2, THREAD_REG18(thread); \ 234 lw s3, THREAD_REG19(thread); \ 235 lw s4, THREAD_REG20(thread); \ 236 lw s5, THREAD_REG21(thread); \ 237 lw s6, THREAD_REG22(thread); \ 238 lw s7, THREAD_REG23(thread); \ 239 lw sp, THREAD_REG29(thread); \ 240 lw fp, THREAD_REG30(thread); \ 241 lw ra, THREAD_REG31(thread) 242 243#endif /* _ASM_ASMMACRO_H */ 244