1/* $Id: chafsr.h,v 1.1.1.1 2008/10/15 03:27:26 james26_jang Exp $ */ 2#ifndef _SPARC64_CHAFSR_H 3#define _SPARC64_CHAFSR_H 4 5/* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */ 6 7/* All bits of this register except M_SYNDROME and E_SYNDROME are 8 * read, write 1 to clear. M_SYNDROME and E_SYNDROME are read-only. 9 */ 10 11/* Multiple errors of the same type have occurred. This bit is set when 12 * an uncorrectable error or a SW correctable error occurs and the status 13 * bit to report that error is already set. When multiple errors of 14 * different types are indicated by setting multiple status bits. 15 * 16 * This bit is not set if multiple HW corrected errors with the same 17 * status bit occur, only uncorrectable and SW correctable ones have 18 * this behavior. 19 * 20 * This bit is not set when multiple ECC errors happen within a single 21 * 64-byte system bus transaction. Only the first ECC error in a 16-byte 22 * subunit will be logged. All errors in subsequent 16-byte subunits 23 * from the same 64-byte transaction are ignored. 24 */ 25#define CHAFSR_ME 0x0020000000000000 26 27/* Privileged state error has occurred. This is a capture of PSTATE.PRIV 28 * at the time the error is detected. 29 */ 30#define CHAFSR_PRIV 0x0010000000000000 31 32/* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error 33 * bits and record the most recently detected errors. Bits accumulate 34 * errors that have been detected since the last write to clear the bit. 35 */ 36 37/* System interface protocol error. The processor asserts its' ERROR 38 * pin when this event occurs and it also logs a specific cause code 39 * into a JTAG scannable flop. 40 */ 41#define CHAFSR_PERR 0x0008000000000000 42 43/* Internal processor error. The processor asserts its' ERROR 44 * pin when this event occurs and it also logs a specific cause code 45 * into a JTAG scannable flop. 46 */ 47#define CHAFSR_IERR 0x0004000000000000 48 49/* System request parity error on incoming address */ 50#define CHAFSR_ISAP 0x0002000000000000 51 52/* HW Corrected system bus MTAG ECC error */ 53#define CHAFSR_EMC 0x0001000000000000 54 55/* Uncorrectable system bus MTAG ECC error */ 56#define CHAFSR_EMU 0x0000800000000000 57 58/* HW Corrected system bus data ECC error for read of interrupt vector */ 59#define CHAFSR_IVC 0x0000400000000000 60 61/* Uncorrectable system bus data ECC error for read of interrupt vector */ 62#define CHAFSR_IVU 0x0000200000000000 63 64/* Unmappeed error from system bus */ 65#define CHAFSR_TO 0x0000100000000000 66 67/* Bus error response from system bus */ 68#define CHAFSR_BERR 0x0000080000000000 69 70/* SW Correctable E-cache ECC error for instruction fetch or data access 71 * other than block load. 72 */ 73#define CHAFSR_UCC 0x0000040000000000 74 75/* Uncorrectable E-cache ECC error for instruction fetch or data access 76 * other than block load. 77 */ 78#define CHAFSR_UCU 0x0000020000000000 79 80/* Copyout HW Corrected ECC error */ 81#define CHAFSR_CPC 0x0000010000000000 82 83/* Copyout Uncorrectable ECC error */ 84#define CHAFSR_CPU 0x0000008000000000 85 86/* HW Corrected ECC error from E-cache for writeback */ 87#define CHAFSR_WDC 0x0000004000000000 88 89/* Uncorrectable ECC error from E-cache for writeback */ 90#define CHAFSR_WDU 0x0000002000000000 91 92/* HW Corrected ECC error from E-cache for store merge or block load */ 93#define CHAFSR_EDC 0x0000001000000000 94 95/* Uncorrectable ECC error from E-cache for store merge or block load */ 96#define CHAFSR_EDU 0x0000000800000000 97 98/* Uncorrectable system bus data ECC error for read of memory or I/O */ 99#define CHAFSR_UE 0x0000000400000000 100 101/* HW Corrected system bus data ECC error for read of memory or I/O */ 102#define CHAFSR_CE 0x0000000200000000 103 104#define CHAFSR_ERRORS (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \ 105 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \ 106 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \ 107 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \ 108 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE) 109 110/* System bus MTAG ECC syndrome. This field captures the status of the 111 * first occurrence of the highest-priority error according to the M_SYND 112 * overwrite policy. After the AFSR sticky bit, corresponding to the error 113 * for which the M_SYND is reported, is cleared, the contents of the M_SYND 114 * field will be unchanged by will be unfrozen for further error capture. 115 */ 116#define CHAFSR_M_SYNDROME 0x00000000000f0000 117#define CHAFSR_M_SYNDROME_SHIFT 16 118 119/* System bus or E-cache data ECC syndrome. This field captures the status 120 * of the first occurrence of the highest-priority error according to the 121 * E_SYND overwrite policy. After the AFSR sticky bit, corresponding to the 122 * error for which the E_SYND is reported, is cleare, the contents of the E_SYND 123 * field will be unchanged but will be unfrozen for further error capture. 124 */ 125#define CHAFSR_E_SYNDROME 0x00000000000001ff 126#define CHAFSR_E_SYNDROME_SHIFT 0 127 128/* The AFSR must be explicitly cleared by software, it is not cleared automatically 129 * by a read. Writes to bits <51:33> with bits set will clear the corresponding 130 * bits in the AFSR. Bits assosciated with disrupting traps must be cleared before 131 * interrupts are re-enabled to prevent multiple traps for the same error. I.e. 132 * PSTATE.IE and AFSR bits control delivery of disrupting traps. 133 * 134 * Since there is only one AFAR, when multiple events have been logged by the 135 * bits in the AFSR, at most one of these events will have its status captured 136 * in the AFAR. The highest priority of those event bits will get AFAR logging. 137 * The AFAR will be unlocked and available to capture the address of another event 138 * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is 139 * cleared. For example, if AFSR.CE is detected, then AFSR.UE (which overwrites 140 * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked 141 * and ready for another event, even though AFSR.CE is still set. The same rules 142 * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR. 143 */ 144 145/* Software bit set by linux trap handlers to indicate that the trap was 146 * signalled at %tl >= 1. 147 */ 148#define CHAFSR_TL1 0x8000000000000000 149 150#endif /* _SPARC64_CHAFSR_H */ 151