1 2/* 3 * include/asm-s390/lowcore.h 4 * 5 * S390 version 6 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation 7 * Author(s): Hartmut Penner (hpenner@de.ibm.com), 8 * Martin Schwidefsky (schwidefsky@de.ibm.com), 9 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com) 10 */ 11 12#ifndef _ASM_S390_LOWCORE_H 13#define _ASM_S390_LOWCORE_H 14 15#define __LC_EXT_OLD_PSW 0x0130 16#define __LC_SVC_OLD_PSW 0x0140 17#define __LC_PGM_OLD_PSW 0x0150 18#define __LC_MCK_OLD_PSW 0x0160 19#define __LC_IO_OLD_PSW 0x0170 20#define __LC_EXT_NEW_PSW 0x01b0 21#define __LC_SVC_NEW_PSW 0x01c0 22#define __LC_PGM_NEW_PSW 0x01d0 23#define __LC_MCK_NEW_PSW 0x01e0 24#define __LC_IO_NEW_PSW 0x01f0 25#define __LC_RETURN_PSW 0x0200 26#define __LC_SYNC_IO_WORD 0x0210 27#define __LC_EXT_PARAMS 0x080 28#define __LC_CPU_ADDRESS 0x084 29#define __LC_EXT_INT_CODE 0x086 30#define __LC_SVC_ILC 0x088 31#define __LC_SVC_INT_CODE 0x08A 32#define __LC_PGM_ILC 0x08C 33#define __LC_PGM_INT_CODE 0x08E 34#define __LC_TRANS_EXC_ADDR 0x0a8 35#define __LC_SUBCHANNEL_ID 0x0B8 36#define __LC_SUBCHANNEL_NR 0x0BA 37#define __LC_IO_INT_PARM 0x0BC 38#define __LC_IO_INT_WORD 0x0C0 39#define __LC_MCCK_CODE 0x0E8 40 41#define __LC_DIAG44_OPCODE 0x214 42 43#define __LC_SAVE_AREA 0xC00 44#define __LC_KERNEL_STACK 0xD40 45#define __LC_ASYNC_STACK 0xD48 46#define __LC_CPUID 0xD90 47#define __LC_CPUADDR 0xD98 48#define __LC_IPLDEV 0xDB8 49 50#define __LC_JIFFY_TIMER 0xDC0 51 52#define __LC_PANIC_MAGIC 0xE00 53 54#define __LC_AREGS_SAVE_AREA 0x1340 55#define __LC_CREGS_SAVE_AREA 0x1380 56 57#define __LC_PFAULT_INTPARM 0x11B8 58 59/* interrupt handler start with all io, external and mcck interrupt disabled */ 60 61#define _RESTART_PSW_MASK 0x0000000180000000 62#define _EXT_PSW_MASK 0x0400000180000000 63#define _PGM_PSW_MASK 0x0400000180000000 64#define _SVC_PSW_MASK 0x0400000180000000 65#define _MCCK_PSW_MASK 0x0400000180000000 66#define _IO_PSW_MASK 0x0400000180000000 67#define _USER_PSW_MASK 0x0705C00180000000 68#define _WAIT_PSW_MASK 0x0706000180000000 69#define _DW_PSW_MASK 0x0002000180000000 70 71#define _PRIMARY_MASK 0x0000 /* MASK for SACF */ 72#define _SECONDARY_MASK 0x0100 /* MASK for SACF */ 73#define _ACCESS_MASK 0x0200 /* MASK for SACF */ 74#define _HOME_MASK 0x0300 /* MASK for SACF */ 75 76#define _PSW_PRIM_SPACE_MODE 0x0000000000000000 77#define _PSW_SEC_SPACE_MODE 0x0000800000000000 78#define _PSW_ACC_REG_MODE 0x0000400000000000 79#define _PSW_HOME_SPACE_MODE 0x0000C00000000000 80 81#define _PSW_WAIT_MASK_BIT 0x0002000000000000 82#define _PSW_IO_MASK_BIT 0x0200000000000000 83#define _PSW_IO_WAIT 0x0202000000000000 84 85#ifndef __ASSEMBLY__ 86 87#include <linux/config.h> 88#include <asm/processor.h> 89#include <linux/types.h> 90#include <asm/atomic.h> 91#include <asm/sigp.h> 92 93void restart_int_handler(void); 94void ext_int_handler(void); 95void system_call(void); 96void pgm_check_handler(void); 97void mcck_int_handler(void); 98void io_int_handler(void); 99 100struct _lowcore 101{ 102 /* prefix area: defined by architecture */ 103 __u32 ccw1[2]; /* 0x000 */ 104 __u32 ccw2[4]; /* 0x008 */ 105 __u8 pad1[0x80-0x18]; /* 0x018 */ 106 __u32 ext_params; /* 0x080 */ 107 __u16 cpu_addr; /* 0x084 */ 108 __u16 ext_int_code; /* 0x086 */ 109 __u16 svc_ilc; /* 0x088 */ 110 __u16 svc_code; /* 0x08a */ 111 __u16 pgm_ilc; /* 0x08c */ 112 __u16 pgm_code; /* 0x08e */ 113 __u32 data_exc_code; /* 0x090 */ 114 __u16 mon_class_num; /* 0x094 */ 115 __u16 per_perc_atmid; /* 0x096 */ 116 addr_t per_address; /* 0x098 */ 117 __u8 exc_access_id; /* 0x0a0 */ 118 __u8 per_access_id; /* 0x0a1 */ 119 __u8 op_access_id; /* 0x0a2 */ 120 __u8 ar_access_id; /* 0x0a3 */ 121 __u8 pad2[0xA8-0xA4]; /* 0x0a4 */ 122 addr_t trans_exc_code; /* 0x0A0 */ 123 addr_t monitor_code; /* 0x09c */ 124 __u16 subchannel_id; /* 0x0b8 */ 125 __u16 subchannel_nr; /* 0x0ba */ 126 __u32 io_int_parm; /* 0x0bc */ 127 __u32 io_int_word; /* 0x0c0 */ 128 __u8 pad3[0xc8-0xc4]; /* 0x0c4 */ 129 __u32 stfl_fac_list; /* 0x0c8 */ 130 __u8 pad4[0xe8-0xcc]; /* 0x0cc */ 131 __u32 mcck_interruption_code[2]; /* 0x0e8 */ 132 __u8 pad5[0xf4-0xf0]; /* 0x0f0 */ 133 __u32 external_damage_code; /* 0x0f4 */ 134 addr_t failing_storage_address; /* 0x0f8 */ 135 __u8 pad6[0x120-0x100]; /* 0x100 */ 136 psw_t restart_old_psw; /* 0x120 */ 137 psw_t external_old_psw; /* 0x130 */ 138 psw_t svc_old_psw; /* 0x140 */ 139 psw_t program_old_psw; /* 0x150 */ 140 psw_t mcck_old_psw; /* 0x160 */ 141 psw_t io_old_psw; /* 0x170 */ 142 __u8 pad7[0x1a0-0x180]; /* 0x180 */ 143 psw_t restart_psw; /* 0x1a0 */ 144 psw_t external_new_psw; /* 0x1b0 */ 145 psw_t svc_new_psw; /* 0x1c0 */ 146 psw_t program_new_psw; /* 0x1d0 */ 147 psw_t mcck_new_psw; /* 0x1e0 */ 148 psw_t io_new_psw; /* 0x1f0 */ 149 psw_t return_psw; /* 0x200 */ 150 __u32 sync_io_word; /* 0x210 */ 151 __u32 diag44_opcode; /* 0x214 */ 152 __u8 pad8[0xc00-0x218]; /* 0x218 */ 153 /* System info area */ 154 __u64 save_area[16]; /* 0xc00 */ 155 __u8 pad9[0xd40-0xc80]; /* 0xc80 */ 156 __u64 kernel_stack; /* 0xd40 */ 157 __u64 async_stack; /* 0xd48 */ 158 /* entry.S sensitive area start */ 159 __u8 pad10[0xd80-0xd50]; /* 0xd64 */ 160 struct cpuinfo_S390 cpu_data; /* 0xd80 */ 161 __u32 ipl_device; /* 0xdb8 */ 162 __u32 pad11; /* 0xdbc was lsw word of ipl_device until a bug was found DJB */ 163 /* entry.S sensitive area end */ 164 165 /* SMP info area: defined by DJB */ 166 __u64 jiffy_timer; /* 0xdc0 */ 167 __u64 ext_call_fast; /* 0xdc8 */ 168 __u8 pad12[0xe00-0xdd0]; /* 0xdd0 */ 169 170 /* 0xe00 is used as indicator for dump tools */ 171 /* whether the kernel died with panic() or not */ 172 __u32 panic_magic; /* 0xe00 */ 173 174 __u8 pad13[0x1200-0xe04]; /* 0xe04 */ 175 176 /* System info area */ 177 178 __u64 floating_pt_save_area[16]; /* 0x1200 */ 179 __u64 gpregs_save_area[16]; /* 0x1280 */ 180 __u32 st_status_fixed_logout[4]; /* 0x1300 */ 181 __u8 pad14[0x1318-0x1310]; /* 0x1310 */ 182 __u32 prefixreg_save_area; /* 0x1318 */ 183 __u32 fpt_creg_save_area; /* 0x131c */ 184 __u8 pad15[0x1324-0x1320]; /* 0x1320 */ 185 __u32 tod_progreg_save_area; /* 0x1324 */ 186 __u32 cpu_timer_save_area[2]; /* 0x1328 */ 187 __u32 clock_comp_save_area[2]; /* 0x1330 */ 188 __u8 pad16[0x1340-0x1338]; /* 0x1338 */ 189 __u32 access_regs_save_area[16]; /* 0x1340 */ 190 __u64 cregs_save_area[16]; /* 0x1380 */ 191 192 /* align to the top of the prefix area */ 193 194 __u8 pad17[0x2000-0x1400]; /* 0x1400 */ 195} __attribute__((packed)); /* End structure*/ 196 197extern __inline__ void set_prefix(__u32 address) 198{ 199 __asm__ __volatile__ ("spx %0" : : "m" (address) : "memory" ); 200} 201 202#define S390_lowcore (*((struct _lowcore *) 0)) 203extern struct _lowcore *lowcore_ptr[]; 204 205#ifndef CONFIG_SMP 206#define get_cpu_lowcore(cpu) (&S390_lowcore) 207#define safe_get_cpu_lowcore(cpu) (&S390_lowcore) 208#else 209#define get_cpu_lowcore(cpu) (lowcore_ptr[(cpu)]) 210#define safe_get_cpu_lowcore(cpu) \ 211 ((cpu) == smp_processor_id() ? &S390_lowcore : lowcore_ptr[(cpu)]) 212#endif 213#endif /* __ASSEMBLY__ */ 214 215#define __PANIC_MAGIC 0xDEADC0DE 216 217#endif 218 219