1/* 2 * BK Id: SCCS/s.dma.h 1.8 05/17/01 18:14:24 cort 3 */ 4/* 5 * linux/include/asm/dma.h: Defines for using and allocating dma channels. 6 * Written by Hennus Bergman, 1992. 7 * High DMA channel support & info by Hannu Savolainen 8 * and John Boyd, Nov. 1992. 9 * Changes for ppc sound by Christoph Nadig 10 */ 11 12#ifdef __KERNEL__ 13 14#include <linux/config.h> 15#include <asm/io.h> 16#include <linux/spinlock.h> 17#include <asm/system.h> 18 19/* 20 * Note: Adapted for PowerPC by Gary Thomas 21 * Modified by Cort Dougan <cort@cs.nmt.edu> 22 * 23 * None of this really applies for Power Macintoshes. There is 24 * basically just enough here to get kernel/dma.c to compile. 25 * 26 * There may be some comments or restrictions made here which are 27 * not valid for the PReP platform. Take what you read 28 * with a grain of salt. 29 */ 30 31 32#ifndef _ASM_DMA_H 33#define _ASM_DMA_H 34 35#ifndef MAX_DMA_CHANNELS 36#define MAX_DMA_CHANNELS 8 37#endif 38 39/* The maximum address that we can perform a DMA transfer to on this platform */ 40/* Doesn't really apply... */ 41#define MAX_DMA_ADDRESS 0xFFFFFFFF 42 43/* in arch/ppc/kernel/setup.c -- Cort */ 44extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ; 45extern unsigned long ISA_DMA_THRESHOLD; 46 47 48#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER 49#define dma_outb outb_p 50#else 51#define dma_outb outb 52#endif 53 54#define dma_inb inb 55 56/* 57 * NOTES about DMA transfers: 58 * 59 * controller 1: channels 0-3, byte operations, ports 00-1F 60 * controller 2: channels 4-7, word operations, ports C0-DF 61 * 62 * - ALL registers are 8 bits only, regardless of transfer size 63 * - channel 4 is not used - cascades 1 into 2. 64 * - channels 0-3 are byte - addresses/counts are for physical bytes 65 * - channels 5-7 are word - addresses/counts are for physical words 66 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries 67 * - transfer count loaded to registers is 1 less than actual count 68 * - controller 2 offsets are all even (2x offsets for controller 1) 69 * - page registers for 5-7 don't use data bit 0, represent 128K pages 70 * - page registers for 0-3 use bit 0, represent 64K pages 71 * 72 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. 73 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing. 74 * Note that addresses loaded into registers must be _physical_ addresses, 75 * not logical addresses (which may differ if paging is active). 76 * 77 * Address mapping for channels 0-3: 78 * 79 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) 80 * | ... | | ... | | ... | 81 * | ... | | ... | | ... | 82 * | ... | | ... | | ... | 83 * P7 ... P0 A7 ... A0 A7 ... A0 84 * | Page | Addr MSB | Addr LSB | (DMA registers) 85 * 86 * Address mapping for channels 5-7: 87 * 88 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) 89 * | ... | \ \ ... \ \ \ ... \ \ 90 * | ... | \ \ ... \ \ \ ... \ (not used) 91 * | ... | \ \ ... \ \ \ ... \ 92 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 93 * | Page | Addr MSB | Addr LSB | (DMA registers) 94 * 95 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses 96 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at 97 * the hardware level, so odd-byte transfers aren't possible). 98 * 99 * Transfer count (_not # bytes_) is limited to 64K, represented as actual 100 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, 101 * and up to 128K bytes may be transferred on channels 5-7 in one operation. 102 * 103 */ 104 105/* used in nasty hack for sound - see prep_setup_arch() -- Cort */ 106extern long ppc_cs4232_dma, ppc_cs4232_dma2; 107#if defined(CONFIG_CS4232) 108#if defined(CONFIG_ALL_PPC) 109#define SND_DMA1 ppc_cs4232_dma 110#define SND_DMA2 ppc_cs4232_dma2 111#else /* !CONFIG_ALL_PPC */ 112#define SND_DMA1 -1 113#define SND_DMA2 -1 114#endif /* CONFIG_ALL_PPC */ 115#elif defined(CONFIG_MSS) 116#define SND_DMA1 CONFIG_MSS_DMA 117#define SND_DMA2 CONFIG_MSS_DMA2 118#else 119#define SND_DMA1 -1 120#define SND_DMA2 -1 121#endif 122 123/* 8237 DMA controllers */ 124#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 125#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 126 127/* DMA controller registers */ 128#define DMA1_CMD_REG 0x08 /* command register (w) */ 129#define DMA1_STAT_REG 0x08 /* status register (r) */ 130#define DMA1_REQ_REG 0x09 /* request register (w) */ 131#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 132#define DMA1_MODE_REG 0x0B /* mode register (w) */ 133#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 134#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 135#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 136#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 137#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 138 139#define DMA2_CMD_REG 0xD0 /* command register (w) */ 140#define DMA2_STAT_REG 0xD0 /* status register (r) */ 141#define DMA2_REQ_REG 0xD2 /* request register (w) */ 142#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 143#define DMA2_MODE_REG 0xD6 /* mode register (w) */ 144#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 145#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 146#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 147#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 148#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 149 150#define DMA_ADDR_0 0x00 /* DMA address registers */ 151#define DMA_ADDR_1 0x02 152#define DMA_ADDR_2 0x04 153#define DMA_ADDR_3 0x06 154#define DMA_ADDR_4 0xC0 155#define DMA_ADDR_5 0xC4 156#define DMA_ADDR_6 0xC8 157#define DMA_ADDR_7 0xCC 158 159#define DMA_CNT_0 0x01 /* DMA count registers */ 160#define DMA_CNT_1 0x03 161#define DMA_CNT_2 0x05 162#define DMA_CNT_3 0x07 163#define DMA_CNT_4 0xC2 164#define DMA_CNT_5 0xC6 165#define DMA_CNT_6 0xCA 166#define DMA_CNT_7 0xCE 167 168#define DMA_LO_PAGE_0 0x87 /* DMA page registers */ 169#define DMA_LO_PAGE_1 0x83 170#define DMA_LO_PAGE_2 0x81 171#define DMA_LO_PAGE_3 0x82 172#define DMA_LO_PAGE_5 0x8B 173#define DMA_LO_PAGE_6 0x89 174#define DMA_LO_PAGE_7 0x8A 175 176#define DMA_HI_PAGE_0 0x487 /* DMA page registers */ 177#define DMA_HI_PAGE_1 0x483 178#define DMA_HI_PAGE_2 0x481 179#define DMA_HI_PAGE_3 0x482 180#define DMA_HI_PAGE_5 0x48B 181#define DMA_HI_PAGE_6 0x489 182#define DMA_HI_PAGE_7 0x48A 183 184#define DMA1_EXT_REG 0x40B 185#define DMA2_EXT_REG 0x4D6 186 187#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 188#define DMA_AUTOINIT 0x10 189 190extern spinlock_t dma_spin_lock; 191 192static __inline__ unsigned long claim_dma_lock(void) 193{ 194 unsigned long flags; 195 spin_lock_irqsave(&dma_spin_lock, flags); 196 return flags; 197} 198 199static __inline__ void release_dma_lock(unsigned long flags) 200{ 201 spin_unlock_irqrestore(&dma_spin_lock, flags); 202} 203 204/* enable/disable a specific DMA channel */ 205static __inline__ void enable_dma(unsigned int dmanr) 206{ 207 unsigned char ucDmaCmd=0x00; 208 209 if (dmanr != 4) 210 { 211 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ 212 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ 213 } 214 if (dmanr<=3) 215 { 216 dma_outb(dmanr, DMA1_MASK_REG); 217 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ 218 } else 219 { 220 dma_outb(dmanr & 3, DMA2_MASK_REG); 221 } 222} 223 224static __inline__ void disable_dma(unsigned int dmanr) 225{ 226 if (dmanr<=3) 227 dma_outb(dmanr | 4, DMA1_MASK_REG); 228 else 229 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 230} 231 232/* Clear the 'DMA Pointer Flip Flop'. 233 * Write 0 for LSB/MSB, 1 for MSB/LSB access. 234 * Use this once to initialize the FF to a known state. 235 * After that, keep track of it. :-) 236 * --- In order to do that, the DMA routines below should --- 237 * --- only be used while interrupts are disabled! --- 238 */ 239static __inline__ void clear_dma_ff(unsigned int dmanr) 240{ 241 if (dmanr<=3) 242 dma_outb(0, DMA1_CLEAR_FF_REG); 243 else 244 dma_outb(0, DMA2_CLEAR_FF_REG); 245} 246 247/* set mode (above) for a specific DMA channel */ 248static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 249{ 250 if (dmanr<=3) 251 dma_outb(mode | dmanr, DMA1_MODE_REG); 252 else 253 dma_outb(mode | (dmanr&3), DMA2_MODE_REG); 254} 255 256/* Set only the page register bits of the transfer address. 257 * This is used for successive transfers when we know the contents of 258 * the lower 16 bits of the DMA current address register, but a 64k boundary 259 * may have been crossed. 260 */ 261static __inline__ void set_dma_page(unsigned int dmanr, int pagenr) 262{ 263 switch(dmanr) { 264 case 0: 265 dma_outb(pagenr, DMA_LO_PAGE_0); 266 dma_outb(pagenr>>8, DMA_HI_PAGE_0); 267 break; 268 case 1: 269 dma_outb(pagenr, DMA_LO_PAGE_1); 270 dma_outb(pagenr>>8, DMA_HI_PAGE_1); 271 break; 272 case 2: 273 dma_outb(pagenr, DMA_LO_PAGE_2); 274 dma_outb(pagenr>>8, DMA_HI_PAGE_2); 275 break; 276 case 3: 277 dma_outb(pagenr, DMA_LO_PAGE_3); 278 dma_outb(pagenr>>8, DMA_HI_PAGE_3); 279 break; 280 case 5: 281 if (SND_DMA1 == 5 || SND_DMA2 == 5) 282 dma_outb(pagenr, DMA_LO_PAGE_5); 283 else 284 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5); 285 dma_outb(pagenr>>8, DMA_HI_PAGE_5); 286 break; 287 case 6: 288 if (SND_DMA1 == 6 || SND_DMA2 == 6) 289 dma_outb(pagenr, DMA_LO_PAGE_6); 290 else 291 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6); 292 dma_outb(pagenr>>8, DMA_HI_PAGE_6); 293 break; 294 case 7: 295 if (SND_DMA1 == 7 || SND_DMA2 == 7) 296 dma_outb(pagenr, DMA_LO_PAGE_7); 297 else 298 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7); 299 dma_outb(pagenr>>8, DMA_HI_PAGE_7); 300 break; 301 } 302} 303 304 305/* Set transfer address & page bits for specific DMA channel. 306 * Assumes dma flipflop is clear. 307 */ 308static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys) 309{ 310 if (dmanr <= 3) { 311 dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 312 dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); 313 } else { 314 if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { 315 dma_outb( phys & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 316 dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 317 dma_outb( (dmanr&3), DMA2_EXT_REG); 318 } else { 319 dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 320 dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); 321 } 322 } 323 set_dma_page(dmanr, phys>>16); 324} 325 326 327/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for 328 * a specific DMA channel. 329 * You must ensure the parameters are valid. 330 * NOTE: from a manual: "the number of transfers is one more 331 * than the initial word count"! This is taken into account. 332 * Assumes dma flip-flop is clear. 333 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 334 */ 335static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 336{ 337 count--; 338 if (dmanr <= 3) { 339 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 340 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); 341 } else { 342 if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { 343 dma_outb( count & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 344 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 345 } else { 346 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 347 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); 348 } 349 } 350} 351 352 353/* Get DMA residue count. After a DMA transfer, this 354 * should return zero. Reading this while a DMA transfer is 355 * still in progress will return unpredictable results. 356 * If called before the channel has been used, it may return 1. 357 * Otherwise, it returns the number of _bytes_ left to transfer. 358 * 359 * Assumes DMA flip-flop is clear. 360 */ 361static __inline__ int get_dma_residue(unsigned int dmanr) 362{ 363 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE 364 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; 365 366 /* using short to get 16-bit wrap around */ 367 unsigned short count; 368 369 count = 1 + dma_inb(io_port); 370 count += dma_inb(io_port) << 8; 371 372 return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2) 373 ? count : (count<<1); 374} 375 376/* These are in kernel/dma.c: */ 377extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ 378extern void free_dma(unsigned int dmanr); /* release it again */ 379 380#ifdef CONFIG_PCI 381extern int isa_dma_bridge_buggy; 382#else 383#define isa_dma_bridge_buggy (0) 384#endif 385#endif /* _ASM_DMA_H */ 386#endif /* __KERNEL__ */ 387