1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126. 7 * 8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. 9 * Copyright (C) 1999 by Ralf Baechle 10 */ 11#ifndef _ASM_SN_SN0_ADDRS_H 12#define _ASM_SN_SN0_ADDRS_H 13 14#include <linux/config.h> 15 16/* 17 * SN0 (on a T5) Address map 18 * 19 * This file contains a set of definitions and macros which are used 20 * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, 21 * and UNCAC) used by the SN0 architecture. It also contains addresses 22 * for "major" statically locatable PROM/Kernel data structures, such as 23 * the partition table, the configuration data structure, etc. 24 * We make an implicit assumption that the processor using this file 25 * follows the R10K's provisions for specifying uncached attributes; 26 * should this change, the base registers may very well become processor- 27 * dependent. 28 * 29 * For more information on the address spaces, see the "Local Resources" 30 * chapter of the Hub specification. 31 * 32 * NOTE: This header file is included both by C and by assembler source 33 * files. Please bracket any language-dependent definitions 34 * appropriately. 35 */ 36 37/* 38 * Some of the macros here need to be casted to appropriate types when used 39 * from C. They definitely must not be casted from assembly language so we 40 * use some new ANSI preprocessor stuff to paste these on where needed. 41 */ 42 43#define CAC_BASE 0xa800000000000000 44 45#define HSPEC_BASE 0x9000000000000000 46#define IO_BASE 0x9200000000000000 47#define MSPEC_BASE 0x9400000000000000 48#define __UNCAC_BASE 0x9600000000000000 49 50#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) 51#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) 52#define TO_UNCAC(x) (__UNCAC_BASE | ((x) & TO_PHYS_MASK)) 53#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK)) 54#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK)) 55 56 57/* 58 * The following couple of definitions will eventually need to be variables, 59 * since the amount of address space assigned to each node depends on 60 * whether the system is running in N-mode (more nodes with less memory) 61 * or M-mode (fewer nodes with more memory). We expect that it will 62 * be a while before we need to make this decision dynamically, though, 63 * so for now we just use defines bracketed by an ifdef. 64 */ 65 66#ifdef CONFIG_SGI_SN0_N_MODE 67 68#define NODE_SIZE_BITS 31 69#define BWIN_SIZE_BITS 28 70 71#define NASID_BITS 9 72#define NASID_BITMASK (0x1ffLL) 73#define NASID_SHFT 31 74#define NASID_META_BITS 5 75#define NASID_LOCAL_BITS 4 76 77#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10) 78#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3) 79 80#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */ 81 82#define NODE_SIZE_BITS 32 83#define BWIN_SIZE_BITS 29 84 85#define NASID_BITMASK (0xffLL) 86#define NASID_BITS 8 87#define NASID_SHFT 32 88#define NASID_META_BITS 4 89#define NASID_LOCAL_BITS 4 90 91#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10) 92#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3) 93 94#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */ 95 96#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) 97 98#define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) 99#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ 100 NASID_SHFT) & NASID_BITMASK) 101 102#if !defined(__ASSEMBLY__) && !defined(_STANDALONE) 103#define NODE_SWIN_BASE(nasid, widget) \ 104 ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ 105 : RAW_NODE_SWIN_BASE(nasid, widget)) 106#else /* __ASSEMBLY__ || _STANDALONE */ 107#define NODE_SWIN_BASE(nasid, widget) \ 108 (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) 109#endif /* __ASSEMBLY__ || _STANDALONE */ 110 111/* 112 * The following definitions pertain to the IO special address 113 * space. They define the location of the big and little windows 114 * of any given node. 115 */ 116 117#define BWIN_INDEX_BITS 3 118#define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) 119#define BWIN_SIZEMASK (BWIN_SIZE - 1) 120#define BWIN_WIDGET_MASK 0x7 121#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) 122#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ 123 (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) 124 125#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) 126#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) 127/* 128 * Verify if addr belongs to large window address of node with "nasid" 129 * 130 * 131 * NOTE: "addr" is expected to be XKPHYS address, and NOT physical 132 * address 133 * 134 * 135 */ 136 137#define NODE_BWIN_ADDR(nasid, addr) \ 138 (((addr) >= NODE_BWIN_BASE0(nasid)) && \ 139 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ 140 BWIN_SIZE))) 141 142/* 143 * The following define the major position-independent aliases used 144 * in SN0. 145 * CALIAS -- Varies in size, points to the first n bytes of memory 146 * on the reader's node. 147 */ 148 149#define CALIAS_BASE CAC_BASE 150 151 152 153#define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ 154 ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) 155 156#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) 157 158/* Turn on sable logging for the processors whose bits are set. */ 159#ifdef SABLE 160#define SABLE_LOG_TRIGGER(_map) \ 161 *((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map) 162#else 163#define SABLE_LOG_TRIGGER(_map) 164#endif /* SABLE */ 165 166#ifndef __ASSEMBLY__ 167#define KERN_NMI_ADDR(nasid, slice) \ 168 TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ 169 (IP27_NMI_KREGS_CPU_SIZE * (slice))) 170#endif /* !__ASSEMBLY__ */ 171 172#ifdef PROM 173 174#define MISC_PROM_BASE PHYS_TO_K0(0x01300000) 175#define MISC_PROM_SIZE 0x200000 176 177#define DIAG_BASE PHYS_TO_K0(0x01500000) 178#define DIAG_SIZE 0x300000 179 180#define ROUTE_BASE PHYS_TO_K0(0x01800000) 181#define ROUTE_SIZE 0x200000 182 183#define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000) 184#define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000) 185#define IP27PROM_CORP_MAX 32 186#define IP27PROM_CORP PHYS_TO_K0(0x01800000) 187#define IP27PROM_CORP_SIZE 0x10000 188#define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000) 189#define IP27PROM_CORP_STKSIZE 0x2000 190#define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000) 191#define IP27PROM_DECOMP_SIZE 0xfff00 192 193#define IP27PROM_BASE PHYS_TO_K0(0x01a00000) 194#define IP27PROM_BASE_MAPPED (K2BASE | 0x1fc00000) 195#define IP27PROM_SIZE_MAX 0x100000 196 197#define IP27PROM_PCFG PHYS_TO_K0(0x01b00000) 198#define IP27PROM_PCFG_SIZE 0xd0000 199#define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000) 200#define IP27PROM_ERRDMP_SIZE 0xf000 201 202#define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000) 203#define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000) 204#define IP27PROM_CONSOLE_SIZE 0x200 205#define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200) 206#define IP27PROM_NETUART_SIZE 0x100 207#define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300) 208#define IP27PROM_UNUSED1_SIZE 0x500 209#define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800) 210#define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00) 211#define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000) 212#define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000) 213#define IP27PROM_STACK_SHFT 16 214#define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT) 215#define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000) 216 217#define SLAVESTACK_BASE PHYS_TO_K0(0x01580000) 218#define SLAVESTACK_SIZE 0x40000 219 220#define ENETBUFS_BASE PHYS_TO_K0(0x01f80000) 221#define ENETBUFS_SIZE 0x20000 222 223#define IO6PROM_BASE PHYS_TO_K0(0x01c00000) 224#define IO6PROM_SIZE 0x400000 225#define IO6PROM_BASE_MAPPED (K2BASE | 0x11c00000) 226#define IO6DPROM_BASE PHYS_TO_K0(0x01c00000) 227#define IO6DPROM_SIZE 0x200000 228 229#define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000) 230#define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000) 231 232#define IP27PROM_INT_LAUNCH 10 /* and 11 */ 233#define IP27PROM_INT_NETUART 12 /* through 17 */ 234 235#endif /* PROM */ 236 237/* 238 * needed by symmon so it needs to be outside #if PROM 239 */ 240#define IP27PROM_ELSC_SHFT 10 241#define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT) 242 243/* 244 * This address is used by IO6PROM to build MemoryDescriptors of 245 * free memory. This address is important since unix gets loaded 246 * at this address, and this memory has to be FREE if unix is to 247 * be loaded. 248 */ 249 250#define FREEMEM_BASE PHYS_TO_K0(0x2000000) 251 252#define IO6PROM_STACK_SHFT 14 /* stack per cpu */ 253#define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT) 254 255/* 256 * IP27 PROM vectors 257 */ 258 259#define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000) 260#define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008) 261#define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010) 262#define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018) 263#define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020) 264#define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028) 265#define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030) 266#define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038) 267#define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040) 268#define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048) 269 270#define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */ 271#define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */ 272#define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */ 273#define KL_I2C_REG MD_UREG0_0 /* I2C reg */ 274 275#ifndef __ASSEMBLY__ 276/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc 277 * CACHE_ERR_SP_PTR could either contain an address to the stack, or 278 * the stack could start at CACHE_ERR_SP_PTR 279 */ 280#if defined(HUB_ERR_STS_WAR) 281#define CACHE_ERR_EFRAME 0x480 282#else /* HUB_ERR_STS_WAR */ 283#define CACHE_ERR_EFRAME 0x400 284#endif /* HUB_ERR_STS_WAR */ 285 286#define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE) 287#define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */ 288#define CACHE_ERR_IBASE_PTR (0x1000 - 40) 289#define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) 290#define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) 291 292#endif /* !__ASSEMBLY__ */ 293 294#define _ARCSPROM 295 296#ifdef _STANDALONE 297 298/* 299 * The PROM needs to pass the device base address and the 300 * device pci cfg space address to the device drivers during 301 * install. The COMPONENT->Key field is used for this purpose. 302 * Macros needed by SN0 device drivers to convert the 303 * COMPONENT->Key field to the respective base address. 304 * Key field looks as follows: 305 * 306 * +----------------------------------------------------+ 307 * |devnasid | widget |pciid |hubwidid|hstnasid | adap | 308 * | 2 | 1 | 1 | 1 | 2 | 1 | 309 * +----------------------------------------------------+ 310 * | | | | | | | 311 * 64 48 40 32 24 8 0 312 * 313 * These are used by standalone drivers till the io infrastructure 314 * is in place. 315 */ 316 317#ifndef __ASSEMBLY__ 318 319#define uchar unsigned char 320 321#define KEY_DEVNASID_SHFT 48 322#define KEY_WIDID_SHFT 40 323#define KEY_PCIID_SHFT 32 324#define KEY_HUBWID_SHFT 24 325#define KEY_HSTNASID_SHFT 8 326 327#define MK_SN0_KEY(nasid, widid, pciid) \ 328 ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\ 329 ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\ 330 ((__psunsigned_t)pciid) << KEY_PCIID_SHFT) 331 332#define ADD_HUBWID_KEY(key,hubwid)\ 333 (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT)) 334 335#define ADD_HSTNASID_KEY(key,hstnasid)\ 336 (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT)) 337 338#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT)) 339#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT)) 340#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT)) 341#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT)) 342#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT)) 343 344#define PCI_64_TARGID_SHFT 60 345 346#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ 347 GET_WIDID_FROM_KEY(key))\ 348 | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key))) 349 350#define GET_PCICFGBASE_FROM_KEY(key) \ 351 (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ 352 GET_WIDID_FROM_KEY(key))\ 353 | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key))) 354 355#define GET_WIDBASE_FROM_KEY(key) \ 356 (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ 357 GET_WIDID_FROM_KEY(key))) 358 359#define PUT_INSTALL_STATUS(c,s) c->Revision = s 360#define GET_INSTALL_STATUS(c) c->Revision 361 362#endif /* !__ASSEMBLY__ */ 363 364#endif /* _STANDALONE */ 365 366#if defined(HUB_ERR_STS_WAR) 367 368#define ERR_STS_WAR_REGISTER IIO_IIBUSERR 369#define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) 370#define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR) 371 /* Used to match addr in error reg. */ 372#define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100) 373 374#endif /* HUB_ERR_STS_WAR */ 375 376#endif /* _ASM_SN_SN0_ADDRS_H */ 377