1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * sgimc.h: Definitions for memory controller hardware found on 7 * SGI IP20, IP22, IP26, and IP28 machines. 8 * 9 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) 10 * Copyright (C) 1999 Ralf Baechle 11 * Copyright (C) 1999 Silicon Graphics, Inc. 12 */ 13#ifndef _ASM_SGI_SGIMC_H 14#define _ASM_SGI_SGIMC_H 15 16struct sgimc_misc_ctrl { 17 u32 _unused1; 18 volatile u32 cpuctrl0; /* CPU control register 0, readwrite */ 19#define SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */ 20#define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */ 21#define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */ 22#define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */ 23#define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */ 24#define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */ 25#define SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */ 26#define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */ 27#define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */ 28#define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */ 29#define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */ 30#define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */ 31#define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */ 32#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */ 33#define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */ 34#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */ 35#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */ 36#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */ 37#define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */ 38 39 u32 _unused2; 40 volatile u32 cpuctrl1; /* CPU control register 1, readwrite */ 41#define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */ 42#define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */ 43#define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */ 44#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */ 45#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */ 46#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ 47#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ 48 49 u32 _unused3; 50 volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */ 51 52 u32 _unused4; 53 volatile u32 systemid; /* MC system ID register, readonly */ 54#define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */ 55#define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */ 56 57 u32 _unused5[3]; 58 volatile u32 divider; /* Divider reg for RPSS */ 59 60 u32 _unused6; 61 volatile unsigned char eeprom; /* EEPROM byte reg for r4k */ 62#define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ 63#define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ 64#define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */ 65#define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */ 66#define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */ 67 68 unsigned char _unused7[3]; 69 u32 _unused8[3]; 70 volatile unsigned short rcntpre; /* Preload refresh counter */ 71 72 unsigned short _unused9; 73 u32 _unused9a; 74 volatile unsigned short rcounter; /* Readonly refresh counter */ 75 76 unsigned short _unused10; 77 u32 _unused11[13]; 78 volatile u32 gioparm; /* Parameter word for GIO64 */ 79#define SGIMC_GIOPARM_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */ 80#define SGIMC_GIOPARM_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */ 81#define SGIMC_GIOPARM_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */ 82#define SGIMC_GIOPARM_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */ 83#define SGIMC_GIOPARM_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */ 84#define SGIMC_GIOPARM_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */ 85#define SGIMC_GIOPARM_RTIMEGFX 0x00000040 /* GFX device has realtime attr */ 86#define SGIMC_GIOPARM_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */ 87#define SGIMC_GIOPARM_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */ 88#define SGIMC_GIOPARM_MASTEREISA 0x00000200 /* EISA bus can act as bus master */ 89#define SGIMC_GIOPARM_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */ 90#define SGIMC_GIOPARM_MASTERGFX 0x00000800 /* GFX can act as a bus master */ 91#define SGIMC_GIOPARM_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */ 92#define SGIMC_GIOPARM_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */ 93#define SGIMC_GIOPARM_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */ 94#define SGIMC_GIOPARM_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */ 95 96 u32 _unused13; 97 volatile unsigned short cputp; /* CPU bus arb time period */ 98 99 unsigned short _unused14; 100 u32 _unused15[3]; 101 volatile unsigned short lbursttp; /* Time period for long bursts */ 102 103 unsigned short _unused16; 104 u32 _unused17[9]; 105 volatile u32 mconfig0; /* Memory config register zero */ 106 u32 _unused18; 107 volatile u32 mconfig1; /* Memory config register one */ 108 109 /* These defines apply to both mconfig registers above. */ 110#define SGIMC_MCONFIG_FOURMB 0x00000000 /* Physical ram = 4megs */ 111#define SGIMC_MCONFIG_EIGHTMB 0x00000100 /* Physical ram = 8megs */ 112#define SGIMC_MCONFIG_SXTEENMB 0x00000300 /* Physical ram = 16megs */ 113#define SGIMC_MCONFIG_TTWOMB 0x00000700 /* Physical ram = 32megs */ 114#define SGIMC_MCONFIG_SFOURMB 0x00000f00 /* Physical ram = 64megs */ 115#define SGIMC_MCONFIG_OTEIGHTMB 0x00001f00 /* Physical ram = 128megs */ 116#define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */ 117 118 u32 _unused19; 119 volatile u32 cmacc; /* Mem access config for CPU */ 120 u32 _unused20; 121 volatile u32 gmacc; /* Mem access config for GIO */ 122 123 /* This define applies to both cmacc and gmacc registers above. */ 124#define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */ 125 126 /* Error address/status regs from GIO and CPU perspectives. */ 127 u32 _unused21; 128 volatile u32 cerr; /* Error address reg for CPU */ 129 u32 _unused22; 130 volatile u32 cstat; /* Status reg for CPU */ 131#define SGIMC_CSTAT_RD 0x00000100 /* read parity error */ 132#define SGIMC_CSTAT_PAR 0x00000200 /* CPU parity error */ 133#define SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */ 134#define SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */ 135#define SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */ 136#define SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */ 137#define SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */ 138#define SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR) 139 140 u32 _unused23; 141 volatile u32 gerr; /* Error address reg for GIO */ 142 u32 _unused24; 143 volatile u32 gstat; /* Status reg for GIO */ 144#define SGIMC_GSTAT_RD 0x00000100 /* read parity error */ 145#define SGIMC_GSTAT_WR 0x00000200 /* write parity error */ 146#define SGIMC_GSTAT_TIME 0x00000400 /* GIO bus timed out */ 147#define SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */ 148#define SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */ 149#define SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */ 150#define SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */ 151#define SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */ 152 153 /* Special hard bus locking registers. */ 154 u32 _unused25; 155 volatile unsigned char syssembit; /* Uni-bit system semaphore */ 156 unsigned char _unused26[3]; 157 u32 _unused27; 158 volatile unsigned char mlock; /* Global GIO memory access lock */ 159 unsigned char _unused28[3]; 160 u32 _unused29; 161 volatile unsigned char elock; /* Locks EISA from GIO accesses */ 162 163 /* GIO dma control registers. */ 164 unsigned char _unused30[3]; 165 u32 _unused31[14]; 166 volatile u32 gio_dma_trans;/* DMA mask to translation GIO addrs */ 167 u32 _unused32; 168 volatile u32 gio_dma_sbits;/* DMA GIO addr substitution bits */ 169 u32 _unused33; 170 volatile u32 dma_intr_cause; /* DMA IRQ cause indicator bits */ 171 u32 _unused34; 172 volatile u32 dma_ctrl; /* Main DMA control reg */ 173 174 /* DMA TLB entry 0 */ 175 u32 _unused35; 176 volatile u32 dtlb_hi0; 177 u32 _unused36; 178 volatile u32 dtlb_lo0; 179 180 /* DMA TLB entry 1 */ 181 u32 _unused37; 182 volatile u32 dtlb_hi1; 183 u32 _unused38; 184 volatile u32 dtlb_lo1; 185 186 /* DMA TLB entry 2 */ 187 u32 _unused39; 188 volatile u32 dtlb_hi2; 189 u32 _unused40; 190 volatile u32 dtlb_lo2; 191 192 /* DMA TLB entry 3 */ 193 u32 _unused41; 194 volatile u32 dtlb_hi3; 195 u32 _unused42; 196 volatile u32 dtlb_lo3; 197}; 198 199/* MC misc control registers live at physical 0x1fa00000. */ 200extern struct sgimc_misc_ctrl *mcmisc_regs; 201extern u32 *rpsscounter; /* Chirps at 100ns */ 202 203struct sgimc_dma_ctrl { 204 u32 _unused1; 205 volatile u32 maddronly; /* Address DMA goes at */ 206 u32 _unused2; 207 volatile u32 maddrpdeflts; /* Same as above, plus set defaults */ 208 u32 _unused3; 209 volatile u32 dmasz; /* DMA count */ 210 u32 _unused4; 211 volatile u32 ssize; /* DMA stride size */ 212 u32 _unused5; 213 volatile u32 gmaddronly; /* Set GIO DMA but do not start trans */ 214 u32 _unused6; 215 volatile u32 dmaddnpgo; /* Set GIO DMA addr + start transfer */ 216 u32 _unused7; 217 volatile u32 dmamode; /* DMA mode config bit settings */ 218 u32 _unused8; 219 volatile u32 dmaccount; /* Zoom and byte count for DMA */ 220 u32 _unused9; 221 volatile u32 dmastart; /* Pedal to the metal. */ 222 u32 _unused10; 223 volatile u32 dmarunning; /* DMA op is in progress */ 224 u32 _unused11; 225 226 /* Set dma addr, defaults, and kick it */ 227 volatile u32 maddr_defl_go; /* go go go! -lm */ 228}; 229 230/* MC controller dma regs live at physical 0x1fa02000. */ 231extern struct sgimc_dma_ctrl *dmactrlregs; 232 233/* Base location of the two ram banks found in IP2[0268] machines. */ 234#define SGIMC_SEG0_BADDR 0x08000000 235#define SGIMC_SEG1_BADDR 0x20000000 236 237/* Maximum size of the above banks are per machine. */ 238extern u32 sgimc_seg0_size, sgimc_seg1_size; 239#define SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */ 240#define SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */ 241#define SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */ 242 243extern void sgimc_init(void); 244 245#endif /* _ASM_SGI_SGIMC_H */ 246