1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
4 *
5 * ########################################################################
6 *
7 *  This program is free software; you can distribute it and/or modify it
8 *  under the terms of the GNU General Public License (Version 2) as
9 *  published by the Free Software Foundation.
10 *
11 *  This program is distributed in the hope it will be useful, but WITHOUT
12 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14 *  for more details.
15 *
16 *  You should have received a copy of the GNU General Public License along
17 *  with this program; if not, write to the Free Software Foundation, Inc.,
18 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Register definitions for Intel PIIX4 South Bridge Device.
23 *
24 */
25
26#ifndef PIIX4_H
27#define PIIX4_H
28
29/************************************************************************
30 *  IO register offsets
31 ************************************************************************/
32#define PIIX4_ICTLR1_ICW1	0x20
33#define PIIX4_ICTLR1_ICW2	0x21
34#define PIIX4_ICTLR1_ICW3	0x21
35#define PIIX4_ICTLR1_ICW4	0x21
36#define PIIX4_ICTLR2_ICW1	0xa0
37#define PIIX4_ICTLR2_ICW2	0xa1
38#define PIIX4_ICTLR2_ICW3	0xa1
39#define PIIX4_ICTLR2_ICW4	0xa1
40#define PIIX4_ICTLR1_OCW1	0x21
41#define PIIX4_ICTLR1_OCW2	0x20
42#define PIIX4_ICTLR1_OCW3	0x20
43#define PIIX4_ICTLR1_OCW4	0x20
44#define PIIX4_ICTLR2_OCW1	0xa1
45#define PIIX4_ICTLR2_OCW2	0xa0
46#define PIIX4_ICTLR2_OCW3	0xa0
47#define PIIX4_ICTLR2_OCW4	0xa0
48
49
50/************************************************************************
51 *  Register encodings.
52 ************************************************************************/
53#define PIIX4_OCW2_NSEOI	(0x1 << 5)
54#define PIIX4_OCW2_SEOI		(0x3 << 5)
55#define PIIX4_OCW2_RNSEOI	(0x5 << 5)
56#define PIIX4_OCW2_RAEOIS	(0x4 << 5)
57#define PIIX4_OCW2_RAEOIC	(0x0 << 5)
58#define PIIX4_OCW2_RSEOI	(0x7 << 5)
59#define PIIX4_OCW2_SP		(0x6 << 5)
60#define PIIX4_OCW2_NOP		(0x2 << 5)
61
62#define PIIX4_OCW2_SEL          (0x0 << 3)
63
64#define PIIX4_OCW2_ILS_0	0
65#define PIIX4_OCW2_ILS_1	1
66#define PIIX4_OCW2_ILS_2	2
67#define PIIX4_OCW2_ILS_3	3
68#define PIIX4_OCW2_ILS_4	4
69#define PIIX4_OCW2_ILS_5	5
70#define PIIX4_OCW2_ILS_6	6
71#define PIIX4_OCW2_ILS_7	7
72#define PIIX4_OCW2_ILS_8	0
73#define PIIX4_OCW2_ILS_9	1
74#define PIIX4_OCW2_ILS_10	2
75#define PIIX4_OCW2_ILS_11	3
76#define PIIX4_OCW2_ILS_12	4
77#define PIIX4_OCW2_ILS_13	5
78#define PIIX4_OCW2_ILS_14	6
79#define PIIX4_OCW2_ILS_15	7
80
81#define PIIX4_OCW3_SEL          (0x1 << 3)
82
83#define PIIX4_OCW3_IRR          0x2
84#define PIIX4_OCW3_ISR          0x3
85
86#endif /* !(PIIX4_H) */
87