1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * MAC constants and macros File: sb1250_mac.h 5 * 6 * This module contains constants and macros for the SB1250's 7 * ethernet controllers. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 * Author: Mitch Lichtenberg (mpl@broadcom.com) 12 * 13 ********************************************************************* 14 * 15 * Copyright 2000,2001,2002,2003 16 * Broadcom Corporation. All rights reserved. 17 * 18 * This program is free software; you can redistribute it and/or 19 * modify it under the terms of the GNU General Public License as 20 * published by the Free Software Foundation; either version 2 of 21 * the License, or (at your option) any later version. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * MA 02111-1307 USA 32 ********************************************************************* */ 33 34 35#ifndef _SB1250_MAC_H 36#define _SB1250_MAC_H 37 38#include "sb1250_defs.h" 39 40/* ********************************************************************* 41 * Ethernet MAC Registers 42 ********************************************************************* */ 43 44/* 45 * MAC Configuration Register (Table 9-13) 46 * Register: MAC_CFG_0 47 * Register: MAC_CFG_1 48 * Register: MAC_CFG_2 49 */ 50 51 52#define M_MAC_RESERVED0 _SB_MAKEMASK1(0) 53#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) 54#define M_MAC_RETRY_EN _SB_MAKEMASK1(2) 55#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) 56#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) 57#define M_MAC_BURST_EN _SB_MAKEMASK1(5) 58 59#define S_MAC_TX_PAUSE _SB_MAKE64(6) 60#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) 61#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) 62 63#define K_MAC_TX_PAUSE_CNT_512 0 64#define K_MAC_TX_PAUSE_CNT_1K 1 65#define K_MAC_TX_PAUSE_CNT_2K 2 66#define K_MAC_TX_PAUSE_CNT_4K 3 67#define K_MAC_TX_PAUSE_CNT_8K 4 68#define K_MAC_TX_PAUSE_CNT_16K 5 69#define K_MAC_TX_PAUSE_CNT_32K 6 70#define K_MAC_TX_PAUSE_CNT_64K 7 71 72#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) 73#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) 74#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) 75#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) 76#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) 77#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) 78#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 79#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 80 81#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) 82 83#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 84#define M_MAC_RESERVED2 _SB_MAKEMASK1(18) 85#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) 86#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) 87#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) 88#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) 89#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) 90#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 91#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 92 93#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) 94 95#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 96#define M_MAC_HDX_EN _SB_MAKEMASK1(33) 97 98#define S_MAC_SPEED_SEL _SB_MAKE64(34) 99#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) 100#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) 101#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) 102 103#define K_MAC_SPEED_SEL_10MBPS 0 104#define K_MAC_SPEED_SEL_100MBPS 1 105#define K_MAC_SPEED_SEL_1000MBPS 2 106#define K_MAC_SPEED_SEL_RESERVED 3 107 108#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) 109#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) 110#define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) 111#define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) 112 113#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) 114#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) 115#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) 116#define M_MAC_SS_EN _SB_MAKEMASK1(39) 117 118#define S_MAC_BYPASS_CFG _SB_MAKE64(40) 119#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) 120#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) 121#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) 122 123#define K_MAC_BYPASS_GMII 0 124#define K_MAC_BYPASS_ENCODED 1 125#define K_MAC_BYPASS_SOP 2 126#define K_MAC_BYPASS_EOP 3 127 128#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 129#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 130 131#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 132#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 133#endif /* 1250 PASS2 || 112x PASS1 */ 134 135#if SIBYTE_HDR_FEATURE(112x, PASS1) 136#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 137#endif /* 112x PASS1 */ 138 139#define S_MAC_BYPASS_IFG _SB_MAKE64(46) 140#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) 141#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) 142#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) 143 144#define K_MAC_FC_CMD_DISABLED 0 145#define K_MAC_FC_CMD_ENABLED 1 146#define K_MAC_FC_CMD_ENAB_FALSECARR 2 147 148#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) 149#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) 150#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) 151 152#define M_MAC_FC_SEL _SB_MAKEMASK1(54) 153 154#define S_MAC_FC_CMD _SB_MAKE64(55) 155#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) 156#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) 157#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) 158 159#define S_MAC_RX_CH_SEL _SB_MAKE64(57) 160#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) 161#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) 162#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) 163 164 165/* 166 * MAC Enable Registers 167 * Register: MAC_ENABLE_0 168 * Register: MAC_ENABLE_1 169 * Register: MAC_ENABLE_2 170 */ 171 172#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) 173#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) 174#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) 175#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) 176 177#define M_MAC_PORT_RESET _SB_MAKEMASK1(8) 178 179#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) 180#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) 181#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) 182#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) 183 184/* 185 * MAC DMA Control Register 186 * Register: MAC_TXD_CTL_0 187 * Register: MAC_TXD_CTL_1 188 * Register: MAC_TXD_CTL_2 189 */ 190 191#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 192#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) 193#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) 194#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) 195 196#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 197#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) 198#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) 199#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) 200 201/* 202 * MAC Fifo Threshhold registers (Table 9-14) 203 * Register: MAC_THRSH_CFG_0 204 * Register: MAC_THRSH_CFG_1 205 * Register: MAC_THRSH_CFG_2 206 */ 207 208#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 209#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 210/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ 211#endif /* up to 1250 PASS1 */ 212#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 213#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) 214#endif /* 1250 PASS2 || 112x PASS1 */ 215#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 216#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 217 218#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 219#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 220/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ 221#endif /* up to 1250 PASS1 */ 222#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 223#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) 224#endif /* 1250 PASS2 || 112x PASS1 */ 225#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 226#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 227 228#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 229#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) 230#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) 231#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) 232 233#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 234#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) 235#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) 236#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) 237 238#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 239#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) 240#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) 241#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) 242 243#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 244#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) 245#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 246#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 247 248#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 249#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 250#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) 251#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) 252#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) 253#endif /* 1250 PASS2 || 112x PASS1 */ 254 255/* 256 * MAC Frame Configuration Registers (Table 9-15) 257 * Register: MAC_FRAME_CFG_0 258 * Register: MAC_FRAME_CFG_1 259 * Register: MAC_FRAME_CFG_2 260 */ 261 262/* XXXCGD: ??? Unused in pass2? */ 263#define S_MAC_IFG_RX _SB_MAKE64(0) 264#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) 265#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) 266#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) 267 268#if SIBYTE_HDR_FEATURE(112x, PASS1) 269#define S_MAC_PRE_LEN _SB_MAKE64(0) 270#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) 271#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) 272#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) 273#endif /* 112x PASS1 */ 274 275#define S_MAC_IFG_TX _SB_MAKE64(6) 276#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) 277#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) 278#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) 279 280#define S_MAC_IFG_THRSH _SB_MAKE64(12) 281#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) 282#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) 283#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) 284 285#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 286#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) 287#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) 288#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) 289 290#define S_MAC_LFSR_SEED _SB_MAKE64(22) 291#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) 292#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) 293#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) 294 295#define S_MAC_SLOT_SIZE _SB_MAKE64(30) 296#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) 297#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) 298#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) 299 300#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 301#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) 302#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) 303#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) 304 305#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 306#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) 307#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) 308#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) 309 310/* 311 * These constants are used to configure the fields within the Frame 312 * Configuration Register. 313 */ 314 315#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ 316#define K_MAC_IFG_RX_100 _SB_MAKE64(0) 317#define K_MAC_IFG_RX_1000 _SB_MAKE64(0) 318 319#define K_MAC_IFG_TX_10 _SB_MAKE64(20) 320#define K_MAC_IFG_TX_100 _SB_MAKE64(20) 321#define K_MAC_IFG_TX_1000 _SB_MAKE64(8) 322 323#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) 324#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) 325#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) 326 327#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) 328#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) 329#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) 330 331#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) 332#define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) 333#define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) 334 335#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) 336#define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) 337#define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) 338 339#define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) 340#define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) 341#define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) 342 343#define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) 344#define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) 345#define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) 346 347#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) 348#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) 349#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) 350#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) 351 352#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) 353#define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) 354#define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) 355#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) 356 357/* 358 * MAC VLAN Tag Registers (Table 9-16) 359 * Register: MAC_VLANTAG_0 360 * Register: MAC_VLANTAG_1 361 * Register: MAC_VLANTAG_2 362 */ 363 364#define S_MAC_VLAN_TAG _SB_MAKE64(0) 365#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) 366#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) 367#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) 368 369#if SIBYTE_HDR_FEATURE(112x, PASS1) 370#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) 371#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) 372#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) 373#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) 374 375#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) 376#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) 377#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) 378#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) 379 380#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) 381#endif /* 112x PASS1 */ 382 383/* 384 * MAC Status Registers (Table 9-17) 385 * Also used for the MAC Interrupt Mask Register (Table 9-18) 386 * Register: MAC_STATUS_0 387 * Register: MAC_STATUS_1 388 * Register: MAC_STATUS_2 389 * Register: MAC_INT_MASK_0 390 * Register: MAC_INT_MASK_1 391 * Register: MAC_INT_MASK_2 392 */ 393 394/* 395 * Use these constants to shift the appropriate channel 396 * into the CH0 position so the same tests can be used 397 * on each channel. 398 */ 399 400#define S_MAC_RX_CH0 _SB_MAKE64(0) 401#define S_MAC_RX_CH1 _SB_MAKE64(8) 402#define S_MAC_TX_CH0 _SB_MAKE64(16) 403#define S_MAC_TX_CH1 _SB_MAKE64(24) 404 405#define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ 406#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ 407 408/* 409 * These are the same as RX channel 0. The idea here 410 * is that you'll use one of the "S_" things above 411 * and pass just the six bits to a DMA-channel-specific ISR 412 */ 413#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) 414#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 415#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 416#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 417#define M_MAC_INT_HWM _SB_MAKEMASK1(3) 418#define M_MAC_INT_LWM _SB_MAKEMASK1(4) 419#define M_MAC_INT_DSCR _SB_MAKEMASK1(5) 420#define M_MAC_INT_ERR _SB_MAKEMASK1(6) 421#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ 422#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ 423 424/* 425 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see 426 * also DMA_TX/DMA_RX in sb_regs.h). 427 */ 428#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) 429 430#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) 431#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 432#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 433#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 434#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 435#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 436#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 437#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 438#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 439#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 440#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) 441 442 443#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 444#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) 445#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) 446#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) 447#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 448#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 449#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 450#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 451#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ 452#endif /* 1250 PASS2 || 112x PASS1 */ 453 454#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 455#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 456#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) 457#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) 458 459#if SIBYTE_HDR_FEATURE(112x, PASS1) 460#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 461#endif /* 112x PASS1 */ 462 463/* 464 * MAC Fifo Pointer Registers (Table 9-19) [Debug register] 465 * Register: MAC_FIFO_PTRS_0 466 * Register: MAC_FIFO_PTRS_1 467 * Register: MAC_FIFO_PTRS_2 468 */ 469 470#define S_MAC_TX_WRPTR _SB_MAKE64(0) 471#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) 472#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) 473#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) 474 475#define S_MAC_TX_RDPTR _SB_MAKE64(8) 476#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) 477#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) 478#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) 479 480#define S_MAC_RX_WRPTR _SB_MAKE64(16) 481#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) 482#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) 483#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) 484 485#define S_MAC_RX_RDPTR _SB_MAKE64(24) 486#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) 487#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) 488#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) 489 490/* 491 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 492 * Register: MAC_EOPCNT_0 493 * Register: MAC_EOPCNT_1 494 * Register: MAC_EOPCNT_2 495 */ 496 497#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 498#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) 499#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) 500#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) 501 502#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 503#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) 504#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) 505#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) 506 507/* 508 * MAC Recieve Address Filter Exact Match Registers (Table 9-21) 509 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 510 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 511 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 512 */ 513 514/* No bitfields */ 515 516/* 517 * MAC Receive Address Filter Mask Registers 518 * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 519 * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 520 * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 521 */ 522 523/* No bitfields */ 524 525/* 526 * MAC Recieve Address Filter Hash Match Registers (Table 9-22) 527 * Registers: MAC_HASH0_0 through MAC_HASH7_0 528 * Registers: MAC_HASH0_1 through MAC_HASH7_1 529 * Registers: MAC_HASH0_2 through MAC_HASH7_2 530 */ 531 532/* No bitfields */ 533 534/* 535 * MAC Transmit Source Address Registers (Table 9-23) 536 * Register: MAC_ETHERNET_ADDR_0 537 * Register: MAC_ETHERNET_ADDR_1 538 * Register: MAC_ETHERNET_ADDR_2 539 */ 540 541/* No bitfields */ 542 543/* 544 * MAC Packet Type Configuration Register 545 * Register: MAC_TYPE_CFG_0 546 * Register: MAC_TYPE_CFG_1 547 * Register: MAC_TYPE_CFG_2 548 */ 549 550#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 551 552#define S_TYPECFG_TYPE0 _SB_MAKE64(0) 553#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) 554#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) 555#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) 556 557#define S_TYPECFG_TYPE1 _SB_MAKE64(0) 558#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) 559#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) 560#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) 561 562#define S_TYPECFG_TYPE2 _SB_MAKE64(0) 563#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) 564#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) 565#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) 566 567#define S_TYPECFG_TYPE3 _SB_MAKE64(0) 568#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) 569#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) 570#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) 571 572/* 573 * MAC Receive Address Filter Control Registers (Table 9-24) 574 * Register: MAC_ADFILTER_CFG_0 575 * Register: MAC_ADFILTER_CFG_1 576 * Register: MAC_ADFILTER_CFG_2 577 */ 578 579#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) 580#define M_MAC_UCAST_EN _SB_MAKEMASK1(1) 581#define M_MAC_UCAST_INV _SB_MAKEMASK1(2) 582#define M_MAC_MCAST_EN _SB_MAKEMASK1(3) 583#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 584#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 585#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 586#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 587#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) 588#endif /* 1250 PASS2 || 112x PASS1 */ 589 590#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 591#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 592#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) 593#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) 594 595#if SIBYTE_HDR_FEATURE(112x, PASS1) 596#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 597#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) 598#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) 599#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) 600 601#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) 602#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) 603#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) 604#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) 605 606#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) 607#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) 608 609#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) 610#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) 611#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) 612#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) 613#endif /* 112x PASS1 */ 614 615/* 616 * MAC Receive Channel Select Registers (Table 9-25) 617 */ 618 619/* no bitfields */ 620 621/* 622 * MAC MII Management Interface Registers (Table 9-26) 623 * Register: MAC_MDIO_0 624 * Register: MAC_MDIO_1 625 * Register: MAC_MDIO_2 626 */ 627 628#define S_MAC_MDC 0 629#define S_MAC_MDIO_DIR 1 630#define S_MAC_MDIO_OUT 2 631#define S_MAC_GENC 3 632#define S_MAC_MDIO_IN 4 633 634#define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) 635#define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) 636#define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) 637#define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) 638#define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) 639#define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) 640 641#endif 642