1#ifndef IRQ_HANDLER_ 2#define IRQ_HANDLER_ 3 4#define INT_CAUSE_MAIN 0 5#define INT_CAUSE_HIGH 1 6 7#define MAX_CAUSE_REGS 4 8#define MAX_CAUSE_REG_WIDTH 32 9 10void hook_irq_handler (int int_cause , int bit_num , void *isr_ptr); 11int disable_galileo_irq (int int_cause , int bit_num); 12int enable_galileo_irq (int int_cause , int bit_num); 13 14extern struct tq_struct irq_handlers[MAX_CAUSE_REGS][MAX_CAUSE_REG_WIDTH]; 15 16/* 17 PCI interrupts will come in on either the INTA or 18 INTD interrups lines, which are mapped to the #2 and 19 #5 interrupt pins of the MIPS. On our boards, they 20 all either come in on IntD or they all come in on 21 IntA, they aren't mixed. There can be numerous PCI 22 interrupts, so we keep a list of the "requested" 23 interrupt numbers and go through the list whenever 24 we get an IntA/D. 25 26 All PCI interrupts have numbers >= 20 by arbitrary convention. Any 27 interrupt < 8 is an interrupt that is maskable on the 28 MIPS. 29*/ 30 31#define TIMER 4 32#define INTA 2 33#define INTD 5 34 35 36#endif /* IRQ_HANDLER_ */ 37