1#ifndef __ASM_MSR_H 2#define __ASM_MSR_H 3 4/* 5 * Access to machine-specific registers (available on 586 and better only) 6 * Note: the rd* operations modify the parameters directly (without using 7 * pointer indirection), this allows gcc to optimize better 8 */ 9 10#define rdmsr(msr,val1,val2) \ 11 __asm__ __volatile__("rdmsr" \ 12 : "=a" (val1), "=d" (val2) \ 13 : "c" (msr)) 14 15#define wrmsr(msr,val1,val2) \ 16 __asm__ __volatile__("wrmsr" \ 17 : /* no outputs */ \ 18 : "c" (msr), "a" (val1), "d" (val2)) 19 20#define rdtsc(low,high) \ 21 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high)) 22 23#define rdtscl(low) \ 24 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx") 25 26#define rdtscll(val) \ 27 __asm__ __volatile__("rdtsc" : "=A" (val)) 28 29#define write_tsc(val1,val2) wrmsr(0x10, val1, val2) 30 31#define rdpmc(counter,low,high) \ 32 __asm__ __volatile__("rdpmc" \ 33 : "=a" (low), "=d" (high) \ 34 : "c" (counter)) 35 36/* symbolic names for some interesting MSRs */ 37/* Intel defined MSRs. */ 38#define MSR_IA32_P5_MC_ADDR 0 39#define MSR_IA32_P5_MC_TYPE 1 40#define MSR_IA32_PLATFORM_ID 0x17 41#define MSR_IA32_EBL_CR_POWERON 0x2a 42 43#define MSR_IA32_APICBASE 0x1b 44#define MSR_IA32_APICBASE_BSP (1<<8) 45#define MSR_IA32_APICBASE_ENABLE (1<<11) 46#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 47 48#define MSR_IA32_UCODE_WRITE 0x79 49#define MSR_IA32_UCODE_REV 0x8b 50 51#define MSR_IA32_BBL_CR_CTL 0x119 52 53#define MSR_IA32_MCG_CAP 0x179 54#define MSR_IA32_MCG_STATUS 0x17a 55#define MSR_IA32_MCG_CTL 0x17b 56 57#define MSR_IA32_THERM_CONTROL 0x19a 58#define MSR_IA32_THERM_INTERRUPT 0x19b 59#define MSR_IA32_THERM_STATUS 0x19c 60#define MSR_IA32_MISC_ENABLE 0x1a0 61 62#define MSR_IA32_DEBUGCTLMSR 0x1d9 63#define MSR_IA32_LASTBRANCHFROMIP 0x1db 64#define MSR_IA32_LASTBRANCHTOIP 0x1dc 65#define MSR_IA32_LASTINTFROMIP 0x1dd 66#define MSR_IA32_LASTINTTOIP 0x1de 67 68#define MSR_IA32_MC0_CTL 0x400 69#define MSR_IA32_MC0_STATUS 0x401 70#define MSR_IA32_MC0_ADDR 0x402 71#define MSR_IA32_MC0_MISC 0x403 72 73#define MSR_P6_PERFCTR0 0xc1 74#define MSR_P6_PERFCTR1 0xc2 75#define MSR_P6_EVNTSEL0 0x186 76#define MSR_P6_EVNTSEL1 0x187 77 78/* AMD Defined MSRs */ 79#define MSR_K6_EFER 0xC0000080 80#define MSR_K6_STAR 0xC0000081 81#define MSR_K6_WHCR 0xC0000082 82#define MSR_K6_UWCCR 0xC0000085 83#define MSR_K6_EPMR 0xC0000086 84#define MSR_K6_PSOR 0xC0000087 85#define MSR_K6_PFIR 0xC0000088 86 87#define MSR_K7_EVNTSEL0 0xC0010000 88#define MSR_K7_PERFCTR0 0xC0010004 89#define MSR_K7_HWCR 0xC0010015 90#define MSR_K7_FID_VID_CTL 0xC0010041 91#define MSR_K7_VID_STATUS 0xC0010042 92 93/* Centaur-Hauls/IDT defined MSRs. */ 94#define MSR_IDT_FCR1 0x107 95#define MSR_IDT_FCR2 0x108 96#define MSR_IDT_FCR3 0x109 97#define MSR_IDT_FCR4 0x10a 98 99#define MSR_IDT_MCR0 0x110 100#define MSR_IDT_MCR1 0x111 101#define MSR_IDT_MCR2 0x112 102#define MSR_IDT_MCR3 0x113 103#define MSR_IDT_MCR4 0x114 104#define MSR_IDT_MCR5 0x115 105#define MSR_IDT_MCR6 0x116 106#define MSR_IDT_MCR7 0x117 107#define MSR_IDT_MCR_CTRL 0x120 108 109/* VIA Cyrix defined MSRs*/ 110#define MSR_VIA_FCR 0x1107 111#define MSR_VIA_LONGHAUL 0x110a 112#define MSR_VIA_BCR2 0x1147 113 114/* Transmeta defined MSRs */ 115#define MSR_TMTA_LONGRUN_CTRL 0x80868010 116#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 117 118#endif /* __ASM_MSR_H */ 119