1/* CRIS pgtable.h - macros and functions to manipulate page tables 2 * 3 * HISTORY: 4 * 5 * $Log: pgtable.h,v $ 6 * Revision 1.1.1.1 2008/10/15 03:27:16 james26_jang 7 * Initial. 8 * 9 * Revision 1.1.1.1 2008/07/21 09:15:48 james26_jang 10 * New UI, New QoS, New wireless driver(4.151.10.29), ipmonitor. 11 * 12 * Revision 1.1.1.1 2008/07/02 14:40:12 james26_jang 13 * 4.100.10.29, New QoS and New UI. 14 * 15 * Revision 1.1.1.1 2007/02/15 12:12:00 jiahao 16 * initial update 17 * 18 * Revision 1.1.1.1 2007/01/25 12:52:04 jiahao_jhou 19 * 20 * 21 * Revision 1.1.1.1 2003/02/03 22:38:06 mhuang 22 * LINUX_2_4 branch snapshot from linux-mips.org CVS 23 * 24 * Revision 1.15 2002/04/23 15:37:52 bjornw 25 * Removed page_address and added flush_icache_user_range 26 * 27 * Revision 1.14 2001/12/10 03:08:50 bjornw 28 * Added pgtable_cache_init dummy 29 * 30 * Revision 1.13 2001/11/12 18:05:38 pkj 31 * Added declaration of paging_init(). 32 * 33 * Revision 1.12 2001/08/11 00:28:00 bjornw 34 * PAGE_CHG_MASK and PAGE_NONE had somewhat untraditional values 35 * 36 * Revision 1.11 2001/04/04 14:38:36 bjornw 37 * Removed bad_pagetable handling and the _kernel functions 38 * 39 * Revision 1.10 2001/03/23 07:46:42 starvik 40 * Corrected according to review remarks 41 * 42 * Revision 1.9 2000/11/22 14:57:53 bjornw 43 * * extern inline -> static inline 44 * * include asm-generic/pgtable.h 45 * 46 * Revision 1.8 2000/11/21 13:56:16 bjornw 47 * Use CONFIG_CRIS_LOW_MAP for the low VM map instead of explicit CPU type 48 * 49 * Revision 1.7 2000/10/06 15:05:32 bjornw 50 * VMALLOC area changed in memory mapping change 51 * 52 * Revision 1.6 2000/10/04 16:59:14 bjornw 53 * Changed comments 54 * 55 * Revision 1.5 2000/09/13 14:39:53 bjornw 56 * New macros 57 * 58 * Revision 1.4 2000/08/17 15:38:48 bjornw 59 * 2.4.0-test6 modifications: 60 * * flush_dcache_page added 61 * * MAP_NR removed 62 * * virt_to_page added 63 * 64 * Plus some comments and type-clarifications. 65 * 66 * Revision 1.3 2000/08/15 16:33:35 bjornw 67 * pmd_bad should recognize both kernel and user page-tables 68 * 69 * Revision 1.2 2000/07/10 17:06:01 bjornw 70 * Fixed warnings 71 * 72 * Revision 1.1.1.1 2000/07/10 16:32:31 bjornw 73 * CRIS architecture, working draft 74 * 75 * 76 * Revision 1.11 2000/05/29 14:55:56 bjornw 77 * Small tweaks of pte_mk routines 78 * 79 * Revision 1.10 2000/01/27 01:49:06 bjornw 80 * * Ooops. The physical frame number in a PTE entry needs to point to the 81 * DRAM directly, not to what the kernel thinks is DRAM (due to KSEG mapping). 82 * Hence we need to strip bit 31 so 0xcXXXXXXX -> 0x4XXXXXXX. 83 * 84 * Revision 1.9 2000/01/26 16:25:50 bjornw 85 * Fixed PAGE_KERNEL bits 86 * 87 * Revision 1.8 2000/01/23 22:53:22 bjornw 88 * Correct flush_tlb_* macros and externs 89 * 90 * Revision 1.7 2000/01/18 16:22:55 bjornw 91 * Use PAGE_MASK instead of PFN_MASK. 92 * 93 * Revision 1.6 2000/01/17 02:42:53 bjornw 94 * Added the pmd_set macro. 95 * 96 * Revision 1.5 2000/01/16 19:53:42 bjornw 97 * Removed VMALLOC_OFFSET. Changed definitions of swapper_pg_dir and zero_page. 98 * 99 * Revision 1.4 2000/01/14 16:38:20 bjornw 100 * PAGE_DIRTY -> PAGE_SILENT_WRITE, removed PAGE_COW from PAGE_COPY. 101 * 102 * Revision 1.3 1999/12/04 20:12:21 bjornw 103 * * PTE bits have moved to asm/mmu.h 104 * * Fixed definitions of the higher level page protection bits 105 * * Added the pte_* functions, including dirty/accessed SW simulation 106 * (these are exactly the same as for the MIPS port) 107 * 108 * Revision 1.2 1999/12/04 00:41:54 bjornw 109 * * Fixed page table offsets, sizes and shifts 110 * * Removed reference to i386 SMP stuff 111 * * Added stray comments about Linux/CRIS mm design 112 * * Include asm/mmu.h which will contain MMU details 113 * 114 * Revision 1.1 1999/12/03 15:04:02 bjornw 115 * Copied from include/asm-etrax100. For the new CRIS architecture. 116 */ 117 118#ifndef _CRIS_PGTABLE_H 119#define _CRIS_PGTABLE_H 120 121#include <linux/config.h> 122#include <asm/mmu.h> 123 124/* 125 * The Linux memory management assumes a three-level page table setup. On 126 * CRIS, we use that, but "fold" the mid level into the top-level page 127 * table. Since the MMU TLB is software loaded through an interrupt, it 128 * supports any page table structure, so we could have used a three-level 129 * setup, but for the amounts of memory we normally use, a two-level is 130 * probably more efficient. 131 * 132 * This file contains the functions and defines necessary to modify and use 133 * the CRIS page table tree. 134 */ 135 136extern void paging_init(void); 137 138/* The cache doesn't need to be flushed when TLB entries change because 139 * the cache is mapped to physical memory, not virtual memory 140 */ 141#define flush_cache_all() do { } while (0) 142#define flush_cache_mm(mm) do { } while (0) 143#define flush_cache_range(mm, start, end) do { } while (0) 144#define flush_cache_page(vma, vmaddr) do { } while (0) 145#define flush_page_to_ram(page) do { } while (0) 146#define flush_dcache_page(page) do { } while (0) 147#define flush_icache_range(start, end) do { } while (0) 148#define flush_icache_page(vma,pg) do { } while (0) 149#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) 150 151/* 152 * TLB flushing (implemented in arch/cris/mm/tlb.c): 153 * 154 * - flush_tlb() flushes the current mm struct TLBs 155 * - flush_tlb_all() flushes all processes TLBs 156 * - flush_tlb_mm(mm) flushes the specified mm context TLB's 157 * - flush_tlb_page(vma, vmaddr) flushes one page 158 * - flush_tlb_range(mm, start, end) flushes a range of pages 159 * 160 */ 161 162extern void flush_tlb_all(void); 163extern void flush_tlb_mm(struct mm_struct *mm); 164extern void flush_tlb_page(struct vm_area_struct *vma, 165 unsigned long addr); 166extern void flush_tlb_range(struct mm_struct *mm, 167 unsigned long start, 168 unsigned long end); 169 170static inline void flush_tlb_pgtables(struct mm_struct *mm, 171 unsigned long start, unsigned long end) 172{ 173 /* CRIS does not keep any page table caches in TLB */ 174} 175 176 177static inline void flush_tlb(void) 178{ 179 flush_tlb_mm(current->mm); 180} 181 182/* Certain architectures need to do special things when pte's 183 * within a page table are directly modified. Thus, the following 184 * hook is made available. 185 */ 186#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval)) 187/* 188 * (pmds are folded into pgds so this doesn't get actually called, 189 * but the define is needed for a generic inline function.) 190 */ 191#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) 192#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval) 193 194/* PMD_SHIFT determines the size of the area a second-level page table can 195 * map. It is equal to the page size times the number of PTE's that fit in 196 * a PMD page. A PTE is 4-bytes in CRIS. Hence the following number. 197 */ 198 199#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2)) 200#define PMD_SIZE (1UL << PMD_SHIFT) 201#define PMD_MASK (~(PMD_SIZE-1)) 202 203/* PGDIR_SHIFT determines what a third-level page table entry can map. 204 * Since we fold into a two-level structure, this is the same as PMD_SHIFT. 205 */ 206 207#define PGDIR_SHIFT PMD_SHIFT 208#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 209#define PGDIR_MASK (~(PGDIR_SIZE-1)) 210 211/* 212 * entries per page directory level: we use a two-level, so 213 * we don't really have any PMD directory physically. 214 * pointers are 4 bytes so we can use the page size and 215 * divide it by 4 (shift by 2). 216 */ 217#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2)) 218#define PTRS_PER_PMD 1 219#define PTRS_PER_PGD (1UL << (PAGE_SHIFT-2)) 220 221/* calculate how many PGD entries a user-level program can use 222 * the first mappable virtual address is 0 223 * (TASK_SIZE is the maximum virtual address space) 224 */ 225 226#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 227#define FIRST_USER_PGD_NR 0 228 229/* 230 * Kernels own virtual memory area. 231 */ 232 233#ifdef CONFIG_CRIS_LOW_MAP 234#define VMALLOC_START KSEG_7 235#define VMALLOC_VMADDR(x) ((unsigned long)(x)) 236#define VMALLOC_END KSEG_8 237#else 238#define VMALLOC_START KSEG_D 239#define VMALLOC_VMADDR(x) ((unsigned long)(x)) 240#define VMALLOC_END KSEG_E 241#endif 242 243/* Define some higher level generic page attributes. The PTE bits are 244 * defined in asm-cris/mmu.h, and these are just combinations of those. 245 */ 246 247#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) 248#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) 249 250#define _PAGE_TABLE (_PAGE_PRESENT | __READABLE | __WRITEABLE) 251#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED) 252 253#define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED) 254#define PAGE_SHARED __pgprot(_PAGE_PRESENT | __READABLE | _PAGE_WRITE | \ 255 _PAGE_ACCESSED) 256#define PAGE_COPY __pgprot(_PAGE_PRESENT | __READABLE) // | _PAGE_COW 257#define PAGE_READONLY __pgprot(_PAGE_PRESENT | __READABLE) 258#define PAGE_KERNEL __pgprot(_PAGE_GLOBAL | _PAGE_KERNEL | \ 259 _PAGE_PRESENT | __READABLE | __WRITEABLE) 260#define _KERNPG_TABLE (_PAGE_TABLE | _PAGE_KERNEL) 261 262/* 263 * CRIS can't do page protection for execute, and considers read the same. 264 * Also, write permissions imply read permissions. This is the closest we can 265 * get.. 266 */ 267 268#define __P000 PAGE_NONE 269#define __P001 PAGE_READONLY 270#define __P010 PAGE_COPY 271#define __P011 PAGE_COPY 272#define __P100 PAGE_READONLY 273#define __P101 PAGE_READONLY 274#define __P110 PAGE_COPY 275#define __P111 PAGE_COPY 276 277#define __S000 PAGE_NONE 278#define __S001 PAGE_READONLY 279#define __S010 PAGE_SHARED 280#define __S011 PAGE_SHARED 281#define __S100 PAGE_READONLY 282#define __S101 PAGE_READONLY 283#define __S110 PAGE_SHARED 284#define __S111 PAGE_SHARED 285 286/* zero page used for uninitialized stuff */ 287extern unsigned long empty_zero_page; 288#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 289 290/* number of bits that fit into a memory pointer */ 291#define BITS_PER_PTR (8*sizeof(unsigned long)) 292 293/* to align the pointer to a pointer address */ 294#define PTR_MASK (~(sizeof(void*)-1)) 295 296/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */ 297/* 64-bit machines, beware! SRB. */ 298#define SIZEOF_PTR_LOG2 2 299 300/* to find an entry in a page-table */ 301#define PAGE_PTR(address) \ 302((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK) 303 304/* to set the page-dir */ 305#define SET_PAGE_DIR(tsk,pgdir) 306 307#define pte_none(x) (!pte_val(x)) 308#define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 309#define pte_clear(xp) do { pte_val(*(xp)) = 0; } while (0) 310 311#define pmd_none(x) (!pmd_val(x)) 312/* by removing the _PAGE_KERNEL bit from the comparision, the same pmd_bad 313 * works for both _PAGE_TABLE and _KERNPG_TABLE pmd entries. 314 */ 315#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_KERNEL)) != _PAGE_TABLE) 316#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) 317#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) 318 319/* 320 * The "pgd_xxx()" functions here are trivial for a folded two-level 321 * setup: the pgd is never bad, and a pmd always exists (as it's folded 322 * into the pgd entry) 323 */ 324static inline int pgd_none(pgd_t pgd) { return 0; } 325static inline int pgd_bad(pgd_t pgd) { return 0; } 326static inline int pgd_present(pgd_t pgd) { return 1; } 327static inline void pgd_clear(pgd_t * pgdp) { } 328 329/* 330 * The following only work if pte_present() is true. 331 * Undefined behaviour if not.. 332 */ 333 334static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; } 335static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; } 336static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_READ; } 337static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; } 338static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 339 340static inline pte_t pte_wrprotect(pte_t pte) 341{ 342 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); 343 return pte; 344} 345 346static inline pte_t pte_rdprotect(pte_t pte) 347{ 348 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); 349 return pte; 350} 351 352static inline pte_t pte_exprotect(pte_t pte) 353{ 354 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ); 355 return pte; 356} 357 358static inline pte_t pte_mkclean(pte_t pte) 359{ 360 pte_val(pte) &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); 361 return pte; 362} 363 364static inline pte_t pte_mkold(pte_t pte) 365{ 366 pte_val(pte) &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); 367 return pte; 368} 369 370static inline pte_t pte_mkwrite(pte_t pte) 371{ 372 pte_val(pte) |= _PAGE_WRITE; 373 if (pte_val(pte) & _PAGE_MODIFIED) 374 pte_val(pte) |= _PAGE_SILENT_WRITE; 375 return pte; 376} 377 378static inline pte_t pte_mkread(pte_t pte) 379{ 380 pte_val(pte) |= _PAGE_READ; 381 if (pte_val(pte) & _PAGE_ACCESSED) 382 pte_val(pte) |= _PAGE_SILENT_READ; 383 return pte; 384} 385 386static inline pte_t pte_mkexec(pte_t pte) 387{ 388 pte_val(pte) |= _PAGE_READ; 389 if (pte_val(pte) & _PAGE_ACCESSED) 390 pte_val(pte) |= _PAGE_SILENT_READ; 391 return pte; 392} 393 394static inline pte_t pte_mkdirty(pte_t pte) 395{ 396 pte_val(pte) |= _PAGE_MODIFIED; 397 if (pte_val(pte) & _PAGE_WRITE) 398 pte_val(pte) |= _PAGE_SILENT_WRITE; 399 return pte; 400} 401 402static inline pte_t pte_mkyoung(pte_t pte) 403{ 404 pte_val(pte) |= _PAGE_ACCESSED; 405 if (pte_val(pte) & _PAGE_READ) 406 { 407 pte_val(pte) |= _PAGE_SILENT_READ; 408 if ((pte_val(pte) & (_PAGE_WRITE | _PAGE_MODIFIED)) == 409 (_PAGE_WRITE | _PAGE_MODIFIED)) 410 pte_val(pte) |= _PAGE_SILENT_WRITE; 411 } 412 return pte; 413} 414 415/* 416 * Conversion functions: convert a page and protection to a page entry, 417 * and a page entry and page directory to the page they refer to. 418 */ 419 420/* What actually goes as arguments to the various functions is less than 421 * obvious, but a rule of thumb is that struct page's goes as struct page *, 422 * really physical DRAM addresses are unsigned long's, and DRAM "virtual" 423 * addresses (the 0xc0xxxxxx's) goes as void *'s. 424 */ 425 426static inline pte_t __mk_pte(void * page, pgprot_t pgprot) 427{ 428 pte_t pte; 429 /* the PTE needs a physical address */ 430 pte_val(pte) = __pa(page) | pgprot_val(pgprot); 431 return pte; 432} 433 434#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot)) 435 436#define mk_pte_phys(physpage, pgprot) \ 437({ \ 438 pte_t __pte; \ 439 \ 440 pte_val(__pte) = (physpage) + pgprot_val(pgprot); \ 441 __pte; \ 442}) 443 444static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 445{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; } 446 447 448/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval 449 * __pte_page(pte_val) refers to the "virtual" DRAM interval 450 * pte_pagenr refers to the page-number counted starting from the virtual DRAM start 451 */ 452 453static inline unsigned long __pte_page(pte_t pte) 454{ 455 /* the PTE contains a physical address */ 456 return (unsigned long)__va(pte_val(pte) & PAGE_MASK); 457} 458 459#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT) 460 461/* permanent address of a page */ 462 463#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT)) 464#define pte_page(pte) (mem_map+pte_pagenr(pte)) 465 466/* only the pte's themselves need to point to physical DRAM (see above) 467 * the pagetable links are purely handled within the kernel SW and thus 468 * don't need the __pa and __va transformations. 469 */ 470 471static inline unsigned long pmd_page(pmd_t pmd) 472{ return pmd_val(pmd) & PAGE_MASK; } 473 474static inline void pmd_set(pmd_t * pmdp, pte_t * ptep) 475{ pmd_val(*pmdp) = _PAGE_TABLE | (unsigned long) ptep; } 476 477/* to find an entry in a page-table-directory. */ 478#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 479 480/* to find an entry in a page-table-directory */ 481static inline pgd_t * pgd_offset(struct mm_struct * mm, unsigned long address) 482{ 483 return mm->pgd + pgd_index(address); 484} 485 486/* to find an entry in a kernel page-table-directory */ 487#define pgd_offset_k(address) pgd_offset(&init_mm, address) 488 489/* Find an entry in the second-level page table.. */ 490static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) 491{ 492 return (pmd_t *) dir; 493} 494 495/* Find an entry in the third-level page table.. */ 496static inline pte_t * pte_offset(pmd_t * dir, unsigned long address) 497{ 498 return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); 499} 500 501#define pte_ERROR(e) \ 502 printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e)) 503#define pmd_ERROR(e) \ 504 printk("%s:%d: bad pmd %p(%08lx).\n", __FILE__, __LINE__, &(e), pmd_val(e)) 505#define pgd_ERROR(e) \ 506 printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e)) 507 508extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */ 509 510/* 511 * CRIS doesn't have any external MMU info: the kernel page 512 * tables contain all the necessary information. 513 * 514 * Actually I am not sure on what this could be used for. 515 */ 516static inline void update_mmu_cache(struct vm_area_struct * vma, 517 unsigned long address, pte_t pte) 518{ 519} 520 521/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */ 522/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */ 523 524#define SWP_TYPE(x) (((x).val >> 5) & 0x7f) 525#define SWP_OFFSET(x) ((x).val >> 12) 526#define SWP_ENTRY(type, offset) ((swp_entry_t) { ((type) << 5) | ((offset) << 12) }) 527#define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 528#define swp_entry_to_pte(x) ((pte_t) { (x).val }) 529 530/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 531#define PageSkip(page) (0) 532#define kern_addr_valid(addr) (1) 533 534#include <asm-generic/pgtable.h> 535 536/* 537 * No page table caches to initialise 538 */ 539#define pgtable_cache_init() do { } while (0) 540 541#endif /* _CRIS_PGTABLE_H */ 542