1/***************************************************************************\ 2|* *| 3|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 4|* *| 5|* NOTICE TO USER: The source code is copyrighted under U.S. and *| 6|* international laws. Users and possessors of this source code are *| 7|* hereby granted a nonexclusive, royalty-free copyright license to *| 8|* use this code in individual and commercial software. *| 9|* *| 10|* Any use of this source code must include, in the user documenta- *| 11|* tion and internal comments to the code, notices to the end user *| 12|* as follows: *| 13|* *| 14|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 15|* *| 16|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| 17|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| 18|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| 19|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| 20|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| 21|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| 22|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| 23|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| 24|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| 25|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| 26|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| 27|* *| 28|* U.S. Government End Users. This source code is a "commercial *| 29|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| 30|* consisting of "commercial computer software" and "commercial *| 31|* computer software documentation," as such terms are used in *| 32|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| 33|* ment only as a commercial end item. Consistent with 48 C.F.R. *| 34|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| 35|* all U.S. Government End Users acquire the source code with only *| 36|* those rights set forth herein. *| 37|* *| 38\***************************************************************************/ 39 40/* 41 * GPL licensing note -- nVidia is allowing a liberal interpretation of 42 * the documentation restriction above, to merely say that this nVidia's 43 * copyright and disclaimer should be included with all code derived 44 * from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 45 */ 46 47/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.6 2000/02/08 17:19:12 dawes Exp $ */ 48#ifndef __RIVA_HW_H__ 49#define __RIVA_HW_H__ 50#define RIVA_SW_VERSION 0x00010003 51 52/* 53 * Typedefs to force certain sized values. 54 */ 55typedef unsigned char U008; 56typedef unsigned short U016; 57typedef unsigned int U032; 58 59/* 60 * HW access macros. 61 */ 62#define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d)) 63#define NV_RD08(p,i) (((U008 *)(p))[i]) 64#define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d)) 65#define NV_RD16(p,i) (((U016 *)(p))[(i)/2]) 66#define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d)) 67#define NV_RD32(p,i) (((U032 *)(p))[(i)/4]) 68#define VGA_WR08(p,i,d) NV_WR08(p,i,d) 69#define VGA_RD08(p,i) NV_RD08(p,i) 70 71/* 72 * Define supported architectures. 73 */ 74#define NV_ARCH_03 0x03 75#define NV_ARCH_04 0x04 76#define NV_ARCH_10 0x10 77#define NV_ARCH_20 0x20 78 79/***************************************************************************\ 80* * 81* FIFO registers. * 82* * 83\***************************************************************************/ 84 85/* 86 * Raster OPeration. Windows style ROP3. 87 */ 88typedef volatile struct 89{ 90 U032 reserved00[4]; 91 U016 FifoFree; 92 U016 Nop; 93 U032 reserved01[0x0BB]; 94 U032 Rop3; 95} RivaRop; 96/* 97 * 8X8 Monochrome pattern. 98 */ 99typedef volatile struct 100{ 101 U032 reserved00[4]; 102 U016 FifoFree; 103 U016 Nop; 104 U032 reserved01[0x0BD]; 105 U032 Shape; 106 U032 reserved03[0x001]; 107 U032 Color0; 108 U032 Color1; 109 U032 Monochrome[2]; 110} RivaPattern; 111/* 112 * Scissor clip rectangle. 113 */ 114typedef volatile struct 115{ 116 U032 reserved00[4]; 117 U016 FifoFree; 118 U016 Nop; 119 U032 reserved01[0x0BB]; 120 U032 TopLeft; 121 U032 WidthHeight; 122} RivaClip; 123/* 124 * 2D filled rectangle. 125 */ 126typedef volatile struct 127{ 128 U032 reserved00[4]; 129 U016 FifoFree; 130 U016 Nop[1]; 131 U032 reserved01[0x0BC]; 132 U032 Color; 133 U032 reserved03[0x03E]; 134 U032 TopLeft; 135 U032 WidthHeight; 136} RivaRectangle; 137/* 138 * 2D screen-screen BLT. 139 */ 140typedef volatile struct 141{ 142 U032 reserved00[4]; 143 U016 FifoFree; 144 U016 Nop; 145 U032 reserved01[0x0BB]; 146 U032 TopLeftSrc; 147 U032 TopLeftDst; 148 U032 WidthHeight; 149} RivaScreenBlt; 150/* 151 * 2D pixel BLT. 152 */ 153typedef volatile struct 154{ 155 U032 reserved00[4]; 156 U016 FifoFree; 157 U016 Nop[1]; 158 U032 reserved01[0x0BC]; 159 U032 TopLeft; 160 U032 WidthHeight; 161 U032 WidthHeightIn; 162 U032 reserved02[0x03C]; 163 U032 Pixels; 164} RivaPixmap; 165/* 166 * Filled rectangle combined with monochrome expand. Useful for glyphs. 167 */ 168typedef volatile struct 169{ 170 U032 reserved00[4]; 171 U016 FifoFree; 172 U016 Nop; 173 U032 reserved01[0x0BB]; 174 U032 reserved03[(0x040)-1]; 175 U032 Color1A; 176 struct 177 { 178 U032 TopLeft; 179 U032 WidthHeight; 180 } UnclippedRectangle[64]; 181 U032 reserved04[(0x080)-3]; 182 struct 183 { 184 U032 TopLeft; 185 U032 BottomRight; 186 } ClipB; 187 U032 Color1B; 188 struct 189 { 190 U032 TopLeft; 191 U032 BottomRight; 192 } ClippedRectangle[64]; 193 U032 reserved05[(0x080)-5]; 194 struct 195 { 196 U032 TopLeft; 197 U032 BottomRight; 198 } ClipC; 199 U032 Color1C; 200 U032 WidthHeightC; 201 U032 PointC; 202 U032 MonochromeData1C; 203 U032 reserved06[(0x080)+121]; 204 struct 205 { 206 U032 TopLeft; 207 U032 BottomRight; 208 } ClipD; 209 U032 Color1D; 210 U032 WidthHeightInD; 211 U032 WidthHeightOutD; 212 U032 PointD; 213 U032 MonochromeData1D; 214 U032 reserved07[(0x080)+120]; 215 struct 216 { 217 U032 TopLeft; 218 U032 BottomRight; 219 } ClipE; 220 U032 Color0E; 221 U032 Color1E; 222 U032 WidthHeightInE; 223 U032 WidthHeightOutE; 224 U032 PointE; 225 U032 MonochromeData01E; 226} RivaBitmap; 227/* 228 * 3D textured, Z buffered triangle. 229 */ 230typedef volatile struct 231{ 232 U032 reserved00[4]; 233 U016 FifoFree; 234 U016 Nop; 235 U032 reserved01[0x0BC]; 236 U032 TextureOffset; 237 U032 TextureFormat; 238 U032 TextureFilter; 239 U032 FogColor; 240/* This is a problem on LynxOS */ 241#ifdef Control 242#undef Control 243#endif 244 U032 Control; 245 U032 AlphaTest; 246 U032 reserved02[0x339]; 247 U032 FogAndIndex; 248 U032 Color; 249 float ScreenX; 250 float ScreenY; 251 float ScreenZ; 252 float EyeM; 253 float TextureS; 254 float TextureT; 255} RivaTexturedTriangle03; 256typedef volatile struct 257{ 258 U032 reserved00[4]; 259 U016 FifoFree; 260 U016 Nop; 261 U032 reserved01[0x0BB]; 262 U032 ColorKey; 263 U032 TextureOffset; 264 U032 TextureFormat; 265 U032 TextureFilter; 266 U032 Blend; 267/* This is a problem on LynxOS */ 268#ifdef Control 269#undef Control 270#endif 271 U032 Control; 272 U032 FogColor; 273 U032 reserved02[0x39]; 274 struct 275 { 276 float ScreenX; 277 float ScreenY; 278 float ScreenZ; 279 float EyeM; 280 U032 Color; 281 U032 Specular; 282 float TextureS; 283 float TextureT; 284 } Vertex[16]; 285 U032 DrawTriangle3D; 286} RivaTexturedTriangle05; 287/* 288 * 2D line. 289 */ 290typedef volatile struct 291{ 292 U032 reserved00[4]; 293 U016 FifoFree; 294 U016 Nop[1]; 295 U032 reserved01[0x0BC]; 296 U032 Color; /* source color 0304-0307*/ 297 U032 Reserved02[0x03e]; 298 struct { /* start aliased methods in array 0400- */ 299 U032 point0; /* y_x S16_S16 in pixels 0- 3*/ 300 U032 point1; /* y_x S16_S16 in pixels 4- 7*/ 301 } Lin[16]; /* end of aliased methods in array -047f*/ 302 struct { /* start aliased methods in array 0480- */ 303 U032 point0X; /* in pixels, 0 at left 0- 3*/ 304 U032 point0Y; /* in pixels, 0 at top 4- 7*/ 305 U032 point1X; /* in pixels, 0 at left 8- b*/ 306 U032 point1Y; /* in pixels, 0 at top c- f*/ 307 } Lin32[8]; /* end of aliased methods in array -04ff*/ 308 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/ 309 struct { /* start aliased methods in array 0580- */ 310 U032 x; /* in pixels, 0 at left 0- 3*/ 311 U032 y; /* in pixels, 0 at top 4- 7*/ 312 } PolyLin32[16]; /* end of aliased methods in array -05ff*/ 313 struct { /* start aliased methods in array 0600- */ 314 U032 color; /* source color 0- 3*/ 315 U032 point; /* y_x S16_S16 in pixels 4- 7*/ 316 } ColorPolyLin[16]; /* end of aliased methods in array -067f*/ 317} RivaLine; 318/* 319 * 2D/3D surfaces 320 */ 321typedef volatile struct 322{ 323 U032 reserved00[4]; 324 U016 FifoFree; 325 U016 Nop; 326 U032 reserved01[0x0BE]; 327 U032 Offset; 328} RivaSurface; 329typedef volatile struct 330{ 331 U032 reserved00[4]; 332 U016 FifoFree; 333 U016 Nop; 334 U032 reserved01[0x0BD]; 335 U032 Pitch; 336 U032 RenderBufferOffset; 337 U032 ZBufferOffset; 338} RivaSurface3D; 339 340/***************************************************************************\ 341* * 342* Virtualized RIVA H/W interface. * 343* * 344\***************************************************************************/ 345 346struct _riva_hw_inst; 347struct _riva_hw_state; 348/* 349 * Virtialized chip interface. Makes RIVA 128 and TNT look alike. 350 */ 351typedef struct _riva_hw_inst 352{ 353 /* 354 * Chip specific settings. 355 */ 356 U032 Architecture; 357 U032 Version; 358 U032 CrystalFreqKHz; 359 U032 RamAmountKBytes; 360 U032 MaxVClockFreqKHz; 361 U032 RamBandwidthKBytesPerSec; 362 U032 EnableIRQ; 363 U032 IO; 364 U032 VBlankBit; 365 U032 FifoFreeCount; 366 U032 FifoEmptyCount; 367 /* 368 * Non-FIFO registers. 369 */ 370 volatile U032 *PCRTC; 371 volatile U032 *PRAMDAC; 372 volatile U032 *PFB; 373 volatile U032 *PFIFO; 374 volatile U032 *PGRAPH; 375 volatile U032 *PEXTDEV; 376 volatile U032 *PTIMER; 377 volatile U032 *PMC; 378 volatile U032 *PRAMIN; 379 volatile U032 *FIFO; 380 volatile U032 *CURSOR; 381 volatile U032 *CURSORPOS; 382 volatile U032 *VBLANKENABLE; 383 volatile U032 *VBLANK; 384 volatile U008 *PCIO; 385 volatile U008 *PVIO; 386 volatile U008 *PDIO; 387 /* 388 * Common chip functions. 389 */ 390 int (*Busy)(struct _riva_hw_inst *); 391 void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int,int,int,int,int,int,int,int,int); 392 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); 393 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); 394 void (*SetStartAddress)(struct _riva_hw_inst *,U032); 395 void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032); 396 void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032); 397 int (*ShowHideCursor)(struct _riva_hw_inst *,int); 398 void (*LockUnlock)(struct _riva_hw_inst *, int); 399 /* 400 * Current extended mode settings. 401 */ 402 struct _riva_hw_state *CurrentState; 403 /* 404 * FIFO registers. 405 */ 406 RivaRop *Rop; 407 RivaPattern *Patt; 408 RivaClip *Clip; 409 RivaPixmap *Pixmap; 410 RivaScreenBlt *Blt; 411 RivaBitmap *Bitmap; 412 RivaLine *Line; 413 RivaTexturedTriangle03 *Tri03; 414 RivaTexturedTriangle05 *Tri05; 415} RIVA_HW_INST; 416/* 417 * Extended mode state information. 418 */ 419typedef struct _riva_hw_state 420{ 421 U032 bpp; 422 U032 width; 423 U032 height; 424 U032 repaint0; 425 U032 repaint1; 426 U032 screen; 427 U032 pixel; 428 U032 horiz; 429 U032 arbitration0; 430 U032 arbitration1; 431 U032 vpll; 432 U032 pllsel; 433 U032 general; 434 U032 config; 435 U032 cursor0; 436 U032 cursor1; 437 U032 cursor2; 438 U032 offset0; 439 U032 offset1; 440 U032 offset2; 441 U032 offset3; 442 U032 pitch0; 443 U032 pitch1; 444 U032 pitch2; 445 U032 pitch3; 446} RIVA_HW_STATE; 447/* 448 * External routines. 449 */ 450int RivaGetConfig(RIVA_HW_INST *); 451/* 452 * FIFO Free Count. Should attempt to yield processor if RIVA is busy. 453 */ 454 455#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \ 456{ \ 457 while ((hwinst).FifoFreeCount < (cnt)) \ 458 (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2; \ 459 (hwinst).FifoFreeCount -= (cnt); \ 460} 461#endif /* __RIVA_HW_H__ */ 462 463