1#ifndef _RADEON_H 2#define _RADEON_H 3 4 5/* radeon PCI ids */ 6#define PCI_DEVICE_ID_RADEON_QD 0x5144 7#define PCI_DEVICE_ID_RADEON_QE 0x5145 8#define PCI_DEVICE_ID_RADEON_QF 0x5146 9#define PCI_DEVICE_ID_RADEON_QG 0x5147 10#define PCI_DEVICE_ID_RADEON_QY 0x5159 11#define PCI_DEVICE_ID_RADEON_QZ 0x515a 12#define PCI_DEVICE_ID_RADEON_LW 0x4c57 13#define PCI_DEVICE_ID_RADEON_LY 0x4c59 14#define PCI_DEVICE_ID_RADEON_LZ 0x4c5a 15#define PCI_DEVICE_ID_RADEON_PM 0x4c52 16#define PCI_DEVICE_ID_RADEON_QL 0x514c 17#define PCI_DEVICE_ID_RADEON_QW 0x5157 18 19#define RADEON_REGSIZE 0x4000 20 21 22#define MM_INDEX 0x0000 23#define MM_DATA 0x0004 24#define BUS_CNTL 0x0030 25#define HI_STAT 0x004C 26#define BUS_CNTL1 0x0034 27#define I2C_CNTL_1 0x0094 28#define CONFIG_CNTL 0x00E0 29#define CONFIG_MEMSIZE 0x00F8 30#define CONFIG_APER_0_BASE 0x0100 31#define CONFIG_APER_1_BASE 0x0104 32#define CONFIG_APER_SIZE 0x0108 33#define CONFIG_REG_1_BASE 0x010C 34#define CONFIG_REG_APER_SIZE 0x0110 35#define PAD_AGPINPUT_DELAY 0x0164 36#define PAD_CTLR_STRENGTH 0x0168 37#define PAD_CTLR_UPDATE 0x016C 38#define AGP_CNTL 0x0174 39#define BM_STATUS 0x0160 40#define CAP0_TRIG_CNTL 0x0950 41#define VIPH_CONTROL 0x0C40 42#define VENDOR_ID 0x0F00 43#define DEVICE_ID 0x0F02 44#define COMMAND 0x0F04 45#define STATUS 0x0F06 46#define REVISION_ID 0x0F08 47#define REGPROG_INF 0x0F09 48#define SUB_CLASS 0x0F0A 49#define BASE_CODE 0x0F0B 50#define CACHE_LINE 0x0F0C 51#define LATENCY 0x0F0D 52#define HEADER 0x0F0E 53#define BIST 0x0F0F 54#define REG_MEM_BASE 0x0F10 55#define REG_IO_BASE 0x0F14 56#define REG_REG_BASE 0x0F18 57#define ADAPTER_ID 0x0F2C 58#define BIOS_ROM 0x0F30 59#define CAPABILITIES_PTR 0x0F34 60#define INTERRUPT_LINE 0x0F3C 61#define INTERRUPT_PIN 0x0F3D 62#define MIN_GRANT 0x0F3E 63#define MAX_LATENCY 0x0F3F 64#define ADAPTER_ID_W 0x0F4C 65#define PMI_CAP_ID 0x0F50 66#define PMI_NXT_CAP_PTR 0x0F51 67#define PMI_PMC_REG 0x0F52 68#define PM_STATUS 0x0F54 69#define PMI_DATA 0x0F57 70#define AGP_CAP_ID 0x0F58 71#define AGP_STATUS 0x0F5C 72#define AGP_COMMAND 0x0F60 73#define AIC_CTRL 0x01D0 74#define AIC_STAT 0x01D4 75#define AIC_PT_BASE 0x01D8 76#define AIC_LO_ADDR 0x01DC 77#define AIC_HI_ADDR 0x01E0 78#define AIC_TLB_ADDR 0x01E4 79#define AIC_TLB_DATA 0x01E8 80#define DAC_CNTL 0x0058 81#define CRTC_GEN_CNTL 0x0050 82#define MEM_CNTL 0x0140 83#define EXT_MEM_CNTL 0x0144 84#define MC_AGP_LOCATION 0x014C 85#define MEM_IO_CNTL_A0 0x0178 86#define MEM_INIT_LATENCY_TIMER 0x0154 87#define MEM_SDRAM_MODE_REG 0x0158 88#define AGP_BASE 0x0170 89#define MEM_IO_CNTL_A1 0x017C 90#define MEM_IO_CNTL_B0 0x0180 91#define MEM_IO_CNTL_B1 0x0184 92#define MC_DEBUG 0x0188 93#define MC_STATUS 0x0150 94#define MEM_IO_OE_CNTL 0x018C 95#define MC_FB_LOCATION 0x0148 96#define HOST_PATH_CNTL 0x0130 97#define MEM_VGA_WP_SEL 0x0038 98#define MEM_VGA_RP_SEL 0x003C 99#define HDP_DEBUG 0x0138 100#define SW_SEMAPHORE 0x013C 101#define CRTC2_GEN_CNTL 0x03f8 102#define CRTC2_DISPLAY_BASE_ADDR 0x033c 103#define SURFACE_CNTL 0x0B00 104#define SURFACE0_LOWER_BOUND 0x0B04 105#define SURFACE1_LOWER_BOUND 0x0B14 106#define SURFACE2_LOWER_BOUND 0x0B24 107#define SURFACE3_LOWER_BOUND 0x0B34 108#define SURFACE4_LOWER_BOUND 0x0B44 109#define SURFACE5_LOWER_BOUND 0x0B54 110#define SURFACE6_LOWER_BOUND 0x0B64 111#define SURFACE7_LOWER_BOUND 0x0B74 112#define SURFACE0_UPPER_BOUND 0x0B08 113#define SURFACE1_UPPER_BOUND 0x0B18 114#define SURFACE2_UPPER_BOUND 0x0B28 115#define SURFACE3_UPPER_BOUND 0x0B38 116#define SURFACE4_UPPER_BOUND 0x0B48 117#define SURFACE5_UPPER_BOUND 0x0B58 118#define SURFACE6_UPPER_BOUND 0x0B68 119#define SURFACE7_UPPER_BOUND 0x0B78 120#define SURFACE0_INFO 0x0B0C 121#define SURFACE1_INFO 0x0B1C 122#define SURFACE2_INFO 0x0B2C 123#define SURFACE3_INFO 0x0B3C 124#define SURFACE4_INFO 0x0B4C 125#define SURFACE5_INFO 0x0B5C 126#define SURFACE6_INFO 0x0B6C 127#define SURFACE7_INFO 0x0B7C 128#define SURFACE_ACCESS_FLAGS 0x0BF8 129#define SURFACE_ACCESS_CLR 0x0BFC 130#define GEN_INT_CNTL 0x0040 131#define GEN_INT_STATUS 0x0044 132#define CRTC_EXT_CNTL 0x0054 133#define RB3D_CNTL 0x1C3C 134#define WAIT_UNTIL 0x1720 135#define ISYNC_CNTL 0x1724 136#define RBBM_GUICNTL 0x172C 137#define RBBM_STATUS 0x0E40 138#define RBBM_STATUS_alt_1 0x1740 139#define RBBM_CNTL 0x00EC 140#define RBBM_CNTL_alt_1 0x0E44 141#define RBBM_SOFT_RESET 0x00F0 142#define RBBM_SOFT_RESET_alt_1 0x0E48 143#define NQWAIT_UNTIL 0x0E50 144#define RBBM_DEBUG 0x0E6C 145#define RBBM_CMDFIFO_ADDR 0x0E70 146#define RBBM_CMDFIFO_DATAL 0x0E74 147#define RBBM_CMDFIFO_DATAH 0x0E78 148#define RBBM_CMDFIFO_STAT 0x0E7C 149#define CRTC_STATUS 0x005C 150#define GPIO_VGA_DDC 0x0060 151#define GPIO_DVI_DDC 0x0064 152#define GPIO_MONID 0x0068 153#define PALETTE_INDEX 0x00B0 154#define PALETTE_DATA 0x00B4 155#define PALETTE_30_DATA 0x00B8 156#define CRTC_H_TOTAL_DISP 0x0200 157#define CRTC_H_SYNC_STRT_WID 0x0204 158#define CRTC_V_TOTAL_DISP 0x0208 159#define CRTC_V_SYNC_STRT_WID 0x020C 160#define CRTC_VLINE_CRNT_VLINE 0x0210 161#define CRTC_CRNT_FRAME 0x0214 162#define CRTC_GUI_TRIG_VLINE 0x0218 163#define CRTC_DEBUG 0x021C 164#define CRTC_OFFSET_RIGHT 0x0220 165#define CRTC_OFFSET 0x0224 166#define CRTC_OFFSET_CNTL 0x0228 167#define CRTC_PITCH 0x022C 168#define OVR_CLR 0x0230 169#define OVR_WID_LEFT_RIGHT 0x0234 170#define OVR_WID_TOP_BOTTOM 0x0238 171#define DISPLAY_BASE_ADDR 0x023C 172#define SNAPSHOT_VH_COUNTS 0x0240 173#define SNAPSHOT_F_COUNT 0x0244 174#define N_VIF_COUNT 0x0248 175#define SNAPSHOT_VIF_COUNT 0x024C 176#define FP_CRTC_H_TOTAL_DISP 0x0250 177#define FP_CRTC_V_TOTAL_DISP 0x0254 178#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 179#define CRT_CRTC_V_SYNC_STRT_WID 0x025C 180#define CUR_OFFSET 0x0260 181#define CUR_HORZ_VERT_POSN 0x0264 182#define CUR_HORZ_VERT_OFF 0x0268 183#define CUR_CLR0 0x026C 184#define CUR_CLR1 0x0270 185#define FP_HORZ_VERT_ACTIVE 0x0278 186#define CRTC_MORE_CNTL 0x027C 187#define DAC_EXT_CNTL 0x0280 188#define FP_GEN_CNTL 0x0284 189#define FP_HORZ_STRETCH 0x028C 190#define FP_VERT_STRETCH 0x0290 191#define FP_H_SYNC_STRT_WID 0x02C4 192#define FP_V_SYNC_STRT_WID 0x02C8 193#define AUX_WINDOW_HORZ_CNTL 0x02D8 194#define AUX_WINDOW_VERT_CNTL 0x02DC 195#define DDA_CONFIG 0x02e0 196#define DDA_ON_OFF 0x02e4 197#define GRPH_BUFFER_CNTL 0x02F0 198#define VGA_BUFFER_CNTL 0x02F4 199#define OV0_Y_X_START 0x0400 200#define OV0_Y_X_END 0x0404 201#define OV0_PIPELINE_CNTL 0x0408 202#define OV0_REG_LOAD_CNTL 0x0410 203#define OV0_SCALE_CNTL 0x0420 204#define OV0_V_INC 0x0424 205#define OV0_P1_V_ACCUM_INIT 0x0428 206#define OV0_P23_V_ACCUM_INIT 0x042C 207#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 208#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 209#define OV0_BASE_ADDR 0x043C 210#define OV0_VID_BUF0_BASE_ADRS 0x0440 211#define OV0_VID_BUF1_BASE_ADRS 0x0444 212#define OV0_VID_BUF2_BASE_ADRS 0x0448 213#define OV0_VID_BUF3_BASE_ADRS 0x044C 214#define OV0_VID_BUF4_BASE_ADRS 0x0450 215#define OV0_VID_BUF5_BASE_ADRS 0x0454 216#define OV0_VID_BUF_PITCH0_VALUE 0x0460 217#define OV0_VID_BUF_PITCH1_VALUE 0x0464 218#define OV0_AUTO_FLIP_CNTRL 0x0470 219#define OV0_DEINTERLACE_PATTERN 0x0474 220#define OV0_SUBMIT_HISTORY 0x0478 221#define OV0_H_INC 0x0480 222#define OV0_STEP_BY 0x0484 223#define OV0_P1_H_ACCUM_INIT 0x0488 224#define OV0_P23_H_ACCUM_INIT 0x048C 225#define OV0_P1_X_START_END 0x0494 226#define OV0_P2_X_START_END 0x0498 227#define OV0_P3_X_START_END 0x049C 228#define OV0_FILTER_CNTL 0x04A0 229#define OV0_FOUR_TAP_COEF_0 0x04B0 230#define OV0_FOUR_TAP_COEF_1 0x04B4 231#define OV0_FOUR_TAP_COEF_2 0x04B8 232#define OV0_FOUR_TAP_COEF_3 0x04BC 233#define OV0_FOUR_TAP_COEF_4 0x04C0 234#define OV0_FLAG_CNTRL 0x04DC 235#define OV0_SLICE_CNTL 0x04E0 236#define OV0_VID_KEY_CLR_LOW 0x04E4 237#define OV0_VID_KEY_CLR_HIGH 0x04E8 238#define OV0_GRPH_KEY_CLR_LOW 0x04EC 239#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 240#define OV0_KEY_CNTL 0x04F4 241#define OV0_TEST 0x04F8 242#define SUBPIC_CNTL 0x0540 243#define SUBPIC_DEFCOLCON 0x0544 244#define SUBPIC_Y_X_START 0x054C 245#define SUBPIC_Y_X_END 0x0550 246#define SUBPIC_V_INC 0x0554 247#define SUBPIC_H_INC 0x0558 248#define SUBPIC_BUF0_OFFSET 0x055C 249#define SUBPIC_BUF1_OFFSET 0x0560 250#define SUBPIC_LC0_OFFSET 0x0564 251#define SUBPIC_LC1_OFFSET 0x0568 252#define SUBPIC_PITCH 0x056C 253#define SUBPIC_BTN_HLI_COLCON 0x0570 254#define SUBPIC_BTN_HLI_Y_X_START 0x0574 255#define SUBPIC_BTN_HLI_Y_X_END 0x0578 256#define SUBPIC_PALETTE_INDEX 0x057C 257#define SUBPIC_PALETTE_DATA 0x0580 258#define SUBPIC_H_ACCUM_INIT 0x0584 259#define SUBPIC_V_ACCUM_INIT 0x0588 260#define DISP_MISC_CNTL 0x0D00 261#define DAC_MACRO_CNTL 0x0D04 262#define DISP_PWR_MAN 0x0D08 263#define DISP_TEST_DEBUG_CNTL 0x0D10 264#define DISP_HW_DEBUG 0x0D14 265#define DAC_CRC_SIG1 0x0D18 266#define DAC_CRC_SIG2 0x0D1C 267#define OV0_LIN_TRANS_A 0x0D20 268#define OV0_LIN_TRANS_B 0x0D24 269#define OV0_LIN_TRANS_C 0x0D28 270#define OV0_LIN_TRANS_D 0x0D2C 271#define OV0_LIN_TRANS_E 0x0D30 272#define OV0_LIN_TRANS_F 0x0D34 273#define OV0_GAMMA_0_F 0x0D40 274#define OV0_GAMMA_10_1F 0x0D44 275#define OV0_GAMMA_20_3F 0x0D48 276#define OV0_GAMMA_40_7F 0x0D4C 277#define OV0_GAMMA_380_3BF 0x0D50 278#define OV0_GAMMA_3C0_3FF 0x0D54 279#define DISP_MERGE_CNTL 0x0D60 280#define DISP_OUTPUT_CNTL 0x0D64 281#define DISP_LIN_TRANS_GRPH_A 0x0D80 282#define DISP_LIN_TRANS_GRPH_B 0x0D84 283#define DISP_LIN_TRANS_GRPH_C 0x0D88 284#define DISP_LIN_TRANS_GRPH_D 0x0D8C 285#define DISP_LIN_TRANS_GRPH_E 0x0D90 286#define DISP_LIN_TRANS_GRPH_F 0x0D94 287#define DISP_LIN_TRANS_VID_A 0x0D98 288#define DISP_LIN_TRANS_VID_B 0x0D9C 289#define DISP_LIN_TRANS_VID_C 0x0DA0 290#define DISP_LIN_TRANS_VID_D 0x0DA4 291#define DISP_LIN_TRANS_VID_E 0x0DA8 292#define DISP_LIN_TRANS_VID_F 0x0DAC 293#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 294#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 295#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 296#define RMX_HORZ_PHASE 0x0DBC 297#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 298#define DAC_BROAD_PULSE 0x0DC4 299#define DAC_SKEW_CLKS 0x0DC8 300#define DAC_INCR 0x0DCC 301#define DAC_NEG_SYNC_LEVEL 0x0DD0 302#define DAC_POS_SYNC_LEVEL 0x0DD4 303#define DAC_BLANK_LEVEL 0x0DD8 304#define CLOCK_CNTL_INDEX 0x0008 305#define CLOCK_CNTL_DATA 0x000C 306#define CP_RB_CNTL 0x0704 307#define CP_RB_BASE 0x0700 308#define CP_RB_RPTR_ADDR 0x070C 309#define CP_RB_RPTR 0x0710 310#define CP_RB_WPTR 0x0714 311#define CP_RB_WPTR_DELAY 0x0718 312#define CP_IB_BASE 0x0738 313#define CP_IB_BUFSZ 0x073C 314#define SCRATCH_REG0 0x15E0 315#define GUI_SCRATCH_REG0 0x15E0 316#define SCRATCH_REG1 0x15E4 317#define GUI_SCRATCH_REG1 0x15E4 318#define SCRATCH_REG2 0x15E8 319#define GUI_SCRATCH_REG2 0x15E8 320#define SCRATCH_REG3 0x15EC 321#define GUI_SCRATCH_REG3 0x15EC 322#define SCRATCH_REG4 0x15F0 323#define GUI_SCRATCH_REG4 0x15F0 324#define SCRATCH_REG5 0x15F4 325#define GUI_SCRATCH_REG5 0x15F4 326#define SCRATCH_UMSK 0x0770 327#define SCRATCH_ADDR 0x0774 328#define DP_BRUSH_FRGD_CLR 0x147C 329#define DP_BRUSH_BKGD_CLR 0x1478 330#define DST_LINE_START 0x1600 331#define DST_LINE_END 0x1604 332#define SRC_OFFSET 0x15AC 333#define SRC_PITCH 0x15B0 334#define SRC_TILE 0x1704 335#define SRC_PITCH_OFFSET 0x1428 336#define SRC_X 0x1414 337#define SRC_Y 0x1418 338#define SRC_X_Y 0x1590 339#define SRC_Y_X 0x1434 340#define DST_Y_X 0x1438 341#define DST_WIDTH_HEIGHT 0x1598 342#define DST_HEIGHT_WIDTH 0x143c 343#define DST_OFFSET 0x1404 344#define SRC_CLUT_ADDRESS 0x1780 345#define SRC_CLUT_DATA 0x1784 346#define SRC_CLUT_DATA_RD 0x1788 347#define HOST_DATA0 0x17C0 348#define HOST_DATA1 0x17C4 349#define HOST_DATA2 0x17C8 350#define HOST_DATA3 0x17CC 351#define HOST_DATA4 0x17D0 352#define HOST_DATA5 0x17D4 353#define HOST_DATA6 0x17D8 354#define HOST_DATA7 0x17DC 355#define HOST_DATA_LAST 0x17E0 356#define DP_SRC_ENDIAN 0x15D4 357#define DP_SRC_FRGD_CLR 0x15D8 358#define DP_SRC_BKGD_CLR 0x15DC 359#define SC_LEFT 0x1640 360#define SC_RIGHT 0x1644 361#define SC_TOP 0x1648 362#define SC_BOTTOM 0x164C 363#define SRC_SC_RIGHT 0x1654 364#define SRC_SC_BOTTOM 0x165C 365#define DP_CNTL 0x16C0 366#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 367#define DP_DATATYPE 0x16C4 368#define DP_MIX 0x16C8 369#define DP_WRITE_MSK 0x16CC 370#define DP_XOP 0x17F8 371#define CLR_CMP_CLR_SRC 0x15C4 372#define CLR_CMP_CLR_DST 0x15C8 373#define CLR_CMP_CNTL 0x15C0 374#define CLR_CMP_MSK 0x15CC 375#define DSTCACHE_MODE 0x1710 376#define DSTCACHE_CTLSTAT 0x1714 377#define DEFAULT_PITCH_OFFSET 0x16E0 378#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 379#define DP_GUI_MASTER_CNTL 0x146C 380#define SC_TOP_LEFT 0x16EC 381#define SC_BOTTOM_RIGHT 0x16F0 382#define SRC_SC_BOTTOM_RIGHT 0x16F4 383#define RB2D_DSTCACHE_CTLSTAT 0x342C 384#define LVDS_GEN_CNTL 0x02d0 385#define LVDS_PLL_CNTL 0x02d4 386#define TMDS_CRC 0x02a0 387#define TMDS_TRANSMITTER_CNTL 0x02a4 388 389#define RADEON_BASE_CODE 0x0f0b 390#define RADEON_BIOS_0_SCRATCH 0x0010 391#define RADEON_BIOS_1_SCRATCH 0x0014 392#define RADEON_BIOS_2_SCRATCH 0x0018 393#define RADEON_BIOS_3_SCRATCH 0x001c 394#define RADEON_BIOS_4_SCRATCH 0x0020 395#define RADEON_BIOS_5_SCRATCH 0x0024 396#define RADEON_BIOS_6_SCRATCH 0x0028 397#define RADEON_BIOS_7_SCRATCH 0x002c 398 399 400#define CLK_PIN_CNTL 0x0001 401#define PPLL_CNTL 0x0002 402#define PPLL_REF_DIV 0x0003 403#define PPLL_DIV_0 0x0004 404#define PPLL_DIV_1 0x0005 405#define PPLL_DIV_2 0x0006 406#define PPLL_DIV_3 0x0007 407#define VCLK_ECP_CNTL 0x0008 408#define HTOTAL_CNTL 0x0009 409#define M_SPLL_REF_FB_DIV 0x000a 410#define AGP_PLL_CNTL 0x000b 411#define SPLL_CNTL 0x000c 412#define SCLK_CNTL 0x000d 413#define MPLL_CNTL 0x000e 414#define MDLL_CKO 0x000f 415#define MCLK_CNTL 0x0012 416#define AGP_PLL_CNTL 0x000b 417#define PLL_TEST_CNTL 0x0013 418 419/* MCLK_CNTL bit constants */ 420#define FORCEON_MCLKA (1 << 16) 421#define FORCEON_MCLKB (1 << 17) 422#define FORCEON_YCLKA (1 << 18) 423#define FORCEON_YCLKB (1 << 19) 424#define FORCEON_MC (1 << 20) 425#define FORCEON_AIC (1 << 21) 426 427 428/* BUS_CNTL bit constants */ 429#define BUS_DBL_RESYNC 0x00000001 430#define BUS_MSTR_RESET 0x00000002 431#define BUS_FLUSH_BUF 0x00000004 432#define BUS_STOP_REQ_DIS 0x00000008 433#define BUS_ROTATION_DIS 0x00000010 434#define BUS_MASTER_DIS 0x00000040 435#define BUS_ROM_WRT_EN 0x00000080 436#define BUS_DIS_ROM 0x00001000 437#define BUS_PCI_READ_RETRY_EN 0x00002000 438#define BUS_AGP_AD_STEPPING_EN 0x00004000 439#define BUS_PCI_WRT_RETRY_EN 0x00008000 440#define BUS_MSTR_RD_MULT 0x00100000 441#define BUS_MSTR_RD_LINE 0x00200000 442#define BUS_SUSPEND 0x00400000 443#define LAT_16X 0x00800000 444#define BUS_RD_DISCARD_EN 0x01000000 445#define BUS_RD_ABORT_EN 0x02000000 446#define BUS_MSTR_WS 0x04000000 447#define BUS_PARKING_DIS 0x08000000 448#define BUS_MSTR_DISCONNECT_EN 0x10000000 449#define BUS_WRT_BURST 0x20000000 450#define BUS_READ_BURST 0x40000000 451#define BUS_RDY_READ_DLY 0x80000000 452 453 454/* CLOCK_CNTL_INDEX bit constants */ 455#define PLL_WR_EN 0x00000080 456 457/* CONFIG_CNTL bit constants */ 458#define CFG_VGA_RAM_EN 0x00000100 459 460/* CRTC_EXT_CNTL bit constants */ 461#define VGA_ATI_LINEAR 0x00000008 462#define VGA_128KAP_PAGING 0x00000010 463#define XCRT_CNT_EN (1 << 6) 464#define CRTC_HSYNC_DIS (1 << 8) 465#define CRTC_VSYNC_DIS (1 << 9) 466#define CRTC_DISPLAY_DIS (1 << 10) 467#define CRTC_CRT_ON (1 << 15) 468 469 470/* DSTCACHE_CTLSTAT bit constants */ 471#define RB2D_DC_FLUSH (3 << 0) 472#define RB2D_DC_FLUSH_ALL 0xf 473#define RB2D_DC_BUSY (1 << 31) 474 475 476/* CRTC_GEN_CNTL bit constants */ 477#define CRTC_DBL_SCAN_EN 0x00000001 478#define CRTC_CUR_EN 0x00010000 479#define CRTC_INTERLACE_EN (1 << 1) 480#define CRTC_EXT_DISP_EN (1 << 24) 481#define CRTC_EN (1 << 25) 482#define CRTC_DISP_REQ_EN_B (1 << 26) 483 484/* CRTC_STATUS bit constants */ 485#define CRTC_VBLANK 0x00000001 486 487/* CRTC2_GEN_CNTL bit constants */ 488#define CRT2_ON (1 << 7) 489#define CRTC2_DISPLAY_DIS (1 << 23) 490#define CRTC2_EN (1 << 25) 491#define CRTC2_DISP_REQ_EN_B (1 << 26) 492 493/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ 494#define CUR_LOCK 0x80000000 495 496 497/* FP bit constants */ 498#define FP_CRTC_H_TOTAL_MASK 0x000003ff 499#define FP_CRTC_H_DISP_MASK 0x01ff0000 500#define FP_CRTC_V_TOTAL_MASK 0x00000fff 501#define FP_CRTC_V_DISP_MASK 0x0fff0000 502#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 503#define FP_H_SYNC_WID_MASK 0x003f0000 504#define FP_V_SYNC_STRT_MASK 0x00000fff 505#define FP_V_SYNC_WID_MASK 0x001f0000 506#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 507#define FP_CRTC_H_DISP_SHIFT 0x00000010 508#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 509#define FP_CRTC_V_DISP_SHIFT 0x00000010 510#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 511#define FP_H_SYNC_WID_SHIFT 0x00000010 512#define FP_V_SYNC_STRT_SHIFT 0x00000000 513#define FP_V_SYNC_WID_SHIFT 0x00000010 514 515/* FP_GEN_CNTL bit constants */ 516#define FP_FPON (1 << 0) 517#define FP_TMDS_EN (1 << 2) 518#define FP_EN_TMDS (1 << 7) 519#define FP_DETECT_SENSE (1 << 8) 520#define FP_SEL_CRTC2 (1 << 13) 521#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 522#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 523#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) 524#define FP_CRTC_USE_SHADOW_VEND (1 << 18) 525#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 526#define FP_DFP_SYNC_SEL (1 << 21) 527#define FP_CRTC_LOCK_8DOT (1 << 22) 528#define FP_CRT_SYNC_SEL (1 << 23) 529#define FP_USE_SHADOW_EN (1 << 24) 530#define FP_CRT_SYNC_ALT (1 << 26) 531 532/* LVDS_GEN_CNTL bit constants */ 533#define LVDS_ON (1 << 0) 534#define LVDS_DISPLAY_DIS (1 << 1) 535#define LVDS_PANEL_TYPE (1 << 2) 536#define LVDS_PANEL_FORMAT (1 << 3) 537#define LVDS_EN (1 << 7) 538#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 539#define LVDS_BL_MOD_LEVEL_SHIFT 8 540#define LVDS_BL_MOD_EN (1 << 16) 541#define LVDS_DIGON (1 << 18) 542#define LVDS_BLON (1 << 19) 543#define LVDS_SEL_CRTC2 (1 << 23) 544#define LVDS_STATE_MASK \ 545 (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | \ 546 LVDS_EN | LVDS_DIGON | LVDS_BLON) 547 548/* LVDS_PLL_CNTL bit constatns */ 549#define HSYNC_DELAY_SHIFT 0x1c 550#define HSYNC_DELAY_MASK (0xf << 0x1c) 551 552/* TMDS_TRANSMITTER_CNTL bit constants */ 553#define TMDS_PLL_EN (1 << 0) 554#define TMDS_PLLRST (1 << 1) 555#define TMDS_RAN_PAT_RST (1 << 7) 556#define ICHCSEL (1 << 28) 557 558/* FP_HORZ_STRETCH bit constants */ 559#define HORZ_STRETCH_RATIO_MASK 0xffff 560#define HORZ_STRETCH_RATIO_MAX 4096 561#define HORZ_PANEL_SIZE (0x1ff << 16) 562#define HORZ_PANEL_SHIFT 16 563#define HORZ_STRETCH_PIXREP (0 << 25) 564#define HORZ_STRETCH_BLEND (1 << 26) 565#define HORZ_STRETCH_ENABLE (1 << 25) 566#define HORZ_AUTO_RATIO (1 << 27) 567#define HORZ_FP_LOOP_STRETCH (0x7 << 28) 568#define HORZ_AUTO_RATIO_INC (1 << 31) 569 570 571/* FP_VERT_STRETCH bit constants */ 572#define VERT_STRETCH_RATIO_MASK 0xfff 573#define VERT_STRETCH_RATIO_MAX 4096 574#define VERT_PANEL_SIZE (0xfff << 12) 575#define VERT_PANEL_SHIFT 12 576#define VERT_STRETCH_LINREP (0 << 26) 577#define VERT_STRETCH_BLEND (1 << 26) 578#define VERT_STRETCH_ENABLE (1 << 25) 579#define VERT_AUTO_RATIO_EN (1 << 27) 580#define VERT_FP_LOOP_STRETCH (0x7 << 28) 581#define VERT_STRETCH_RESERVED 0xf1000000 582 583/* DAC_CNTL bit constants */ 584#define DAC_8BIT_EN 0x00000100 585#define DAC_4BPP_PIX_ORDER 0x00000200 586#define DAC_CRC_EN 0x00080000 587#define DAC_MASK_ALL (0xff << 24) 588#define DAC_EXPAND_MODE (1 << 14) 589#define DAC_VGA_ADR_EN (1 << 13) 590#define DAC_RANGE_CNTL (3 << 0) 591#define DAC_BLANKING (1 << 2) 592 593/* GEN_RESET_CNTL bit constants */ 594#define SOFT_RESET_GUI 0x00000001 595#define SOFT_RESET_VCLK 0x00000100 596#define SOFT_RESET_PCLK 0x00000200 597#define SOFT_RESET_ECP 0x00000400 598#define SOFT_RESET_DISPENG_XCLK 0x00000800 599 600/* MEM_CNTL bit constants */ 601#define MEM_CTLR_STATUS_IDLE 0x00000000 602#define MEM_CTLR_STATUS_BUSY 0x00100000 603#define MEM_SEQNCR_STATUS_IDLE 0x00000000 604#define MEM_SEQNCR_STATUS_BUSY 0x00200000 605#define MEM_ARBITER_STATUS_IDLE 0x00000000 606#define MEM_ARBITER_STATUS_BUSY 0x00400000 607#define MEM_REQ_UNLOCK 0x00000000 608#define MEM_REQ_LOCK 0x00800000 609 610 611/* RBBM_SOFT_RESET bit constants */ 612#define SOFT_RESET_CP (1 << 0) 613#define SOFT_RESET_HI (1 << 1) 614#define SOFT_RESET_SE (1 << 2) 615#define SOFT_RESET_RE (1 << 3) 616#define SOFT_RESET_PP (1 << 4) 617#define SOFT_RESET_E2 (1 << 5) 618#define SOFT_RESET_RB (1 << 6) 619#define SOFT_RESET_HDP (1 << 7) 620 621/* SURFACE_CNTL bit consants */ 622#define SURF_TRANSLATION_DIS (1 << 8) 623#define NONSURF_AP0_SWP_16BPP (1 << 20) 624#define NONSURF_AP0_SWP_32BPP (1 << 21) 625 626/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ 627#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 628#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 629 630/* MM_INDEX bit constants */ 631#define MM_APER 0x80000000 632 633/* CLR_CMP_CNTL bit constants */ 634#define COMPARE_SRC_FALSE 0x00000000 635#define COMPARE_SRC_TRUE 0x00000001 636#define COMPARE_SRC_NOT_EQUAL 0x00000004 637#define COMPARE_SRC_EQUAL 0x00000005 638#define COMPARE_SRC_EQUAL_FLIP 0x00000007 639#define COMPARE_DST_FALSE 0x00000000 640#define COMPARE_DST_TRUE 0x00000100 641#define COMPARE_DST_NOT_EQUAL 0x00000400 642#define COMPARE_DST_EQUAL 0x00000500 643#define COMPARE_DESTINATION 0x00000000 644#define COMPARE_SOURCE 0x01000000 645#define COMPARE_SRC_AND_DST 0x02000000 646 647 648/* DP_CNTL bit constants */ 649#define DST_X_RIGHT_TO_LEFT 0x00000000 650#define DST_X_LEFT_TO_RIGHT 0x00000001 651#define DST_Y_BOTTOM_TO_TOP 0x00000000 652#define DST_Y_TOP_TO_BOTTOM 0x00000002 653#define DST_X_MAJOR 0x00000000 654#define DST_Y_MAJOR 0x00000004 655#define DST_X_TILE 0x00000008 656#define DST_Y_TILE 0x00000010 657#define DST_LAST_PEL 0x00000020 658#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 659#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 660#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 661#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 662#define DST_BRES_SIGN 0x00000100 663#define DST_HOST_BIG_ENDIAN_EN 0x00000200 664#define DST_POLYLINE_NONLAST 0x00008000 665#define DST_RASTER_STALL 0x00010000 666#define DST_POLY_EDGE 0x00040000 667 668 669/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ 670#define DST_X_MAJOR_S 0x00000000 671#define DST_Y_MAJOR_S 0x00000001 672#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 673#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 674#define DST_X_RIGHT_TO_LEFT_S 0x00000000 675#define DST_X_LEFT_TO_RIGHT_S 0x80000000 676 677 678/* DP_DATATYPE bit constants */ 679#define DST_8BPP 0x00000002 680#define DST_15BPP 0x00000003 681#define DST_16BPP 0x00000004 682#define DST_24BPP 0x00000005 683#define DST_32BPP 0x00000006 684#define DST_8BPP_RGB332 0x00000007 685#define DST_8BPP_Y8 0x00000008 686#define DST_8BPP_RGB8 0x00000009 687#define DST_16BPP_VYUY422 0x0000000b 688#define DST_16BPP_YVYU422 0x0000000c 689#define DST_32BPP_AYUV444 0x0000000e 690#define DST_16BPP_ARGB4444 0x0000000f 691#define BRUSH_SOLIDCOLOR 0x00000d00 692#define SRC_MONO 0x00000000 693#define SRC_MONO_LBKGD 0x00010000 694#define SRC_DSTCOLOR 0x00030000 695#define BYTE_ORDER_MSB_TO_LSB 0x00000000 696#define BYTE_ORDER_LSB_TO_MSB 0x40000000 697#define DP_CONVERSION_TEMP 0x80000000 698#define HOST_BIG_ENDIAN_EN (1 << 29) 699 700 701/* DP_GUI_MASTER_CNTL bit constants */ 702#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 703#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 704#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 705#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 706#define GMC_SRC_CLIP_DEFAULT 0x00000000 707#define GMC_SRC_CLIP_LEAVE 0x00000004 708#define GMC_DST_CLIP_DEFAULT 0x00000000 709#define GMC_DST_CLIP_LEAVE 0x00000008 710#define GMC_BRUSH_8x8MONO 0x00000000 711#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 712#define GMC_BRUSH_8x1MONO 0x00000020 713#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 714#define GMC_BRUSH_1x8MONO 0x00000040 715#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 716#define GMC_BRUSH_32x1MONO 0x00000060 717#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 718#define GMC_BRUSH_32x32MONO 0x00000080 719#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 720#define GMC_BRUSH_8x8COLOR 0x000000a0 721#define GMC_BRUSH_8x1COLOR 0x000000b0 722#define GMC_BRUSH_1x8COLOR 0x000000c0 723#define GMC_BRUSH_SOLID_COLOR 0x000000d0 724#define GMC_DST_8BPP 0x00000200 725#define GMC_DST_15BPP 0x00000300 726#define GMC_DST_16BPP 0x00000400 727#define GMC_DST_24BPP 0x00000500 728#define GMC_DST_32BPP 0x00000600 729#define GMC_DST_8BPP_RGB332 0x00000700 730#define GMC_DST_8BPP_Y8 0x00000800 731#define GMC_DST_8BPP_RGB8 0x00000900 732#define GMC_DST_16BPP_VYUY422 0x00000b00 733#define GMC_DST_16BPP_YVYU422 0x00000c00 734#define GMC_DST_32BPP_AYUV444 0x00000e00 735#define GMC_DST_16BPP_ARGB4444 0x00000f00 736#define GMC_SRC_MONO 0x00000000 737#define GMC_SRC_MONO_LBKGD 0x00001000 738#define GMC_SRC_DSTCOLOR 0x00003000 739#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 740#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 741#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 742#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 743#define GMC_DP_SRC_RECT 0x02000000 744#define GMC_DP_SRC_HOST 0x03000000 745#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 746#define GMC_3D_FCN_EN_CLR 0x00000000 747#define GMC_3D_FCN_EN_SET 0x08000000 748#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 749#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 750#define GMC_AUX_CLIP_LEAVE 0x00000000 751#define GMC_AUX_CLIP_CLEAR 0x20000000 752#define GMC_WRITE_MASK_LEAVE 0x00000000 753#define GMC_WRITE_MASK_SET 0x40000000 754#define GMC_CLR_CMP_CNTL_DIS (1 << 28) 755#define GMC_SRC_DATATYPE_COLOR (3 << 12) 756#define ROP3_S 0x00cc0000 757#define ROP3_SRCCOPY 0x00cc0000 758#define ROP3_P 0x00f00000 759#define ROP3_PATCOPY 0x00f00000 760#define DP_SRC_SOURCE_MASK (7 << 24) 761#define GMC_BRUSH_NONE (15 << 4) 762#define DP_SRC_SOURCE_MEMORY (2 << 24) 763#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 764 765/* DP_MIX bit constants */ 766#define DP_SRC_RECT 0x00000200 767#define DP_SRC_HOST 0x00000300 768#define DP_SRC_HOST_BYTEALIGN 0x00000400 769 770/* MPLL_CNTL bit constants */ 771#define MPLL_RESET 0x00000001 772 773/* MDLL_CKO bit constants */ 774#define MDLL_CKO__MCKOA_RESET 0x00000002 775 776/* VCLK_ECP_CNTL constants */ 777#define PIXCLK_ALWAYS_ONb 0x00000040 778#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 779 780/* masks */ 781 782#define CONFIG_MEMSIZE_MASK 0x1f000000 783#define MEM_CFG_TYPE 0x40000000 784#define DST_OFFSET_MASK 0x003fffff 785#define DST_PITCH_MASK 0x3fc00000 786#define DEFAULT_TILE_MASK 0xc0000000 787#define PPLL_DIV_SEL_MASK 0x00000300 788#define PPLL_RESET 0x00000001 789#define PPLL_ATOMIC_UPDATE_EN 0x00010000 790#define PPLL_REF_DIV_MASK 0x000003ff 791#define PPLL_FB3_DIV_MASK 0x000007ff 792#define PPLL_POST3_DIV_MASK 0x00070000 793#define PPLL_ATOMIC_UPDATE_R 0x00008000 794#define PPLL_ATOMIC_UPDATE_W 0x00008000 795#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 796 797#define GUI_ACTIVE 0x80000000 798 799#endif /* _RADEON_H */ 800 801