1/* $Id: aty128fb.c,v 1.1.1.1 2008/10/15 03:27:04 james26_jang Exp $ 2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128 3 * 4 * Copyright (C) 1999-2000, Brad Douglas <brad@neruo.com> 5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu> 6 * 7 * Ani Joshi / Jeff Garzik 8 * - Code cleanup 9 * 10 * Michel D�nzer <michdaen@iiic.ethz.ch> 11 * - 15/16 bit cleanup 12 * - fix panning 13 * 14 * Benjamin Herrenschmidt 15 * - pmac-specific PM stuff 16 * 17 * Andreas Hundt <andi@convergence.de> 18 * - FB_ACTIVATE fixes 19 * 20 * Based off of Geert's atyfb.c and vfb.c. 21 * 22 * TODO: 23 * - monitor sensing (DDC) 24 * - virtual display 25 * - other platform support (only ppc/x86 supported) 26 * - hardware cursor support 27 * - ioctl()'s 28 * 29 * Please cc: your patches to brad@neruo.com. 30 */ 31 32/* 33 * A special note of gratitude to ATI's devrel for providing documentation, 34 * example code and hardware. Thanks Nitya. -atong and brad 35 */ 36 37 38#include <linux/config.h> 39#include <linux/module.h> 40#include <linux/kernel.h> 41#include <linux/errno.h> 42#include <linux/string.h> 43#include <linux/mm.h> 44#include <linux/tty.h> 45#include <linux/slab.h> 46#include <linux/vmalloc.h> 47#include <linux/delay.h> 48#include <linux/interrupt.h> 49#include <asm/uaccess.h> 50#include <linux/fb.h> 51#include <linux/init.h> 52#include <linux/selection.h> 53#include <linux/console.h> 54#include <linux/pci.h> 55#include <linux/ioport.h> 56#include <asm/io.h> 57 58#ifdef CONFIG_PPC 59#include <asm/prom.h> 60#include <asm/pci-bridge.h> 61#include <video/macmodes.h> 62#ifdef CONFIG_NVRAM 63#include <linux/nvram.h> 64#endif 65#endif 66 67#ifdef CONFIG_ADB_PMU 68#include <linux/adb.h> 69#include <linux/pmu.h> 70#endif 71 72#ifdef CONFIG_PMAC_BACKLIGHT 73#include <asm/backlight.h> 74#endif 75 76#ifdef CONFIG_FB_COMPAT_XPMAC 77#include <asm/vc_ioctl.h> 78#endif 79#ifdef CONFIG_BOOTX_TEXT 80#include <asm/btext.h> 81#endif /* CONFIG_BOOTX_TEXT */ 82 83#include <video/fbcon.h> 84#include <video/fbcon-cfb8.h> 85#include <video/fbcon-cfb16.h> 86#include <video/fbcon-cfb24.h> 87#include <video/fbcon-cfb32.h> 88 89#ifdef CONFIG_MTRR 90#include <asm/mtrr.h> 91#endif 92 93#include "aty128.h" 94 95/* Debug flag */ 96#undef DEBUG 97 98#ifdef DEBUG 99#define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args); 100#else 101#define DBG(fmt, args...) 102#endif 103 104#ifndef CONFIG_PPC 105/* default mode */ 106static struct fb_var_screeninfo default_var __initdata = { 107 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */ 108 640, 480, 640, 480, 0, 0, 8, 0, 109 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 110 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2, 111 0, FB_VMODE_NONINTERLACED 112}; 113 114#else /* CONFIG_PPC */ 115/* default to 1024x768 at 75Hz on PPC - this will work 116 * on the iMac, the usual 640x480 @ 60Hz doesn't. */ 117static struct fb_var_screeninfo default_var = { 118 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */ 119 1024, 768, 1024, 768, 0, 0, 8, 0, 120 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0}, 121 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3, 122 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED 123}; 124#endif /* CONFIG_PPC */ 125 126/* default modedb mode */ 127/* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */ 128static struct fb_videomode defaultmode __initdata = { 129 refresh: 60, 130 xres: 640, 131 yres: 480, 132 pixclock: 39722, 133 left_margin: 48, 134 right_margin: 16, 135 upper_margin: 33, 136 lower_margin: 10, 137 hsync_len: 96, 138 vsync_len: 2, 139 sync: 0, 140 vmode: FB_VMODE_NONINTERLACED 141}; 142 143/* struct to hold chip description information */ 144struct aty128_chip_info { 145 const char *name; 146 unsigned short device; 147 int chip_gen; 148}; 149 150/* Chip generations */ 151enum { 152 rage_128, 153 rage_128_pro, 154 rage_M3 155}; 156 157/* supported Rage128 chipsets */ 158static struct aty128_chip_info aty128_pci_probe_list[] __initdata = 159{ 160 {"Rage128 RE (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RE, rage_128}, 161 {"Rage128 RF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RF, rage_128}, 162 {"Rage128 RK (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RK, rage_128}, 163 {"Rage128 RL (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RL, rage_128}, 164 {"Rage128 Pro PF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_PF, rage_128_pro}, 165 {"Rage128 Pro PR (PCI)", PCI_DEVICE_ID_ATI_RAGE128_PR, rage_128_pro}, 166 {"Rage128 Pro TR (AGP)", PCI_DEVICE_ID_ATI_RAGE128_U3, rage_128_pro}, 167 {"Rage128 Pro TF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_U1, rage_128_pro}, 168 {"Rage Mobility M3 (PCI)", PCI_DEVICE_ID_ATI_RAGE128_LE, rage_M3}, 169 {"Rage Mobility M3 (AGP)", PCI_DEVICE_ID_ATI_RAGE128_LF, rage_M3}, 170 {NULL, 0, rage_128} 171 }; 172 173/* packed BIOS settings */ 174#ifndef CONFIG_PPC 175typedef struct { 176 u8 clock_chip_type; 177 u8 struct_size; 178 u8 accelerator_entry; 179 u8 VGA_entry; 180 u16 VGA_table_offset; 181 u16 POST_table_offset; 182 u16 XCLK; 183 u16 MCLK; 184 u8 num_PLL_blocks; 185 u8 size_PLL_blocks; 186 u16 PCLK_ref_freq; 187 u16 PCLK_ref_divider; 188 u32 PCLK_min_freq; 189 u32 PCLK_max_freq; 190 u16 MCLK_ref_freq; 191 u16 MCLK_ref_divider; 192 u32 MCLK_min_freq; 193 u32 MCLK_max_freq; 194 u16 XCLK_ref_freq; 195 u16 XCLK_ref_divider; 196 u32 XCLK_min_freq; 197 u32 XCLK_max_freq; 198} __attribute__ ((packed)) PLL_BLOCK; 199#endif /* !CONFIG_PPC */ 200 201/* onboard memory information */ 202struct aty128_meminfo { 203 u8 ML; 204 u8 MB; 205 u8 Trcd; 206 u8 Trp; 207 u8 Twr; 208 u8 CL; 209 u8 Tr2w; 210 u8 LoopLatency; 211 u8 DspOn; 212 u8 Rloop; 213 const char *name; 214}; 215 216/* various memory configurations */ 217static const struct aty128_meminfo sdr_128 = 218 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" }; 219static const struct aty128_meminfo sdr_64 = 220 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" }; 221static const struct aty128_meminfo sdr_sgram = 222 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" }; 223static const struct aty128_meminfo ddr_sgram = 224 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" }; 225 226static const char *aty128fb_name = "ATY Rage128"; 227static char fontname[40] __initdata = { 0 }; 228 229static int noaccel __initdata = 0; 230static char *font __initdata = NULL; 231static char *mode __initdata = NULL; 232static int nomtrr __initdata = 0; 233 234static char *mode_option __initdata = NULL; 235 236#ifdef CONFIG_PPC 237static int default_vmode __initdata = VMODE_1024_768_60; 238static int default_cmode __initdata = CMODE_8; 239#endif 240 241#ifdef CONFIG_PMAC_PBOOK 242static int default_crt_on __initdata = 0; 243static int default_lcd_on __initdata = 1; 244#endif 245 246#ifdef CONFIG_MTRR 247static int mtrr = 1; 248#endif 249 250/* PLL constants */ 251struct aty128_constants { 252 u32 dotclock; 253 u32 ppll_min; 254 u32 ppll_max; 255 u32 ref_divider; 256 u32 xclk; 257 u32 fifo_width; 258 u32 fifo_depth; 259}; 260 261struct aty128_crtc { 262 u32 gen_cntl; 263 u32 ext_cntl; 264 u32 h_total, h_sync_strt_wid; 265 u32 v_total, v_sync_strt_wid; 266 u32 pitch; 267 u32 offset, offset_cntl; 268 u32 xoffset, yoffset; 269 u32 vxres, vyres; 270 u32 depth, bpp; 271}; 272 273struct aty128_pll { 274 u32 post_divider; 275 u32 feedback_divider; 276 u32 vclk; 277}; 278 279struct aty128_ddafifo { 280 u32 dda_config; 281 u32 dda_on_off; 282}; 283 284/* register values for a specific mode */ 285struct aty128fb_par { 286 struct aty128_crtc crtc; 287 struct aty128_pll pll; 288 struct aty128_ddafifo fifo_reg; 289 u32 accel_flags; 290}; 291 292struct fb_info_aty128 { 293 struct fb_info fb_info; 294 struct fb_info_aty128 *next; 295 struct aty128_constants constants; /* PLL and others */ 296 unsigned long regbase_phys; /* physical mmio */ 297 void *regbase; /* remapped mmio */ 298 unsigned long frame_buffer_phys; /* physical fb memory */ 299 void *frame_buffer; /* remaped framebuffer */ 300 u32 vram_size; /* onboard video ram */ 301 int chip_gen; 302 const struct aty128_meminfo *mem; /* onboard mem info */ 303 struct aty128fb_par default_par, current_par; 304 struct display disp; 305 struct { u8 red, green, blue, pad; } palette[256]; 306 union { 307#ifdef FBCON_HAS_CFB16 308 u16 cfb16[16]; 309#endif 310#ifdef FBCON_HAS_CFB24 311 u32 cfb24[16]; 312#endif 313#ifdef FBCON_HAS_CFB32 314 u32 cfb32[16]; 315#endif 316 } fbcon_cmap; 317#ifdef CONFIG_PCI 318 struct pci_dev *pdev; 319#endif 320#ifdef CONFIG_MTRR 321 struct { int vram; int vram_valid; } mtrr; 322#endif 323 int currcon; 324 int blitter_may_be_busy; 325 int fifo_slots; /* free slots in FIFO (64 max) */ 326#ifdef CONFIG_PMAC_PBOOK 327 unsigned char *save_framebuffer; 328 int pm_reg; 329 int crt_on, lcd_on; 330 u32 save_lcd_gen_cntl; 331#endif 332}; 333 334static struct fb_info_aty128 *board_list = NULL; 335 336#ifdef CONFIG_PMAC_PBOOK 337 int aty128_sleep_notify(struct pmu_sleep_notifier *self, int when); 338 static struct pmu_sleep_notifier aty128_sleep_notifier = { 339 aty128_sleep_notify, SLEEP_LEVEL_VIDEO, 340 }; 341#endif 342 343#define round_div(n, d) ((n+(d/2))/d) 344 345 /* 346 * Interface used by the world 347 */ 348 349int aty128fb_setup(char *options); 350 351static int aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con, 352 struct fb_info *info); 353static int aty128fb_get_var(struct fb_var_screeninfo *var, int con, 354 struct fb_info *info); 355static int aty128fb_set_var(struct fb_var_screeninfo *var, int con, 356 struct fb_info *info); 357static int aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con, 358 struct fb_info *info); 359static int aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con, 360 struct fb_info *info); 361static int aty128fb_pan_display(struct fb_var_screeninfo *var, int con, 362 struct fb_info *fb); 363static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd, 364 u_long arg, int con, struct fb_info *info); 365static int aty128fb_rasterimg(struct fb_info *info, int start); 366 367 368 /* 369 * Interface to the low level console driver 370 */ 371 372int aty128fb_init(void); 373static int aty128fbcon_switch(int con, struct fb_info *fb); 374static void aty128fbcon_blank(int blank, struct fb_info *fb); 375 376 /* 377 * Internal routines 378 */ 379 380static void aty128_encode_fix(struct fb_fix_screeninfo *fix, 381 struct aty128fb_par *par, 382 const struct fb_info_aty128 *info); 383static void aty128_set_dispsw(struct display *disp, 384 struct fb_info_aty128 *info, int bpp, int accel); 385static int aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue, 386 u_int *transp, struct fb_info *info); 387static int aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 388 u_int transp, struct fb_info *info); 389static void do_install_cmap(int con, struct fb_info *info); 390static int aty128_encode_var(struct fb_var_screeninfo *var, 391 const struct aty128fb_par *par, 392 const struct fb_info_aty128 *info); 393static int aty128_decode_var(struct fb_var_screeninfo *var, 394 struct aty128fb_par *par, 395 const struct fb_info_aty128 *info); 396static int aty128_pci_register(struct pci_dev *pdev, 397 const struct aty128_chip_info *aci); 398static struct fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128 399 *board_list, struct fb_info_aty128 *new_node); 400#if !defined(CONFIG_PPC) && !defined(__sparc__) 401static void __init aty128_get_pllinfo(struct fb_info_aty128 *info, 402 char *bios_seg); 403static char __init *aty128find_ROM(struct fb_info_aty128 *info); 404#endif 405static void aty128_timings(struct fb_info_aty128 *info); 406static void aty128_init_engine(const struct aty128fb_par *par, 407 struct fb_info_aty128 *info); 408static void aty128_reset_engine(const struct fb_info_aty128 *info); 409static void aty128_flush_pixel_cache(const struct fb_info_aty128 *info); 410static void do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info); 411static void wait_for_fifo(u16 entries, struct fb_info_aty128 *info); 412static void wait_for_idle(struct fb_info_aty128 *info); 413static u32 depth_to_dst(u32 depth); 414 415#ifdef FBCON_HAS_CFB8 416static struct display_switch fbcon_aty128_8; 417static void fbcon_aty8_putc(struct vc_data *conp, struct display *p, 418 int c, int yy, int xx); 419static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p, 420 const unsigned short *s, int count, 421 int yy, int xx); 422#endif 423#ifdef FBCON_HAS_CFB16 424static struct display_switch fbcon_aty128_16; 425static void fbcon_aty16_putc(struct vc_data *conp, struct display *p, 426 int c, int yy, int xx); 427static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p, 428 const unsigned short *s, int count, 429 int yy, int xx); 430#endif 431#ifdef FBCON_HAS_CFB24 432static struct display_switch fbcon_aty128_24; 433static void fbcon_aty24_putc(struct vc_data *conp, struct display *p, 434 int c, int yy, int xx); 435static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p, 436 const unsigned short *s, int count, 437 int yy, int xx); 438#endif 439#ifdef FBCON_HAS_CFB32 440static struct display_switch fbcon_aty128_32; 441static void fbcon_aty32_putc(struct vc_data *conp, struct display *p, 442 int c, int yy, int xx); 443static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p, 444 const unsigned short *s, int count, 445 int yy, int xx); 446#endif 447 448static struct fb_ops aty128fb_ops = { 449 owner: THIS_MODULE, 450 fb_get_fix: aty128fb_get_fix, 451 fb_get_var: aty128fb_get_var, 452 fb_set_var: aty128fb_set_var, 453 fb_get_cmap: aty128fb_get_cmap, 454 fb_set_cmap: aty128fb_set_cmap, 455 fb_pan_display: aty128fb_pan_display, 456 fb_ioctl: aty128fb_ioctl, 457 fb_rasterimg: aty128fb_rasterimg, 458}; 459 460#ifdef CONFIG_PMAC_BACKLIGHT 461static int aty128_set_backlight_enable(int on, int level, void* data); 462static int aty128_set_backlight_level(int level, void* data); 463 464static struct backlight_controller aty128_backlight_controller = { 465 aty128_set_backlight_enable, 466 aty128_set_backlight_level 467}; 468#endif /* CONFIG_PMAC_BACKLIGHT */ 469 470 /* 471 * Functions to read from/write to the mmio registers 472 * - endian conversions may possibly be avoided by 473 * using the other register aperture. TODO. 474 */ 475static inline u32 476_aty_ld_le32(volatile unsigned int regindex, 477 const struct fb_info_aty128 *info) 478{ 479 u32 val; 480 481#if defined(__powerpc__) 482 asm("lwbrx %0,%1,%2;eieio" : "=r"(val) : "b"(regindex), "r"(info->regbase)); 483#else 484 val = readl (info->regbase + regindex); 485#endif 486 487 return val; 488} 489 490static inline void 491_aty_st_le32(volatile unsigned int regindex, u32 val, 492 const struct fb_info_aty128 *info) 493{ 494#if defined(__powerpc__) 495 asm("stwbrx %0,%1,%2;eieio" : : "r"(val), "b"(regindex), 496 "r"(info->regbase) : "memory"); 497#else 498 writel (val, info->regbase + regindex); 499#endif 500} 501 502static inline u8 503_aty_ld_8(unsigned int regindex, const struct fb_info_aty128 *info) 504{ 505 return readb (info->regbase + regindex); 506} 507 508static inline void 509_aty_st_8(unsigned int regindex, u8 val, const struct fb_info_aty128 *info) 510{ 511 writeb (val, info->regbase + regindex); 512} 513 514#define aty_ld_le32(regindex) _aty_ld_le32(regindex, info) 515#define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, info) 516#define aty_ld_8(regindex) _aty_ld_8(regindex, info) 517#define aty_st_8(regindex, val) _aty_st_8(regindex, val, info) 518 519 /* 520 * Functions to read from/write to the pll registers 521 */ 522 523#define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, info) 524#define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, info) 525 526 527static u32 528_aty_ld_pll(unsigned int pll_index, 529 const struct fb_info_aty128 *info) 530{ 531 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F); 532 return aty_ld_le32(CLOCK_CNTL_DATA); 533} 534 535 536static void 537_aty_st_pll(unsigned int pll_index, u32 val, 538 const struct fb_info_aty128 *info) 539{ 540 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN); 541 aty_st_le32(CLOCK_CNTL_DATA, val); 542} 543 544 545/* return true when the PLL has completed an atomic update */ 546static int 547aty_pll_readupdate(const struct fb_info_aty128 *info) 548{ 549 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); 550} 551 552 553static void 554aty_pll_wait_readupdate(const struct fb_info_aty128 *info) 555{ 556 unsigned long timeout = jiffies + HZ/100; // should be more than enough 557 int reset = 1; 558 559 while (time_before(jiffies, timeout)) 560 if (aty_pll_readupdate(info)) { 561 reset = 0; 562 break; 563 } 564 565 if (reset) /* reset engine?? */ 566 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n"); 567} 568 569 570/* tell PLL to update */ 571static void 572aty_pll_writeupdate(const struct fb_info_aty128 *info) 573{ 574 aty_pll_wait_readupdate(info); 575 576 aty_st_pll(PPLL_REF_DIV, 577 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W); 578} 579 580 581/* write to the scratch register to test r/w functionality */ 582static int __init 583register_test(const struct fb_info_aty128 *info) 584{ 585 u32 val; 586 int flag = 0; 587 588 val = aty_ld_le32(BIOS_0_SCRATCH); 589 590 aty_st_le32(BIOS_0_SCRATCH, 0x55555555); 591 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) { 592 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA); 593 594 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA) 595 flag = 1; 596 } 597 598 aty_st_le32(BIOS_0_SCRATCH, val); // restore value 599 return flag; 600} 601 602 603 /* 604 * Accelerator engine functions 605 */ 606static void 607do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info) 608{ 609 int i; 610 611 for (;;) { 612 for (i = 0; i < 2000000; i++) { 613 info->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff; 614 if (info->fifo_slots >= entries) 615 return; 616 } 617 aty128_reset_engine(info); 618 } 619} 620 621 622static void 623wait_for_idle(struct fb_info_aty128 *info) 624{ 625 int i; 626 627 do_wait_for_fifo(64, info); 628 629 for (;;) { 630 for (i = 0; i < 2000000; i++) { 631 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) { 632 aty128_flush_pixel_cache(info); 633 info->blitter_may_be_busy = 0; 634 return; 635 } 636 } 637 aty128_reset_engine(info); 638 } 639} 640 641 642static void 643wait_for_fifo(u16 entries, struct fb_info_aty128 *info) 644{ 645 if (info->fifo_slots < entries) 646 do_wait_for_fifo(64, info); 647 info->fifo_slots -= entries; 648} 649 650 651static void 652aty128_flush_pixel_cache(const struct fb_info_aty128 *info) 653{ 654 int i; 655 u32 tmp; 656 657 tmp = aty_ld_le32(PC_NGUI_CTLSTAT); 658 tmp &= ~(0x00ff); 659 tmp |= 0x00ff; 660 aty_st_le32(PC_NGUI_CTLSTAT, tmp); 661 662 for (i = 0; i < 2000000; i++) 663 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY)) 664 break; 665} 666 667 668static void 669aty128_reset_engine(const struct fb_info_aty128 *info) 670{ 671 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl; 672 673 aty128_flush_pixel_cache(info); 674 675 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX); 676 mclk_cntl = aty_ld_pll(MCLK_CNTL); 677 678 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000); 679 680 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL); 681 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); 682 aty_ld_le32(GEN_RESET_CNTL); 683 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI)); 684 aty_ld_le32(GEN_RESET_CNTL); 685 686 aty_st_pll(MCLK_CNTL, mclk_cntl); 687 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index); 688 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl); 689 690 /* use old pio mode */ 691 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4); 692 693 DBG("engine reset"); 694} 695 696 697static void 698aty128_init_engine(const struct aty128fb_par *par, 699 struct fb_info_aty128 *info) 700{ 701 u32 pitch_value; 702 703 wait_for_idle(info); 704 705 /* 3D scaler not spoken here */ 706 wait_for_fifo(1, info); 707 aty_st_le32(SCALE_3D_CNTL, 0x00000000); 708 709 aty128_reset_engine(info); 710 711 pitch_value = par->crtc.pitch; 712 if (par->crtc.bpp == 24) { 713 pitch_value = pitch_value * 3; 714 } 715 716 wait_for_fifo(4, info); 717 /* setup engine offset registers */ 718 aty_st_le32(DEFAULT_OFFSET, 0x00000000); 719 720 /* setup engine pitch registers */ 721 aty_st_le32(DEFAULT_PITCH, pitch_value); 722 723 /* set the default scissor register to max dimensions */ 724 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF); 725 726 /* set the drawing controls registers */ 727 aty_st_le32(DP_GUI_MASTER_CNTL, 728 GMC_SRC_PITCH_OFFSET_DEFAULT | 729 GMC_DST_PITCH_OFFSET_DEFAULT | 730 GMC_SRC_CLIP_DEFAULT | 731 GMC_DST_CLIP_DEFAULT | 732 GMC_BRUSH_SOLIDCOLOR | 733 (depth_to_dst(par->crtc.depth) << 8) | 734 GMC_SRC_DSTCOLOR | 735 GMC_BYTE_ORDER_MSB_TO_LSB | 736 GMC_DP_CONVERSION_TEMP_6500 | 737 ROP3_PATCOPY | 738 GMC_DP_SRC_RECT | 739 GMC_3D_FCN_EN_CLR | 740 GMC_DST_CLR_CMP_FCN_CLEAR | 741 GMC_AUX_CLIP_CLEAR | 742 GMC_WRITE_MASK_SET); 743 744 wait_for_fifo(8, info); 745 /* clear the line drawing registers */ 746 aty_st_le32(DST_BRES_ERR, 0); 747 aty_st_le32(DST_BRES_INC, 0); 748 aty_st_le32(DST_BRES_DEC, 0); 749 750 /* set brush color registers */ 751 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */ 752 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */ 753 754 /* set source color registers */ 755 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */ 756 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */ 757 758 /* default write mask */ 759 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF); 760 761 /* Wait for all the writes to be completed before returning */ 762 wait_for_idle(info); 763} 764 765 766/* convert depth values to their register representation */ 767static u32 768depth_to_dst(u32 depth) 769 { 770 if (depth <= 8) 771 return DST_8BPP; 772 else if (depth <= 15) 773 return DST_15BPP; 774 else if (depth == 16) 775 return DST_16BPP; 776 else if (depth <= 24) 777 return DST_24BPP; 778 else if (depth <= 32) 779 return DST_32BPP; 780 781 return -EINVAL; 782} 783 784 785 /* 786 * CRTC programming 787 */ 788 789/* Program the CRTC registers */ 790static void 791aty128_set_crtc(const struct aty128_crtc *crtc, 792 const struct fb_info_aty128 *info) 793{ 794 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl); 795 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total); 796 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid); 797 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total); 798 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); 799 aty_st_le32(CRTC_PITCH, crtc->pitch); 800 aty_st_le32(CRTC_OFFSET, crtc->offset); 801 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl); 802 /* Disable ATOMIC updating. Is this the right place? */ 803 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); 804} 805 806 807static int 808aty128_var_to_crtc(const struct fb_var_screeninfo *var, 809 struct aty128_crtc *crtc, 810 const struct fb_info_aty128 *info) 811{ 812 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; 813 u32 left, right, upper, lower, hslen, vslen, sync, vmode; 814 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol; 815 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 816 u32 depth, bytpp; 817 u8 hsync_strt_pix[5] = { 0, 0x12, 9, 6, 5 }; 818 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 }; 819 820 /* input */ 821 xres = var->xres; 822 yres = var->yres; 823 vxres = var->xres_virtual; 824 vyres = var->yres_virtual; 825 xoffset = var->xoffset; 826 yoffset = var->yoffset; 827 bpp = var->bits_per_pixel; 828 left = var->left_margin; 829 right = var->right_margin; 830 upper = var->upper_margin; 831 lower = var->lower_margin; 832 hslen = var->hsync_len; 833 vslen = var->vsync_len; 834 sync = var->sync; 835 vmode = var->vmode; 836 837 if (bpp != 16) 838 depth = bpp; 839 else 840 depth = (var->green.length == 6) ? 16 : 15; 841 842 /* check for mode eligibility 843 * accept only non interlaced modes */ 844 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED) 845 return -EINVAL; 846 847 /* convert (and round up) and validate */ 848 xres = (xres + 7) & ~7; 849 xoffset = (xoffset + 7) & ~7; 850 851 if (vxres < xres + xoffset) 852 vxres = xres + xoffset; 853 854 if (vyres < yres + yoffset) 855 vyres = yres + yoffset; 856 857 /* convert depth into ATI register depth */ 858 dst = depth_to_dst(depth); 859 860 if (dst == -EINVAL) { 861 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n"); 862 return -EINVAL; 863 } 864 865 /* convert register depth to bytes per pixel */ 866 bytpp = mode_bytpp[dst]; 867 868 /* make sure there is enough video ram for the mode */ 869 if ((u32)(vxres * vyres * bytpp) > info->vram_size) { 870 printk(KERN_ERR "aty128fb: Not enough memory for mode\n"); 871 return -EINVAL; 872 } 873 874 h_disp = (xres >> 3) - 1; 875 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL; 876 877 v_disp = yres - 1; 878 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL; 879 880 /* check to make sure h_total and v_total are in range */ 881 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) { 882 printk(KERN_ERR "aty128fb: invalid width ranges\n"); 883 return -EINVAL; 884 } 885 886 h_sync_wid = (hslen + 7) >> 3; 887 if (h_sync_wid == 0) 888 h_sync_wid = 1; 889 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */ 890 h_sync_wid = 0x3f; 891 892 h_sync_strt = h_disp + (right >> 3); 893 894 v_sync_wid = vslen; 895 if (v_sync_wid == 0) 896 v_sync_wid = 1; 897 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */ 898 v_sync_wid = 0x1f; 899 900 v_sync_strt = v_disp + lower; 901 902 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1; 903 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1; 904 905 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0; 906 907 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8); 908 909 crtc->h_total = h_total | (h_disp << 16); 910 crtc->v_total = v_total | (v_disp << 16); 911 912 crtc->h_sync_strt_wid = hsync_strt_pix[bytpp] | (h_sync_strt << 3) | 913 (h_sync_wid << 16) | (h_sync_pol << 23); 914 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) | 915 (v_sync_pol << 23); 916 917 crtc->pitch = vxres >> 3; 918 919 crtc->offset = 0; 920 921 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) 922 crtc->offset_cntl = 0x00010000; 923 else 924 crtc->offset_cntl = 0; 925 926 crtc->vxres = vxres; 927 crtc->vyres = vyres; 928 crtc->xoffset = xoffset; 929 crtc->yoffset = yoffset; 930 crtc->depth = depth; 931 crtc->bpp = bpp; 932 933 return 0; 934} 935 936 937static int 938aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var) 939{ 940 941 /* fill in pixel info */ 942 switch (pix_width) { 943 case CRTC_PIX_WIDTH_8BPP: 944 var->bits_per_pixel = 8; 945 var->red.offset = 0; 946 var->red.length = 8; 947 var->green.offset = 0; 948 var->green.length = 8; 949 var->blue.offset = 0; 950 var->blue.length = 8; 951 var->transp.offset = 0; 952 var->transp.length = 0; 953 break; 954 case CRTC_PIX_WIDTH_15BPP: 955 var->bits_per_pixel = 16; 956 var->red.offset = 10; 957 var->red.length = 5; 958 var->green.offset = 5; 959 var->green.length = 5; 960 var->blue.offset = 0; 961 var->blue.length = 5; 962 var->transp.offset = 0; 963 var->transp.length = 0; 964 break; 965 case CRTC_PIX_WIDTH_16BPP: 966 var->bits_per_pixel = 16; 967 var->red.offset = 11; 968 var->red.length = 5; 969 var->green.offset = 5; 970 var->green.length = 6; 971 var->blue.offset = 0; 972 var->blue.length = 5; 973 var->transp.offset = 0; 974 var->transp.length = 0; 975 break; 976 case CRTC_PIX_WIDTH_24BPP: 977 var->bits_per_pixel = 24; 978 var->red.offset = 16; 979 var->red.length = 8; 980 var->green.offset = 8; 981 var->green.length = 8; 982 var->blue.offset = 0; 983 var->blue.length = 8; 984 var->transp.offset = 0; 985 var->transp.length = 0; 986 break; 987 case CRTC_PIX_WIDTH_32BPP: 988 var->bits_per_pixel = 32; 989 var->red.offset = 16; 990 var->red.length = 8; 991 var->green.offset = 8; 992 var->green.length = 8; 993 var->blue.offset = 0; 994 var->blue.length = 8; 995 var->transp.offset = 24; 996 var->transp.length = 8; 997 break; 998 default: 999 printk(KERN_ERR "aty128fb: Invalid pixel width\n"); 1000 return -EINVAL; 1001 } 1002 1003 return 0; 1004} 1005 1006 1007static int 1008aty128_crtc_to_var(const struct aty128_crtc *crtc, 1009 struct fb_var_screeninfo *var) 1010{ 1011 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync; 1012 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol; 1013 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync; 1014 u32 pix_width; 1015 1016 /* fun with masking */ 1017 h_total = crtc->h_total & 0x1ff; 1018 h_disp = (crtc->h_total >> 16) & 0xff; 1019 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff; 1020 h_sync_dly = crtc->h_sync_strt_wid & 0x7; 1021 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f; 1022 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1; 1023 v_total = crtc->v_total & 0x7ff; 1024 v_disp = (crtc->v_total >> 16) & 0x7ff; 1025 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff; 1026 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f; 1027 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1; 1028 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0; 1029 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK; 1030 1031 /* do conversions */ 1032 xres = (h_disp + 1) << 3; 1033 yres = v_disp + 1; 1034 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly; 1035 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly; 1036 hslen = h_sync_wid << 3; 1037 upper = v_total - v_sync_strt - v_sync_wid; 1038 lower = v_sync_strt - v_disp; 1039 vslen = v_sync_wid; 1040 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) | 1041 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) | 1042 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0); 1043 1044 aty128_pix_width_to_var(pix_width, var); 1045 1046 var->xres = xres; 1047 var->yres = yres; 1048 var->xres_virtual = crtc->vxres; 1049 var->yres_virtual = crtc->vyres; 1050 var->xoffset = crtc->xoffset; 1051 var->yoffset = crtc->yoffset; 1052 var->left_margin = left; 1053 var->right_margin = right; 1054 var->upper_margin = upper; 1055 var->lower_margin = lower; 1056 var->hsync_len = hslen; 1057 var->vsync_len = vslen; 1058 var->sync = sync; 1059 var->vmode = FB_VMODE_NONINTERLACED; 1060 1061 return 0; 1062} 1063 1064static void 1065aty128_set_crt_enable(struct fb_info_aty128 *info, int on) 1066{ 1067 if (on) { 1068 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON); 1069 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN)); 1070 } else 1071 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON); 1072} 1073 1074static void 1075aty128_set_lcd_enable(struct fb_info_aty128 *info, int on) 1076{ 1077 u32 reg; 1078 1079 if (on) { 1080 reg = aty_ld_le32(LVDS_GEN_CNTL); 1081 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION; 1082 reg &= ~LVDS_DISPLAY_DIS; 1083 aty_st_le32(LVDS_GEN_CNTL, reg); 1084#ifdef CONFIG_PMAC_BACKLIGHT 1085 aty128_set_backlight_enable(get_backlight_enable(), get_backlight_level(), info); 1086#endif 1087 } else { 1088#ifdef CONFIG_PMAC_BACKLIGHT 1089 aty128_set_backlight_enable(0, 0, info); 1090#endif 1091 reg = aty_ld_le32(LVDS_GEN_CNTL); 1092 reg |= LVDS_DISPLAY_DIS; 1093 aty_st_le32(LVDS_GEN_CNTL, reg); 1094 mdelay(100); 1095 reg &= ~(LVDS_ON /*| LVDS_EN*/); 1096 aty_st_le32(LVDS_GEN_CNTL, reg); 1097 } 1098} 1099 1100static void 1101aty128_set_pll(struct aty128_pll *pll, const struct fb_info_aty128 *info) 1102{ 1103 u32 div3; 1104 1105 unsigned char post_conv[] = /* register values for post dividers */ 1106 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; 1107 1108 /* select PPLL_DIV_3 */ 1109 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8)); 1110 1111 /* reset PLL */ 1112 aty_st_pll(PPLL_CNTL, 1113 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); 1114 1115 /* write the reference divider */ 1116 aty_pll_wait_readupdate(info); 1117 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider & 0x3ff); 1118 aty_pll_writeupdate(info); 1119 1120 div3 = aty_ld_pll(PPLL_DIV_3); 1121 div3 &= ~PPLL_FB3_DIV_MASK; 1122 div3 |= pll->feedback_divider; 1123 div3 &= ~PPLL_POST3_DIV_MASK; 1124 div3 |= post_conv[pll->post_divider] << 16; 1125 1126 /* write feedback and post dividers */ 1127 aty_pll_wait_readupdate(info); 1128 aty_st_pll(PPLL_DIV_3, div3); 1129 aty_pll_writeupdate(info); 1130 1131 aty_pll_wait_readupdate(info); 1132 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ 1133 aty_pll_writeupdate(info); 1134 1135 /* clear the reset, just in case */ 1136 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); 1137 1138} 1139 1140 1141static int 1142aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, 1143 const struct fb_info_aty128 *info) 1144{ 1145 const struct aty128_constants c = info->constants; 1146 unsigned char post_dividers[] = {1,2,4,8,3,6,12}; 1147 u32 output_freq; 1148 u32 vclk; /* in .01 MHz */ 1149 int i; 1150 u32 n, d; 1151 1152 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */ 1153 1154 /* adjust pixel clock if necessary */ 1155 if (vclk > c.ppll_max) 1156 vclk = c.ppll_max; 1157 if (vclk * 12 < c.ppll_min) 1158 vclk = c.ppll_min/12; 1159 1160 /* now, find an acceptable divider */ 1161 for (i = 0; i < sizeof(post_dividers); i++) { 1162 output_freq = post_dividers[i] * vclk; 1163 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) 1164 break; 1165 } 1166 1167 /* calculate feedback divider */ 1168 n = c.ref_divider * output_freq; 1169 d = c.dotclock; 1170 1171 pll->post_divider = post_dividers[i]; 1172 pll->feedback_divider = round_div(n, d); 1173 pll->vclk = vclk; 1174 1175 DBG("post %d feedback %d vlck %d output %d ref_divider %d " 1176 "vclk_per: %d\n", pll->post_divider, 1177 pll->feedback_divider, vclk, output_freq, 1178 c.ref_divider, period_in_ps); 1179 1180 return 0; 1181} 1182 1183 1184static int 1185aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var, 1186 const struct fb_info_aty128 *info) 1187{ 1188 var->pixclock = 100000000 / pll->vclk; 1189 1190 return 0; 1191} 1192 1193 1194static void 1195aty128_set_fifo(const struct aty128_ddafifo *dsp, 1196 const struct fb_info_aty128 *info) 1197{ 1198 aty_st_le32(DDA_CONFIG, dsp->dda_config); 1199 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); 1200} 1201 1202 1203static int 1204aty128_ddafifo(struct aty128_ddafifo *dsp, 1205 const struct aty128_pll *pll, 1206 u32 depth, 1207 const struct fb_info_aty128 *info) 1208{ 1209 const struct aty128_meminfo *m = info->mem; 1210 u32 xclk = info->constants.xclk; 1211 u32 fifo_width = info->constants.fifo_width; 1212 u32 fifo_depth = info->constants.fifo_depth; 1213 s32 x, b, p, ron, roff; 1214 u32 n, d, bpp; 1215 1216 /* round up to multiple of 8 */ 1217 bpp = (depth+7) & ~7; 1218 1219 n = xclk * fifo_width; 1220 d = pll->vclk * bpp; 1221 x = round_div(n, d); 1222 1223 ron = 4 * m->MB + 1224 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) + 1225 2 * m->Trp + 1226 m->Twr + 1227 m->CL + 1228 m->Tr2w + 1229 x; 1230 1231 DBG("x %x\n", x); 1232 1233 b = 0; 1234 while (x) { 1235 x >>= 1; 1236 b++; 1237 } 1238 p = b + 1; 1239 1240 ron <<= (11 - p); 1241 1242 n <<= (11 - p); 1243 x = round_div(n, d); 1244 roff = x * (fifo_depth - 4); 1245 1246 if ((ron + m->Rloop) >= roff) { 1247 printk(KERN_ERR "aty128fb: Mode out of range!\n"); 1248 return -EINVAL; 1249 } 1250 1251 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n", 1252 p, m->Rloop, x, ron, roff); 1253 1254 dsp->dda_config = p << 16 | m->Rloop << 20 | x; 1255 dsp->dda_on_off = ron << 16 | roff; 1256 1257 return 0; 1258} 1259 1260 1261/* 1262 * This actually sets the video mode. 1263 */ 1264static void 1265aty128_set_par(struct aty128fb_par *par, 1266 struct fb_info_aty128 *info) 1267{ 1268 u32 config; 1269 1270 info->current_par = *par; 1271 1272 if (info->blitter_may_be_busy) 1273 wait_for_idle(info); 1274 1275 /* clear all registers that may interfere with mode setting */ 1276 aty_st_le32(OVR_CLR, 0); 1277 aty_st_le32(OVR_WID_LEFT_RIGHT, 0); 1278 aty_st_le32(OVR_WID_TOP_BOTTOM, 0); 1279 aty_st_le32(OV0_SCALE_CNTL, 0); 1280 aty_st_le32(MPP_TB_CONFIG, 0); 1281 aty_st_le32(MPP_GP_CONFIG, 0); 1282 aty_st_le32(SUBPIC_CNTL, 0); 1283 aty_st_le32(VIPH_CONTROL, 0); 1284 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */ 1285 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */ 1286 aty_st_le32(CAP0_TRIG_CNTL, 0); 1287 aty_st_le32(CAP1_TRIG_CNTL, 0); 1288 1289 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */ 1290 1291 aty128_set_crtc(&par->crtc, info); 1292 aty128_set_pll(&par->pll, info); 1293 aty128_set_fifo(&par->fifo_reg, info); 1294 1295 config = aty_ld_le32(CONFIG_CNTL) & ~3; 1296 1297#if defined(__BIG_ENDIAN) 1298 if (par->crtc.bpp == 32) 1299 config |= 2; /* make aperture do 32 bit swapping */ 1300 else if (par->crtc.bpp == 16) 1301 config |= 1; /* make aperture do 16 bit swapping */ 1302#endif 1303 1304 aty_st_le32(CONFIG_CNTL, config); 1305 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */ 1306 1307#ifdef CONFIG_PMAC_PBOOK 1308 if (info->chip_gen == rage_M3) { 1309 aty128_set_crt_enable(info, info->crt_on); 1310 aty128_set_lcd_enable(info, info->lcd_on); 1311 } 1312#endif 1313 if (par->accel_flags & FB_ACCELF_TEXT) 1314 aty128_init_engine(par, info); 1315 1316#ifdef CONFIG_FB_COMPAT_XPMAC 1317 if (!console_fb_info || console_fb_info == &info->fb_info) { 1318 struct fb_var_screeninfo var; 1319 int cmode, vmode; 1320 1321 display_info.height = ((par->crtc.v_total >> 16) & 0x7ff) + 1; 1322 display_info.width = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; 1323 display_info.depth = par->crtc.bpp; 1324 display_info.pitch = (par->crtc.vxres * par->crtc.bpp) >> 3; 1325 aty128_encode_var(&var, par, info); 1326 if (mac_var_to_vmode(&var, &vmode, &cmode)) 1327 display_info.mode = 0; 1328 else 1329 display_info.mode = vmode; 1330 strcpy(display_info.name, aty128fb_name); 1331 display_info.fb_address = info->frame_buffer_phys; 1332 display_info.cmap_adr_address = 0; 1333 display_info.cmap_data_address = 0; 1334 display_info.disp_reg_address = info->regbase_phys; 1335 } 1336#endif /* CONFIG_FB_COMPAT_XPMAC */ 1337#if defined(CONFIG_BOOTX_TEXT) 1338 btext_update_display(info->frame_buffer_phys, 1339 (((par->crtc.h_total>>16) & 0xff)+1)*8, 1340 ((par->crtc.v_total>>16) & 0x7ff)+1, 1341 par->crtc.bpp, 1342 par->crtc.vxres*par->crtc.bpp/8); 1343#endif /* CONFIG_BOOTX_TEXT */ 1344} 1345 1346 /* 1347 * encode/decode the User Defined Part of the Display 1348 */ 1349 1350static int 1351aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par, 1352 const struct fb_info_aty128 *info) 1353{ 1354 int err; 1355 1356 if ((err = aty128_var_to_crtc(var, &par->crtc, info))) 1357 return err; 1358 1359 if ((err = aty128_var_to_pll(var->pixclock, &par->pll, info))) 1360 return err; 1361 1362 if ((err = aty128_ddafifo(&par->fifo_reg, &par->pll, par->crtc.depth, info))) 1363 return err; 1364 1365 if (var->accel_flags & FB_ACCELF_TEXT) 1366 par->accel_flags = FB_ACCELF_TEXT; 1367 else 1368 par->accel_flags = 0; 1369 1370 return 0; 1371} 1372 1373 1374static int 1375aty128_encode_var(struct fb_var_screeninfo *var, 1376 const struct aty128fb_par *par, 1377 const struct fb_info_aty128 *info) 1378{ 1379 int err; 1380 1381 if ((err = aty128_crtc_to_var(&par->crtc, var))) 1382 return err; 1383 1384 if ((err = aty128_pll_to_var(&par->pll, var, info))) 1385 return err; 1386 1387 var->red.msb_right = 0; 1388 var->green.msb_right = 0; 1389 var->blue.msb_right = 0; 1390 var->transp.msb_right = 0; 1391 1392 var->nonstd = 0; 1393 var->activate = 0; 1394 1395 var->height = -1; 1396 var->width = -1; 1397 var->accel_flags = par->accel_flags; 1398 1399 return 0; 1400} 1401 1402 1403 /* 1404 * Get the User Defined Part of the Display 1405 */ 1406 1407static int 1408aty128fb_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb) 1409{ 1410 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb; 1411 1412 if (con == -1) 1413 aty128_encode_var(var, &info->default_par, info); 1414 else 1415 *var = fb_display[con].var; 1416 return 0; 1417} 1418 1419 1420 /* 1421 * Set the User Defined Part of the Display 1422 */ 1423 1424static int 1425aty128fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb) 1426{ 1427 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb; 1428 struct aty128fb_par par; 1429 struct display *display; 1430 int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldgreen, oldaccel; 1431 int accel, err; 1432 1433 display = (con >= 0) ? &fb_display[con] : fb->disp; 1434 1435 /* basic (in)sanity checks */ 1436 if (!var->xres) 1437 var->xres = 1; 1438 if (!var->yres) 1439 var->yres = 1; 1440 if (var->xres > var->xres_virtual) 1441 var->xres_virtual = var->xres; 1442 if (var->yres > var->yres_virtual) 1443 var->yres_virtual = var->yres; 1444 1445 switch (var->bits_per_pixel) { 1446 case 0 ... 8: 1447 var->bits_per_pixel = 8; 1448 break; 1449 case 9 ... 16: 1450 var->bits_per_pixel = 16; 1451 break; 1452 case 17 ... 24: 1453 var->bits_per_pixel = 24; 1454 break; 1455 case 25 ... 32: 1456 var->bits_per_pixel = 32; 1457 break; 1458 default: 1459 return -EINVAL; 1460 } 1461 1462 if ((err = aty128_decode_var(var, &par, info))) 1463 return err; 1464 1465 aty128_encode_var(var, &par, info); 1466 1467 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_TEST) 1468 return 0; 1469 1470 oldxres = display->var.xres; 1471 oldyres = display->var.yres; 1472 oldvxres = display->var.xres_virtual; 1473 oldvyres = display->var.yres_virtual; 1474 oldbpp = display->var.bits_per_pixel; 1475 oldgreen = display->var.green.length; 1476 oldaccel = display->var.accel_flags; 1477 display->var = *var; 1478 if (oldxres != var->xres || oldyres != var->yres || 1479 oldvxres != var->xres_virtual || oldvyres != var->yres_virtual || 1480 oldgreen != var->green.length || oldbpp != var->bits_per_pixel || 1481 oldaccel != var->accel_flags) { 1482 1483 struct fb_fix_screeninfo fix; 1484 1485 aty128_encode_fix(&fix, &par, info); 1486 display->screen_base = info->frame_buffer; 1487 display->visual = fix.visual; 1488 display->type = fix.type; 1489 display->type_aux = fix.type_aux; 1490 display->ypanstep = fix.ypanstep; 1491 display->ywrapstep = fix.ywrapstep; 1492 display->line_length = fix.line_length; 1493 display->can_soft_blank = 1; 1494 display->inverse = 0; 1495 1496 accel = var->accel_flags & FB_ACCELF_TEXT; 1497 aty128_set_dispsw(display, info, par.crtc.bpp, accel); 1498 1499 if (accel) 1500 display->scrollmode = SCROLL_YNOMOVE; 1501 else 1502 display->scrollmode = SCROLL_YREDRAW; 1503 1504 if (info->fb_info.changevar) 1505 (*info->fb_info.changevar)(con); 1506 } 1507 1508 if (!info->fb_info.display_fg || info->fb_info.display_fg->vc_num == con) 1509 aty128_set_par(&par, info); 1510 1511 if (oldbpp != var->bits_per_pixel || oldgreen != var->green.length) { 1512 if ((err = fb_alloc_cmap(&display->cmap, 0, 0))) 1513 return err; 1514 do_install_cmap(con, &info->fb_info); 1515 } 1516 1517 return 0; 1518} 1519 1520 1521static void 1522aty128_set_dispsw(struct display *disp, 1523 struct fb_info_aty128 *info, int bpp, int accel) 1524{ 1525 switch (bpp) { 1526#ifdef FBCON_HAS_CFB8 1527 case 8: 1528 disp->dispsw = accel ? &fbcon_aty128_8 : &fbcon_cfb8; 1529 break; 1530#endif 1531#ifdef FBCON_HAS_CFB16 1532 case 16: 1533 disp->dispsw = accel ? &fbcon_aty128_16 : &fbcon_cfb16; 1534 disp->dispsw_data = info->fbcon_cmap.cfb16; 1535 break; 1536#endif 1537#ifdef FBCON_HAS_CFB24 1538 case 24: 1539 disp->dispsw = accel ? &fbcon_aty128_24 : &fbcon_cfb24; 1540 disp->dispsw_data = info->fbcon_cmap.cfb24; 1541 break; 1542#endif 1543#ifdef FBCON_HAS_CFB32 1544 case 32: 1545 disp->dispsw = accel ? &fbcon_aty128_32 : &fbcon_cfb32; 1546 disp->dispsw_data = info->fbcon_cmap.cfb32; 1547 break; 1548#endif 1549 default: 1550 disp->dispsw = &fbcon_dummy; 1551 } 1552} 1553 1554 1555static void 1556aty128_encode_fix(struct fb_fix_screeninfo *fix, 1557 struct aty128fb_par *par, 1558 const struct fb_info_aty128 *info) 1559{ 1560 memset(fix, 0, sizeof(struct fb_fix_screeninfo)); 1561 1562 strcpy(fix->id, aty128fb_name); 1563 1564 fix->smem_start = (unsigned long)info->frame_buffer_phys; 1565 fix->mmio_start = (unsigned long)info->regbase_phys; 1566 1567 fix->smem_len = info->vram_size; 1568 fix->mmio_len = 0x1fff; 1569 1570 fix->type = FB_TYPE_PACKED_PIXELS; 1571 fix->type_aux = 0; 1572 fix->line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; 1573 fix->visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR 1574 : FB_VISUAL_DIRECTCOLOR; 1575 fix->ywrapstep = 0; 1576 fix->xpanstep = 8; 1577 fix->ypanstep = 1; 1578 1579 fix->accel = FB_ACCEL_ATI_RAGE128; 1580 1581 return; 1582} 1583 1584 1585 /* 1586 * Get the Fixed Part of the Display 1587 */ 1588static int 1589aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *fb) 1590{ 1591 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb; 1592 struct aty128fb_par par; 1593 1594 if (con == -1) 1595 par = info->default_par; 1596 else 1597 aty128_decode_var(&fb_display[con].var, &par, info); 1598 1599 aty128_encode_fix(fix, &par, info); 1600 1601 return 0; 1602} 1603 1604 1605 /* 1606 * Pan or Wrap the Display 1607 */ 1608static int 1609aty128fb_pan_display(struct fb_var_screeninfo *var, int con, 1610 struct fb_info *fb) 1611{ 1612 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb; 1613 struct aty128fb_par *par = &info->current_par; 1614 u32 xoffset, yoffset; 1615 u32 offset; 1616 u32 xres, yres; 1617 1618 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3; 1619 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1; 1620 1621 xoffset = (var->xoffset +7) & ~7; 1622 yoffset = var->yoffset; 1623 1624 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres) 1625 return -EINVAL; 1626 1627 par->crtc.xoffset = xoffset; 1628 par->crtc.yoffset = yoffset; 1629 1630 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7; 1631 1632 if (par->crtc.bpp == 24) 1633 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */ 1634 1635 aty_st_le32(CRTC_OFFSET, offset); 1636 1637 return 0; 1638} 1639 1640 1641 /* 1642 * Get the Colormap 1643 */ 1644 1645static int 1646aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con, 1647 struct fb_info *info) 1648{ 1649 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info; 1650 struct display *disp = (con < 0) ? info->disp : (fb_display + con); 1651 1652 if (con == fb->currcon) /* current console? */ 1653 return fb_get_cmap(cmap, kspc, aty128_getcolreg, info); 1654 else if (disp->cmap.len) /* non default colormap? */ 1655 fb_copy_cmap(&disp->cmap, cmap, kspc ? 0 : 2); 1656 else 1657 fb_copy_cmap(fb_default_cmap((disp->var.bits_per_pixel==8) ? 256 : 32), 1658 cmap, kspc ? 0 : 2); 1659 1660 return 0; 1661} 1662 1663 /* 1664 * Set the Colormap 1665 */ 1666 1667static int 1668aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con, 1669 struct fb_info *info) 1670{ 1671 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info; 1672 struct display *disp = (con < 0) ? info->disp : (fb_display + con); 1673 unsigned int cmap_len = (disp->var.bits_per_pixel==8) ? 256 : 32; 1674 1675 if (disp->cmap.len != cmap_len) { 1676 int err = fb_alloc_cmap(&disp->cmap, cmap_len, 0); 1677 1678 if (!disp->cmap.len) { /* no colormap allocated? */ 1679 int size = (disp->var.bits_per_pixel <= 8) ? 256 : 32; 1680 if ((err = fb_alloc_cmap(&disp->cmap, size, 0))) 1681 return err; 1682 } 1683 if (err) return err; 1684 } 1685 1686 if (con == fb->currcon) /* current console? */ 1687 return fb_set_cmap(cmap, kspc, aty128_setcolreg, info); 1688 else 1689 fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1); 1690 1691 return 0; 1692} 1693 1694 /* 1695 * Helper function to store a single palette register 1696 */ 1697static __inline__ void 1698aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue, 1699 struct fb_info_aty128 *info) 1700{ 1701 /* Note: For now, on M3, we set palette on both heads, which may 1702 * be useless. Can someone with a M3 check this ? 1703 * 1704 * This code would still be useful if using the second CRTC to 1705 * do mirroring 1706 */ 1707 1708 if (info->chip_gen == rage_M3) { 1709 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL); 1710 } 1711 aty_st_8(PALETTE_INDEX, regno); 1712 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue); 1713} 1714 1715static int 1716aty128fb_rasterimg(struct fb_info *info, int start) 1717{ 1718 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info; 1719 1720 if (fb->blitter_may_be_busy) 1721 wait_for_idle(fb); 1722 1723 return 0; 1724} 1725 1726 1727int __init 1728aty128fb_setup(char *options) 1729{ 1730 char *this_opt; 1731 1732 if (!options || !*options) 1733 return 0; 1734 1735 while ((this_opt = strsep(&options, ",")) != 0) { 1736 if (!strncmp(this_opt, "font:", 5)) { 1737 char *p; 1738 int i; 1739 1740 p = this_opt +5; 1741 for (i = 0; i < sizeof(fontname) - 1; i++) 1742 if (!*p || *p == ' ' || *p == ',') 1743 break; 1744 memcpy(fontname, this_opt + 5, i); 1745 fontname[i] = 0; 1746 } else if (!strncmp(this_opt, "noaccel", 7)) { 1747 noaccel = 1; 1748#ifdef CONFIG_PMAC_PBOOK 1749 } else if (!strncmp(this_opt, "lcd:", 4)) { 1750 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0); 1751 } else if (!strncmp(this_opt, "crt:", 4)) { 1752 default_crt_on = simple_strtoul(this_opt+4, NULL, 0); 1753#endif 1754 } 1755#ifdef CONFIG_MTRR 1756 else if(!strncmp(this_opt, "nomtrr", 6)) { 1757 mtrr = 0; 1758 } 1759#endif 1760#ifdef CONFIG_PPC 1761 /* vmode and cmode depreciated */ 1762 else if (!strncmp(this_opt, "vmode:", 6)) { 1763 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0); 1764 if (vmode > 0 && vmode <= VMODE_MAX) 1765 default_vmode = vmode; 1766 } else if (!strncmp(this_opt, "cmode:", 6)) { 1767 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0); 1768 switch (cmode) { 1769 case 0: 1770 case 8: 1771 default_cmode = CMODE_8; 1772 break; 1773 case 15: 1774 case 16: 1775 default_cmode = CMODE_16; 1776 break; 1777 case 24: 1778 case 32: 1779 default_cmode = CMODE_32; 1780 break; 1781 } 1782 } 1783#endif /* CONFIG_PPC */ 1784 else 1785 mode_option = this_opt; 1786 } 1787 return 0; 1788} 1789 1790 1791 /* 1792 * Initialisation 1793 */ 1794 1795static int __init 1796aty128_init(struct fb_info_aty128 *info, const char *name) 1797{ 1798 struct fb_var_screeninfo var; 1799 u32 dac; 1800 int j, k; 1801 u8 chip_rev; 1802 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0]; 1803 char *video_card = "Rage128"; 1804 1805 if (!info->vram_size) /* may have already been probed */ 1806 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF; 1807 1808 /* Get the chip revision */ 1809 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F; 1810 1811 /* put a name with the face */ 1812 while (aci->name && info->pdev->device != aci->device) { aci++; } 1813 video_card = (char *)aci->name; 1814 info->chip_gen = aci->chip_gen; 1815 1816 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev); 1817 1818 if (info->vram_size % (1024 * 1024) == 0) 1819 printk("%dM %s\n", info->vram_size / (1024*1024), info->mem->name); 1820 else 1821 printk("%dk %s\n", info->vram_size / 1024, info->mem->name); 1822 1823 /* fill in info */ 1824 strcpy(info->fb_info.modename, aty128fb_name); 1825 info->fb_info.node = -1; 1826 info->fb_info.fbops = &aty128fb_ops; 1827 info->fb_info.disp = &info->disp; 1828 strcpy(info->fb_info.fontname, fontname); 1829 info->fb_info.changevar = NULL; 1830 info->fb_info.switch_con = &aty128fbcon_switch; 1831 info->fb_info.updatevar = NULL; 1832 info->fb_info.blank = &aty128fbcon_blank; 1833 info->fb_info.flags = FBINFO_FLAG_DEFAULT; 1834#ifdef CONFIG_PMAC_PBOOK 1835 info->lcd_on = default_lcd_on; 1836 info->crt_on = default_crt_on; 1837#endif 1838 1839 var = default_var; 1840#ifdef CONFIG_PPC 1841 if (_machine == _MACH_Pmac) { 1842 if (mode_option) { 1843 if (!mac_find_mode(&var, &info->fb_info, mode_option, 8)) 1844 var = default_var; 1845 } else { 1846 if (default_vmode <= 0 || default_vmode > VMODE_MAX) 1847 default_vmode = VMODE_1024_768_60; 1848 1849 /* iMacs need that resolution 1850 * PowerMac2,1 first r128 iMacs 1851 * PowerMac2,2 summer 2000 iMacs 1852 * PowerMac4,1 january 2001 iMacs "flower power" 1853 */ 1854 if (machine_is_compatible("PowerMac2,1") || 1855 machine_is_compatible("PowerMac2,2") || 1856 machine_is_compatible("PowerMac4,1")) 1857 default_vmode = VMODE_1024_768_75; 1858 1859 /* iBook SE */ 1860 if (machine_is_compatible("PowerBook2,2")) 1861 default_vmode = VMODE_800_600_60; 1862 1863 /* PowerBook Firewire (Pismo), iBook Dual USB */ 1864 if (machine_is_compatible("PowerBook3,1") || 1865 machine_is_compatible("PowerBook4,1")) 1866 default_vmode = VMODE_1024_768_60; 1867 1868 /* PowerBook Titanium */ 1869 if (machine_is_compatible("PowerBook3,2")) 1870 default_vmode = VMODE_1152_768_60; 1871 1872 if (default_cmode < CMODE_8 || default_cmode > CMODE_32) 1873 default_cmode = CMODE_8; 1874 1875 if (mac_vmode_to_var(default_vmode, default_cmode, &var)) 1876 var = default_var; 1877 } 1878 } else 1879#endif /* CONFIG_PPC */ 1880 { 1881 if (fb_find_mode(&var, &info->fb_info, mode_option, NULL, 0, 1882 &defaultmode, 8) == 0) 1883 var = default_var; 1884 } 1885 1886 if (noaccel) 1887 var.accel_flags &= ~FB_ACCELF_TEXT; 1888 else 1889 var.accel_flags |= FB_ACCELF_TEXT; 1890 1891 if (aty128_decode_var(&var, &info->default_par, info)) { 1892 printk(KERN_ERR "aty128fb: Cannot set default mode.\n"); 1893 return 0; 1894 } 1895 1896 /* load up the palette with default colors */ 1897 for (j = 0; j < 16; j++) { 1898 k = color_table[j]; 1899 info->palette[j].red = default_red[k]; 1900 info->palette[j].green = default_grn[k]; 1901 info->palette[j].blue = default_blu[k]; 1902 } 1903 1904 /* setup the DAC the way we like it */ 1905 dac = aty_ld_le32(DAC_CNTL); 1906 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL); 1907 dac |= DAC_MASK; 1908 if (info->chip_gen == rage_M3) 1909 dac |= DAC_PALETTE2_SNOOP_EN; 1910 aty_st_le32(DAC_CNTL, dac); 1911 1912 /* turn off bus mastering, just in case */ 1913 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS); 1914 1915 aty128fb_set_var(&var, -1, &info->fb_info); 1916 aty128_init_engine(&info->default_par, info); 1917 1918 board_list = aty128_board_list_add(board_list, info); 1919 1920 if (register_framebuffer(&info->fb_info) < 0) 1921 return 0; 1922 1923#ifdef CONFIG_PMAC_BACKLIGHT 1924 /* Could be extended to Rage128Pro LVDS output too */ 1925 if (info->chip_gen == rage_M3) 1926 register_backlight_controller(&aty128_backlight_controller, info, "ati"); 1927#endif /* CONFIG_PMAC_BACKLIGHT */ 1928#ifdef CONFIG_PMAC_PBOOK 1929 if (!info->pdev) 1930 printk(KERN_WARNING "aty128fb: Not a PCI card, can't enable power management\n"); 1931 else { 1932 info->pm_reg = pci_find_capability(info->pdev, PCI_CAP_ID_PM); 1933 pmu_register_sleep_notifier(&aty128_sleep_notifier); 1934 } 1935#endif 1936 1937 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n", 1938 GET_FB_IDX(info->fb_info.node), aty128fb_name, name); 1939 1940 return 1; /* success! */ 1941} 1942 1943 1944/* add a new card to the list ++ajoshi */ 1945static struct 1946fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128 *board_list, 1947 struct fb_info_aty128 *new_node) 1948{ 1949 struct fb_info_aty128 *i_p = board_list; 1950 1951 new_node->next = NULL; 1952 if(board_list == NULL) 1953 return new_node; 1954 while(i_p->next != NULL) 1955 i_p = i_p->next; 1956 i_p->next = new_node; 1957 1958 return board_list; 1959} 1960 1961 1962int __init 1963aty128fb_init(void) 1964{ 1965#ifdef CONFIG_PCI 1966 struct pci_dev *pdev = NULL; 1967 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0]; 1968 1969 while (aci->name != NULL) { 1970 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev); 1971 while (pdev != NULL) { 1972 if (aty128_pci_register(pdev, aci) == 0) 1973 return 0; 1974 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev); 1975 } 1976 aci++; 1977 } 1978#endif 1979 1980 return 0; 1981} 1982 1983 1984#ifdef CONFIG_PCI 1985/* register a card ++ajoshi */ 1986static int __init 1987aty128_pci_register(struct pci_dev *pdev, 1988 const struct aty128_chip_info *aci) 1989{ 1990 struct fb_info_aty128 *info = NULL; 1991 unsigned long fb_addr, reg_addr; 1992 int err; 1993#if !defined(CONFIG_PPC) && !defined(__sparc__) 1994 char *bios_seg = NULL; 1995#endif 1996 1997 /* Enable device in PCI config */ 1998 if ((err = pci_enable_device(pdev))) { 1999 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n", 2000 err); 2001 return -ENODEV; 2002 } 2003 2004 fb_addr = pci_resource_start(pdev, 0); 2005 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0), 2006 "aty128fb FB")) { 2007 printk(KERN_ERR "aty128fb: cannot reserve frame " 2008 "buffer memory\n"); 2009 goto err_free_fb; 2010 } 2011 2012 reg_addr = pci_resource_start(pdev, 2); 2013 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2), 2014 "aty128fb MMIO")) { 2015 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n"); 2016 goto err_free_mmio; 2017 } 2018 2019 /* We have the resources. Now virtualize them */ 2020 if (!(info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC))) { 2021 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n"); 2022 goto err_unmap_out; 2023 } 2024 memset(info, 0, sizeof(struct fb_info_aty128)); 2025 2026 /* Copy PCI device info into info->pdev */ 2027 info->pdev = pdev; 2028 2029 info->currcon = -1; 2030 2031 /* Virtualize mmio region */ 2032 info->regbase_phys = reg_addr; 2033 info->regbase = ioremap(reg_addr, 0x1FFF); 2034 2035 if (!info->regbase) 2036 goto err_free_info; 2037 2038 /* Grab memory size from the card */ 2039 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF; 2040 2041 /* Virtualize the framebuffer */ 2042 info->frame_buffer_phys = fb_addr; 2043 info->frame_buffer = ioremap(fb_addr, info->vram_size); 2044 2045 if (!info->frame_buffer) { 2046 iounmap((void *)info->regbase); 2047 goto err_free_info; 2048 } 2049 2050 /* If we can't test scratch registers, something is seriously wrong */ 2051 if (!register_test(info)) { 2052 printk(KERN_ERR "aty128fb: Can't write to video register!\n"); 2053 goto err_out; 2054 } 2055 2056#if !defined(CONFIG_PPC) && !defined(__sparc__) 2057 if (!(bios_seg = aty128find_ROM(info))) 2058 printk(KERN_INFO "aty128fb: Rage128 BIOS not located. " 2059 "Guessing...\n"); 2060 else { 2061 printk(KERN_INFO "aty128fb: Rage128 BIOS located at " 2062 "segment %4.4lX\n", (unsigned long)bios_seg); 2063 aty128_get_pllinfo(info, bios_seg); 2064 } 2065#endif 2066 aty128_timings(info); 2067 2068 if (!aty128_init(info, "PCI")) 2069 goto err_out; 2070 2071#ifdef CONFIG_MTRR 2072 if (mtrr) { 2073 info->mtrr.vram = mtrr_add(info->frame_buffer_phys, 2074 info->vram_size, MTRR_TYPE_WRCOMB, 1); 2075 info->mtrr.vram_valid = 1; 2076 /* let there be speed */ 2077 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n"); 2078 } 2079#endif /* CONFIG_MTRR */ 2080 2081#ifdef CONFIG_FB_COMPAT_XPMAC 2082 if (!console_fb_info) 2083 console_fb_info = &info->fb_info; 2084#endif 2085 2086 return 0; 2087 2088err_out: 2089 iounmap(info->frame_buffer); 2090 iounmap(info->regbase); 2091err_free_info: 2092 kfree(info); 2093err_unmap_out: 2094 release_mem_region(pci_resource_start(pdev, 2), 2095 pci_resource_len(pdev, 2)); 2096err_free_mmio: 2097 release_mem_region(pci_resource_start(pdev, 0), 2098 pci_resource_len(pdev, 0)); 2099err_free_fb: 2100 release_mem_region(pci_resource_start(pdev, 1), 2101 pci_resource_len(pdev, 1)); 2102 return -ENODEV; 2103} 2104#endif /* CONFIG_PCI */ 2105 2106 2107/* PPC and Sparc cannot read video ROM */ 2108#if !defined(CONFIG_PPC) && !defined(__sparc__) 2109static char __init 2110*aty128find_ROM(struct fb_info_aty128 *info) 2111{ 2112 u32 segstart; 2113 char *rom_base; 2114 char *rom; 2115 int stage; 2116 int i; 2117 char aty_rom_sig[] = "761295520"; /* ATI ROM Signature */ 2118 char R128_sig[] = "R128"; /* Rage128 ROM identifier */ 2119 2120 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) { 2121 stage = 1; 2122 2123 rom_base = (char *)ioremap(segstart, 0x1000); 2124 2125 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa)) 2126 stage = 2; 2127 2128 if (stage != 2) { 2129 iounmap(rom_base); 2130 continue; 2131 } 2132 rom = rom_base; 2133 2134 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) { 2135 if (aty_rom_sig[0] == *rom) 2136 if (strncmp(aty_rom_sig, rom, 2137 strlen(aty_rom_sig)) == 0) 2138 stage = 3; 2139 rom++; 2140 } 2141 if (stage != 3) { 2142 iounmap(rom_base); 2143 continue; 2144 } 2145 rom = rom_base; 2146 2147 /* ATI signature found. Let's see if it's a Rage128 */ 2148 for (i = 0; (i < 512) && (stage != 4); i++) { 2149 if (R128_sig[0] == *rom) 2150 if (strncmp(R128_sig, rom, 2151 strlen(R128_sig)) == 0) 2152 stage = 4; 2153 rom++; 2154 } 2155 if (stage != 4) { 2156 iounmap(rom_base); 2157 continue; 2158 } 2159 2160 return rom_base; 2161 } 2162 2163 return NULL; 2164} 2165 2166 2167static void __init 2168aty128_get_pllinfo(struct fb_info_aty128 *info, char *bios_seg) 2169{ 2170 void *bios_header; 2171 void *header_ptr; 2172 u16 bios_header_offset, pll_info_offset; 2173 PLL_BLOCK pll; 2174 2175 bios_header = bios_seg + 0x48L; 2176 header_ptr = bios_header; 2177 2178 bios_header_offset = readw(header_ptr); 2179 bios_header = bios_seg + bios_header_offset; 2180 bios_header += 0x30; 2181 2182 header_ptr = bios_header; 2183 pll_info_offset = readw(header_ptr); 2184 header_ptr = bios_seg + pll_info_offset; 2185 2186 memcpy_fromio(&pll, header_ptr, 50); 2187 2188 info->constants.ppll_max = pll.PCLK_max_freq; 2189 info->constants.ppll_min = pll.PCLK_min_freq; 2190 info->constants.xclk = (u32)pll.XCLK; 2191 info->constants.ref_divider = (u32)pll.PCLK_ref_divider; 2192 info->constants.dotclock = (u32)pll.PCLK_ref_freq; 2193 2194 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d dotclock %d\n", 2195 info->constants.ppll_max, info->constants.ppll_min, 2196 info->constants.xclk, info->constants.ref_divider, 2197 info->constants.dotclock); 2198 2199} 2200#endif /* !CONFIG_PPC */ 2201 2202 2203/* fill in known card constants if pll_block is not available */ 2204static void __init 2205aty128_timings(struct fb_info_aty128 *info) 2206{ 2207#ifdef CONFIG_PPC 2208 /* instead of a table lookup, assume OF has properly 2209 * setup the PLL registers and use their values 2210 * to set the XCLK values and reference divider values */ 2211 2212 u32 x_mpll_ref_fb_div; 2213 u32 xclk_cntl; 2214 u32 Nx, M; 2215 unsigned PostDivSet[] = 2216 { 0, 1, 2, 4, 8, 3, 6, 12 }; 2217#endif 2218 2219 if (!info->constants.dotclock) 2220 info->constants.dotclock = 2950; 2221 2222#ifdef CONFIG_PPC 2223 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV); 2224 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7; 2225 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8; 2226 M = x_mpll_ref_fb_div & 0x0000ff; 2227 2228 info->constants.xclk = round_div((2 * Nx * 2229 info->constants.dotclock), (M * PostDivSet[xclk_cntl])); 2230 2231 info->constants.ref_divider = 2232 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; 2233#endif 2234 2235 if (!info->constants.ref_divider) { 2236 info->constants.ref_divider = 0x3b; 2237 2238 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e); 2239 aty_pll_writeupdate(info); 2240 } 2241 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider); 2242 aty_pll_writeupdate(info); 2243 2244 /* from documentation */ 2245 if (!info->constants.ppll_min) 2246 info->constants.ppll_min = 12500; 2247 if (!info->constants.ppll_max) 2248 info->constants.ppll_max = 25000; /* 23000 on some cards? */ 2249 if (!info->constants.xclk) 2250 info->constants.xclk = 0x1d4d; /* same as mclk */ 2251 2252 info->constants.fifo_width = 128; 2253 info->constants.fifo_depth = 32; 2254 2255 switch (aty_ld_le32(MEM_CNTL) & 0x3) { 2256 case 0: 2257 info->mem = &sdr_128; 2258 break; 2259 case 1: 2260 info->mem = &sdr_sgram; 2261 break; 2262 case 2: 2263 info->mem = &ddr_sgram; 2264 break; 2265 default: 2266 info->mem = &sdr_sgram; 2267 } 2268} 2269 2270 2271static int 2272aty128fbcon_switch(int con, struct fb_info *fb) 2273{ 2274 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb; 2275 struct aty128fb_par par; 2276 2277 /* Do we have to save the colormap? */ 2278 if (fb_display[info->currcon].cmap.len) 2279 fb_get_cmap(&fb_display[info->currcon].cmap, 1, 2280 aty128_getcolreg, fb); 2281 2282 /* set the current console */ 2283 info->currcon = con; 2284 2285 aty128_decode_var(&fb_display[con].var, &par, info); 2286 aty128_set_par(&par, info); 2287 2288 aty128_set_dispsw(&fb_display[con], info, par.crtc.bpp, 2289 par.accel_flags & FB_ACCELF_TEXT); 2290 2291 do_install_cmap(con, fb); 2292 2293 return 1; 2294} 2295 2296 2297 /* 2298 * Blank the display. 2299 */ 2300static void 2301aty128fbcon_blank(int blank, struct fb_info *fb) 2302{ 2303 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb; 2304 u8 state = 0; 2305 2306#ifdef CONFIG_PMAC_BACKLIGHT 2307 if ((_machine == _MACH_Pmac) && blank) 2308 set_backlight_enable(0); 2309#endif /* CONFIG_PMAC_BACKLIGHT */ 2310 2311 if (blank & VESA_VSYNC_SUSPEND) 2312 state |= 2; 2313 if (blank & VESA_HSYNC_SUSPEND) 2314 state |= 1; 2315 if (blank & VESA_POWERDOWN) 2316 state |= 4; 2317 2318 aty_st_8(CRTC_EXT_CNTL+1, state); 2319 2320#ifdef CONFIG_PMAC_PBOOK 2321 if (info->chip_gen == rage_M3) { 2322 aty128_set_crt_enable(info, info->crt_on && !blank); 2323 aty128_set_lcd_enable(info, info->lcd_on && !blank); 2324 } 2325#endif 2326#ifdef CONFIG_PMAC_BACKLIGHT 2327 if ((_machine == _MACH_Pmac) && !blank) 2328 set_backlight_enable(1); 2329#endif /* CONFIG_PMAC_BACKLIGHT */ 2330} 2331 2332 2333 /* 2334 * Read a single color register and split it into 2335 * colors/transparent. Return != 0 for invalid regno. 2336 */ 2337static int 2338aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue, 2339 u_int *transp, struct fb_info *fb) 2340{ 2341 struct fb_info_aty128 *info = (struct fb_info_aty128 *) fb; 2342 2343 if (regno > 255) 2344 return 1; 2345 2346 *red = (info->palette[regno].red<<8) | info->palette[regno].red; 2347 *green = (info->palette[regno].green<<8) | info->palette[regno].green; 2348 *blue = (info->palette[regno].blue<<8) | info->palette[regno].blue; 2349 *transp = 0; 2350 2351 return 0; 2352} 2353 2354 /* 2355 * Set a single color register. The values supplied are already 2356 * rounded down to the hardware's capabilities (according to the 2357 * entries in the var structure). Return != 0 for invalid regno. 2358 */ 2359static int 2360aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue, 2361 u_int transp, struct fb_info *fb) 2362{ 2363 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb; 2364 u32 palreg; 2365 2366 if (regno > 255) 2367 return 1; 2368 2369 red >>= 8; 2370 green >>= 8; 2371 blue >>= 8; 2372 info->palette[regno].red = red; 2373 info->palette[regno].green = green; 2374 info->palette[regno].blue = blue; 2375 2376 /* Note: For now, on M3, we set palette on both heads, which may 2377 * be useless. Can someone with a M3 check this ? */ 2378 2379 /* initialize gamma ramp for hi-color+ */ 2380 2381 if ((info->current_par.crtc.bpp > 8) && (regno == 0)) { 2382 int i; 2383 2384 for (i=0; i<256; i++) 2385 aty128_st_pal(i, i, i, i, info); 2386 } 2387 2388 /* initialize palette */ 2389 2390 palreg = regno; 2391 2392 if (info->current_par.crtc.bpp == 16) 2393 palreg = regno * 8; 2394 2395 if (info->current_par.crtc.depth == 16) { 2396 aty128_st_pal(palreg/2, info->palette[regno/2].red, green, 2397 info->palette[regno/2].blue, info); 2398 green = info->palette[regno*2].green; 2399 } 2400 2401 if (info->current_par.crtc.bpp == 8 || regno < 32) 2402 aty128_st_pal(palreg, red, green, blue, info); 2403 2404 if (regno < 16) 2405 switch (info->current_par.crtc.depth) { 2406#ifdef FBCON_HAS_CFB16 2407 case 15: 2408 info->fbcon_cmap.cfb16[regno] = (regno << 10) | (regno << 5) | 2409 regno; 2410 break; 2411 case 16: 2412 info->fbcon_cmap.cfb16[regno] = (regno << 11) | (regno << 5) | 2413 regno; 2414 break; 2415#endif 2416#ifdef FBCON_HAS_CFB24 2417 case 24: 2418 info->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | 2419 regno; 2420 break; 2421#endif 2422#ifdef FBCON_HAS_CFB32 2423 case 32: { 2424 u32 i = (regno << 8) | regno; 2425 info->fbcon_cmap.cfb32[regno] = (i << 16) | i; 2426 break; 2427 } 2428#endif 2429 } 2430 return 0; 2431} 2432 2433 2434static void 2435do_install_cmap(int con, struct fb_info *info) 2436{ 2437 struct display *disp = (con < 0) ? info->disp : (fb_display + con); 2438 2439 if (disp->cmap.len) 2440 fb_set_cmap(&disp->cmap, 1, aty128_setcolreg, info); 2441 else 2442 fb_set_cmap(fb_default_cmap((disp->var.bits_per_pixel==8) ? 256 :32), 2443 1, aty128_setcolreg, info); 2444} 2445 2446#define ATY_MIRROR_LCD_ON 0x00000001 2447#define ATY_MIRROR_CRT_ON 0x00000002 2448 2449/* out param: u32* backlight value: 0 to 15 */ 2450#define FBIO_ATY128_GET_MIRROR _IOR('@', 1, sizeof(__u32*)) 2451/* in param: u32* backlight value: 0 to 15 */ 2452#define FBIO_ATY128_SET_MIRROR _IOW('@', 2, sizeof(__u32*)) 2453 2454static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd, 2455 u_long arg, int con, struct fb_info *info) 2456{ 2457 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info; 2458 u32 value; 2459 int rc; 2460 2461 switch (cmd) { 2462#ifdef CONFIG_PMAC_PBOOK 2463 case FBIO_ATY128_SET_MIRROR: 2464 if (fb->chip_gen != rage_M3) 2465 return -EINVAL; 2466 rc = get_user(value, (__u32*)arg); 2467 if (rc) 2468 return rc; 2469 fb->lcd_on = (value & 0x01) != 0; 2470 fb->crt_on = (value & 0x02) != 0; 2471 if (!fb->crt_on && !fb->lcd_on) 2472 fb->lcd_on = 1; 2473 aty128_set_crt_enable(fb, fb->crt_on); 2474 aty128_set_lcd_enable(fb, fb->lcd_on); 2475 break; 2476 case FBIO_ATY128_GET_MIRROR: 2477 if (fb->chip_gen != rage_M3) 2478 return -EINVAL; 2479 value = (fb->crt_on << 1) | fb->lcd_on; 2480 return put_user(value, (__u32*)arg); 2481#endif 2482 default: 2483 return -EINVAL; 2484 } 2485 return 0; 2486} 2487 2488#ifdef CONFIG_PMAC_BACKLIGHT 2489static int backlight_conv[] = { 2490 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e, 2491 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24 2492}; 2493 2494/* We turn off the LCD completely instead of just dimming the backlight. 2495 * This provides greater power saving and the display is useless without 2496 * backlight anyway 2497 */ 2498#define BACKLIGHT_LVDS_OFF 2499/* That one prevents proper CRT output with LCD off */ 2500#undef BACKLIGHT_DAC_OFF 2501 2502static int 2503aty128_set_backlight_enable(int on, int level, void* data) 2504{ 2505 struct fb_info_aty128 *info = (struct fb_info_aty128 *)data; 2506 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL); 2507 2508 if (!info->lcd_on) 2509 on = 0; 2510 reg |= LVDS_BL_MOD_EN | LVDS_BLON; 2511 if (on && level > BACKLIGHT_OFF) { 2512 reg |= LVDS_DIGION; 2513 if (!reg & LVDS_ON) { 2514 reg &= ~LVDS_BLON; 2515 aty_st_le32(LVDS_GEN_CNTL, reg); 2516 (void)aty_ld_le32(LVDS_GEN_CNTL); 2517 mdelay(10); 2518 reg |= LVDS_BLON; 2519 aty_st_le32(LVDS_GEN_CNTL, reg); 2520 } 2521 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 2522 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT); 2523#ifdef BACKLIGHT_LVDS_OFF 2524 reg |= LVDS_ON | LVDS_EN; 2525 reg &= ~LVDS_DISPLAY_DIS; 2526#endif 2527 aty_st_le32(LVDS_GEN_CNTL, reg); 2528#ifdef BACKLIGHT_DAC_OFF 2529 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN)); 2530#endif 2531 } else { 2532 reg &= ~LVDS_BL_MOD_LEVEL_MASK; 2533 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT); 2534#ifdef BACKLIGHT_LVDS_OFF 2535 reg |= LVDS_DISPLAY_DIS; 2536 aty_st_le32(LVDS_GEN_CNTL, reg); 2537 (void)aty_ld_le32(LVDS_GEN_CNTL); 2538 udelay(10); 2539 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION); 2540#endif 2541 aty_st_le32(LVDS_GEN_CNTL, reg); 2542#ifdef BACKLIGHT_DAC_OFF 2543 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN); 2544#endif 2545 } 2546 2547 return 0; 2548} 2549 2550static int 2551aty128_set_backlight_level(int level, void* data) 2552{ 2553 return aty128_set_backlight_enable(1, level, data); 2554} 2555#endif /* CONFIG_PMAC_BACKLIGHT */ 2556 2557 /* 2558 * Accelerated functions 2559 */ 2560 2561static inline void 2562aty128_rectcopy(int srcx, int srcy, int dstx, int dsty, 2563 u_int width, u_int height, 2564 struct fb_info_aty128 *info) 2565{ 2566 u32 save_dp_datatype, save_dp_cntl, dstval; 2567 2568 if (!width || !height) 2569 return; 2570 2571 dstval = depth_to_dst(info->current_par.crtc.depth); 2572 if (dstval == DST_24BPP) { 2573 srcx *= 3; 2574 dstx *= 3; 2575 width *= 3; 2576 } else if (dstval == -EINVAL) { 2577 printk("aty128fb: invalid depth or RGBA\n"); 2578 return; 2579 } 2580 2581 wait_for_fifo(2, info); 2582 save_dp_datatype = aty_ld_le32(DP_DATATYPE); 2583 save_dp_cntl = aty_ld_le32(DP_CNTL); 2584 2585 wait_for_fifo(6, info); 2586 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx); 2587 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT); 2588 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM); 2589 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR); 2590 2591 aty_st_le32(DST_Y_X, (dsty << 16) | dstx); 2592 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width); 2593 2594 info->blitter_may_be_busy = 1; 2595 2596 wait_for_fifo(2, info); 2597 aty_st_le32(DP_DATATYPE, save_dp_datatype); 2598 aty_st_le32(DP_CNTL, save_dp_cntl); 2599} 2600 2601 2602 /* 2603 * Text mode accelerated functions 2604 */ 2605 2606static void 2607fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx, 2608 int height, int width) 2609{ 2610 sx *= fontwidth(p); 2611 sy *= fontheight(p); 2612 dx *= fontwidth(p); 2613 dy *= fontheight(p); 2614 width *= fontwidth(p); 2615 height *= fontheight(p); 2616 2617 aty128_rectcopy(sx, sy, dx, dy, width, height, 2618 (struct fb_info_aty128 *)p->fb_info); 2619} 2620 2621 2622#ifdef FBCON_HAS_CFB8 2623static void fbcon_aty8_putc(struct vc_data *conp, struct display *p, 2624 int c, int yy, int xx) 2625{ 2626 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2627 2628 if (fb->blitter_may_be_busy) 2629 wait_for_idle(fb); 2630 2631 fbcon_cfb8_putc(conp, p, c, yy, xx); 2632} 2633 2634 2635static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p, 2636 const unsigned short *s, int count, 2637 int yy, int xx) 2638{ 2639 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2640 2641 if (fb->blitter_may_be_busy) 2642 wait_for_idle(fb); 2643 2644 fbcon_cfb8_putcs(conp, p, s, count, yy, xx); 2645} 2646 2647 2648static void fbcon_aty8_clear_margins(struct vc_data *conp, 2649 struct display *p, int bottom_only) 2650{ 2651 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2652 2653 if (fb->blitter_may_be_busy) 2654 wait_for_idle(fb); 2655 2656 fbcon_cfb8_clear_margins(conp, p, bottom_only); 2657} 2658 2659static struct display_switch fbcon_aty128_8 = { 2660 setup: fbcon_cfb8_setup, 2661 bmove: fbcon_aty128_bmove, 2662 clear: fbcon_cfb8_clear, 2663 putc: fbcon_aty8_putc, 2664 putcs: fbcon_aty8_putcs, 2665 revc: fbcon_cfb8_revc, 2666 clear_margins: fbcon_aty8_clear_margins, 2667 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16) 2668}; 2669#endif 2670#ifdef FBCON_HAS_CFB16 2671static void fbcon_aty16_putc(struct vc_data *conp, struct display *p, 2672 int c, int yy, int xx) 2673{ 2674 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2675 2676 if (fb->blitter_may_be_busy) 2677 wait_for_idle(fb); 2678 2679 fbcon_cfb16_putc(conp, p, c, yy, xx); 2680} 2681 2682 2683static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p, 2684 const unsigned short *s, int count, 2685 int yy, int xx) 2686{ 2687 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2688 2689 if (fb->blitter_may_be_busy) 2690 wait_for_idle(fb); 2691 2692 fbcon_cfb16_putcs(conp, p, s, count, yy, xx); 2693} 2694 2695 2696static void fbcon_aty16_clear_margins(struct vc_data *conp, 2697 struct display *p, int bottom_only) 2698{ 2699 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2700 2701 if (fb->blitter_may_be_busy) 2702 wait_for_idle(fb); 2703 2704 fbcon_cfb16_clear_margins(conp, p, bottom_only); 2705} 2706 2707static struct display_switch fbcon_aty128_16 = { 2708 setup: fbcon_cfb16_setup, 2709 bmove: fbcon_aty128_bmove, 2710 clear: fbcon_cfb16_clear, 2711 putc: fbcon_aty16_putc, 2712 putcs: fbcon_aty16_putcs, 2713 revc: fbcon_cfb16_revc, 2714 clear_margins: fbcon_aty16_clear_margins, 2715 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16) 2716}; 2717#endif 2718#ifdef FBCON_HAS_CFB24 2719static void fbcon_aty24_putc(struct vc_data *conp, struct display *p, 2720 int c, int yy, int xx) 2721{ 2722 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2723 2724 if (fb->blitter_may_be_busy) 2725 wait_for_idle(fb); 2726 2727 fbcon_cfb24_putc(conp, p, c, yy, xx); 2728} 2729 2730 2731static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p, 2732 const unsigned short *s, int count, 2733 int yy, int xx) 2734{ 2735 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2736 2737 if (fb->blitter_may_be_busy) 2738 wait_for_idle(fb); 2739 2740 fbcon_cfb24_putcs(conp, p, s, count, yy, xx); 2741} 2742 2743 2744static void fbcon_aty24_clear_margins(struct vc_data *conp, 2745 struct display *p, int bottom_only) 2746{ 2747 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2748 2749 if (fb->blitter_may_be_busy) 2750 wait_for_idle(fb); 2751 2752 fbcon_cfb24_clear_margins(conp, p, bottom_only); 2753} 2754 2755static struct display_switch fbcon_aty128_24 = { 2756 setup: fbcon_cfb24_setup, 2757 bmove: fbcon_aty128_bmove, 2758 clear: fbcon_cfb24_clear, 2759 putc: fbcon_aty24_putc, 2760 putcs: fbcon_aty24_putcs, 2761 revc: fbcon_cfb24_revc, 2762 clear_margins: fbcon_aty24_clear_margins, 2763 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16) 2764}; 2765#endif 2766#ifdef FBCON_HAS_CFB32 2767static void fbcon_aty32_putc(struct vc_data *conp, struct display *p, 2768 int c, int yy, int xx) 2769{ 2770 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2771 2772 if (fb->blitter_may_be_busy) 2773 wait_for_idle(fb); 2774 2775 fbcon_cfb32_putc(conp, p, c, yy, xx); 2776} 2777 2778 2779static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p, 2780 const unsigned short *s, int count, 2781 int yy, int xx) 2782{ 2783 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2784 2785 if (fb->blitter_may_be_busy) 2786 wait_for_idle(fb); 2787 2788 fbcon_cfb32_putcs(conp, p, s, count, yy, xx); 2789} 2790 2791 2792static void fbcon_aty32_clear_margins(struct vc_data *conp, 2793 struct display *p, int bottom_only) 2794{ 2795 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info); 2796 2797 if (fb->blitter_may_be_busy) 2798 wait_for_idle(fb); 2799 2800 fbcon_cfb32_clear_margins(conp, p, bottom_only); 2801} 2802 2803static struct display_switch fbcon_aty128_32 = { 2804 setup: fbcon_cfb32_setup, 2805 bmove: fbcon_aty128_bmove, 2806 clear: fbcon_cfb32_clear, 2807 putc: fbcon_aty32_putc, 2808 putcs: fbcon_aty32_putcs, 2809 revc: fbcon_cfb32_revc, 2810 clear_margins: fbcon_aty32_clear_margins, 2811 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16) 2812}; 2813#endif 2814 2815#ifdef CONFIG_PMAC_PBOOK 2816static void 2817aty128_set_suspend(struct fb_info_aty128 *info, int suspend) 2818{ 2819 u32 pmgt; 2820 u16 pwr_command; 2821 2822 if (!info->pm_reg) 2823 return; 2824 2825 /* Set the chip into the appropriate suspend mode (we use D2, 2826 * D3 would require a complete re-initialisation of the chip, 2827 * including PCI config registers, clocks, AGP configuration, ...) 2828 */ 2829 if (suspend) { 2830 /* Make sure CRTC2 is reset. Remove that the day we decide to 2831 * actually use CRTC2 and replace it with real code for disabling 2832 * the CRTC2 output during sleep 2833 */ 2834 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) & 2835 ~(CRTC2_EN)); 2836 2837 /* Set the power management mode to be PCI based */ 2838 pmgt = aty_ld_pll(POWER_MANAGEMENT); 2839 pmgt = 0x0c005407; 2840 aty_st_pll(POWER_MANAGEMENT, pmgt); 2841 (void)aty_ld_pll(POWER_MANAGEMENT); 2842 aty_st_le32(BUS_CNTL1, 0x00000010); 2843 aty_st_le32(MEM_POWER_MISC, 0x0c830000); 2844 mdelay(100); 2845 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command); 2846 /* Switch PCI power management to D2 */ 2847 pci_write_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, 2848 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2); 2849 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command); 2850 } else { 2851 /* Switch back PCI power management to D0 */ 2852 mdelay(100); 2853 pci_write_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, 0); 2854 mdelay(100); 2855 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command); 2856 mdelay(100); 2857 } 2858} 2859 2860extern struct display_switch fbcon_dummy; 2861 2862/* 2863 * Save the contents of the frame buffer when we go to sleep, 2864 * and restore it when we wake up again. 2865 */ 2866int 2867aty128_sleep_notify(struct pmu_sleep_notifier *self, int when) 2868{ 2869 struct fb_info_aty128 *info; 2870 int result; 2871 2872 result = PBOOK_SLEEP_OK; 2873 2874 for (info = board_list; info != NULL; info = info->next) { 2875 struct fb_fix_screeninfo fix; 2876 int nb; 2877 2878 aty128fb_get_fix(&fix, fg_console, (struct fb_info *)info); 2879 nb = fb_display[fg_console].var.yres * fix.line_length; 2880 2881 switch (when) { 2882 case PBOOK_SLEEP_REQUEST: 2883 info->save_framebuffer = vmalloc(nb); 2884 if (info->save_framebuffer == NULL) 2885 return PBOOK_SLEEP_REFUSE; 2886 break; 2887 case PBOOK_SLEEP_REJECT: 2888 if (info->save_framebuffer) { 2889 vfree(info->save_framebuffer); 2890 info->save_framebuffer = 0; 2891 } 2892 break; 2893 case PBOOK_SLEEP_NOW: 2894 if (info->currcon >= 0) 2895 fb_display[info->currcon].dispsw = &fbcon_dummy; 2896 2897 wait_for_idle(info); 2898 aty128_reset_engine(info); 2899 wait_for_idle(info); 2900 2901 /* Backup fb content */ 2902 if (info->save_framebuffer) 2903 memcpy_fromio(info->save_framebuffer, 2904 (void *)info->frame_buffer, nb); 2905 2906 /* Blank display and LCD */ 2907 aty128fbcon_blank(VESA_POWERDOWN+1, (struct fb_info *)info); 2908 2909 /* Sleep the chip */ 2910 aty128_set_suspend(info, 1); 2911 2912 break; 2913 case PBOOK_WAKE: 2914 /* Wake the chip */ 2915 aty128_set_suspend(info, 0); 2916 2917 aty128_reset_engine(info); 2918 wait_for_idle(info); 2919 2920 /* Restore fb content */ 2921 if (info->save_framebuffer) { 2922 memcpy_toio((void *)info->frame_buffer, 2923 info->save_framebuffer, nb); 2924 vfree(info->save_framebuffer); 2925 info->save_framebuffer = 0; 2926 } 2927 2928 if (info->currcon >= 0) { 2929 aty128_set_dispsw( 2930 &fb_display[info->currcon], 2931 info, 2932 info->current_par.crtc.bpp, 2933 info->current_par.accel_flags & FB_ACCELF_TEXT); 2934 } 2935 aty128fbcon_blank(0, (struct fb_info *)info); 2936 break; 2937 } 2938 } 2939 return result; 2940} 2941#endif /* CONFIG_PMAC_PBOOK */ 2942 2943#ifdef MODULE 2944MODULE_AUTHOR("(c)1999-2000 Brad Douglas <brad@neruo.com>"); 2945MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards"); 2946MODULE_LICENSE("GPL"); 2947MODULE_PARM(noaccel, "i"); 2948MODULE_PARM_DESC(noaccel, "Disable hardware acceleration (0 or 1=disabled) (default=0)"); 2949MODULE_PARM(font, "s"); 2950MODULE_PARM_DESC(font, "Specify one of the compiled-in fonts (default=none)"); 2951MODULE_PARM(mode, "s"); 2952MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" "); 2953#ifdef CONFIG_MTRR 2954MODULE_PARM(nomtrr, "i"); 2955MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)"); 2956#endif 2957 2958int __init 2959init_module(void) 2960{ 2961 if (noaccel) { 2962 noaccel = 1; 2963 printk(KERN_INFO "aty128fb: Parameter NOACCEL set\n"); 2964 } 2965 if (font) { 2966 strncpy(fontname, font, sizeof(fontname)-1); 2967 printk(KERN_INFO "aty128fb: Parameter FONT set to %s\n", font); 2968 } 2969 if (mode) { 2970 mode_option = mode; 2971 printk(KERN_INFO "aty128fb: Parameter MODE set to %s\n", mode); 2972 } 2973#ifdef CONFIG_MTRR 2974 if (nomtrr) { 2975 mtrr = 0; 2976 printk(KERN_INFO "aty128fb: Parameter NOMTRR set\n"); 2977 } 2978#endif 2979 2980 aty128fb_init(); 2981 return 0; 2982} 2983 2984void __exit 2985cleanup_module(void) 2986{ 2987 struct fb_info_aty128 *info = board_list; 2988 2989 while (board_list) { 2990 info = board_list; 2991 board_list = board_list->next; 2992 2993 unregister_framebuffer(&info->fb_info); 2994#ifdef CONFIG_MTRR 2995 if (info->mtrr.vram_valid) 2996 mtrr_del(info->mtrr.vram, info->frame_buffer_phys, 2997 info->vram_size); 2998#endif /* CONFIG_MTRR */ 2999 iounmap(info->regbase); 3000 iounmap(info->frame_buffer); 3001 3002 release_mem_region(pci_resource_start(info->pdev, 0), 3003 pci_resource_len(info->pdev, 0)); 3004 release_mem_region(pci_resource_start(info->pdev, 1), 3005 pci_resource_len(info->pdev, 1)); 3006 release_mem_region(pci_resource_start(info->pdev, 2), 3007 pci_resource_len(info->pdev, 2)); 3008 3009 kfree(info); 3010 } 3011} 3012#endif /* MODULE */ 3013