1#ifndef __LINUX_UHCI_H 2#define __LINUX_UHCI_H 3 4/* 5 $Id: usb-uhci.h,v 1.1.1.1 2008/10/15 03:27:03 james26_jang Exp $ 6 */ 7#define MODNAME "usb-uhci" 8#define UHCI_LATENCY_TIMER 0 9 10static __inline__ void uhci_wait_ms(unsigned int ms) 11{ 12 if(!in_interrupt()) 13 { 14 set_current_state(TASK_UNINTERRUPTIBLE); 15 schedule_timeout(1 + ms * HZ / 1000); 16 } 17 else 18 mdelay(ms); 19} 20 21/* Command register */ 22#define USBCMD 0 23#define USBCMD_RS 0x0001 /* Run/Stop */ 24#define USBCMD_HCRESET 0x0002 /* Host reset */ 25#define USBCMD_GRESET 0x0004 /* Global reset */ 26#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 27#define USBCMD_FGR 0x0010 /* Force Global Resume */ 28#define USBCMD_SWDBG 0x0020 /* SW Debug mode */ 29#define USBCMD_CF 0x0040 /* Config Flag (sw only) */ 30#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */ 31 32/* Status register */ 33#define USBSTS 2 34#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */ 35#define USBSTS_ERROR 0x0002 /* Interrupt due to error */ 36#define USBSTS_RD 0x0004 /* Resume Detect */ 37#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */ 38#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */ 39#define USBSTS_HCH 0x0020 /* HC Halted */ 40 41/* Interrupt enable register */ 42#define USBINTR 4 43#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */ 44#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 45#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */ 46#define USBINTR_SP 0x0008 /* Short packet interrupt enable */ 47 48#define USBFRNUM 6 49#define USBFLBASEADD 8 50#define USBSOF 12 51 52/* USB port status and control registers */ 53#define USBPORTSC1 16 54#define USBPORTSC2 18 55#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */ 56#define USBPORTSC_CSC 0x0002 /* Connect Status Change */ 57#define USBPORTSC_PE 0x0004 /* Port Enable */ 58#define USBPORTSC_PEC 0x0008 /* Port Enable Change */ 59#define USBPORTSC_LS 0x0030 /* Line Status */ 60#define USBPORTSC_RD 0x0040 /* Resume Detect */ 61#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */ 62#define USBPORTSC_PR 0x0200 /* Port Reset */ 63#define USBPORTSC_SUSP 0x1000 /* Suspend */ 64 65/* Legacy support register */ 66#define USBLEGSUP 0xc0 67#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */ 68 69#define UHCI_NULL_DATA_SIZE 0x7ff /* for UHCI controller TD */ 70#define UHCI_PID 0xff /* PID MASK */ 71 72#define UHCI_PTR_BITS 0x000F 73#define UHCI_PTR_TERM 0x0001 74#define UHCI_PTR_QH 0x0002 75#define UHCI_PTR_DEPTH 0x0004 76 77#define UHCI_NUMFRAMES 1024 /* in the frame list [array] */ 78#define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */ 79#define CAN_SCHEDULE_FRAMES 1000 /* how far future frames can be scheduled */ 80 81/* 82 * for TD <status>: 83 */ 84#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */ 85#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */ 86#define TD_CTRL_LS (1 << 26) /* Low Speed Device */ 87#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */ 88#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */ 89#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */ 90#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */ 91#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */ 92#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */ 93#define TD_CTRL_NAK (1 << 19) /* NAK Received */ 94#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */ 95#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */ 96#define TD_CTRL_ACTLEN_MASK 0x7ff /* actual length, encoded as n - 1 */ 97 98#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \ 99 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF) 100 101#define uhci_status_bits(ctrl_sts) (ctrl_sts & 0xFE0000) 102#define uhci_actual_length(ctrl_sts) ((ctrl_sts + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */ 103#define uhci_ptr_to_virt(x) bus_to_virt(x & ~UHCI_PTR_BITS) 104 105/* 106 * for TD <flags>: 107 */ 108#define UHCI_TD_REMOVE 0x0001 /* Remove when done */ 109 110/* 111 * for TD <info>: (a.k.a. Token) 112 */ 113#define TD_TOKEN_TOGGLE 19 114 115#define uhci_maxlen(token) ((token) >> 21) 116#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE) & 1) 117#define uhci_endpoint(token) (((token) >> 15) & 0xf) 118#define uhci_devaddr(token) (((token) >> 8) & 0x7f) 119#define uhci_devep(token) (((token) >> 8) & 0x7ff) 120#define uhci_packetid(token) ((token) & 0xff) 121#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN) 122#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN) 123 124/* ------------------------------------------------------------------------------------ 125 New TD/QH-structures 126 ------------------------------------------------------------------------------------ */ 127typedef enum { 128 TD_TYPE, QH_TYPE 129} uhci_desc_type_t; 130 131typedef struct { 132 __u32 link; 133 __u32 status; 134 __u32 info; 135 __u32 buffer; 136} uhci_td_t, *puhci_td_t; 137 138typedef struct { 139 __u32 head; 140 __u32 element; /* Queue element pointer */ 141} uhci_qh_t, *puhci_qh_t; 142 143typedef struct { 144 union { 145 uhci_td_t td; 146 uhci_qh_t qh; 147 } hw; 148 uhci_desc_type_t type; 149 dma_addr_t dma_addr; 150 struct list_head horizontal; 151 struct list_head vertical; 152 struct list_head desc_list; 153 int last_used; 154} uhci_desc_t, *puhci_desc_t; 155 156typedef struct { 157 struct list_head desc_list; // list pointer to all corresponding TDs/QHs associated with this request 158 dma_addr_t setup_packet_dma; 159 dma_addr_t transfer_buffer_dma; 160 unsigned long started; 161 struct urb *next_queued_urb; // next queued urb for this EP 162 struct urb *prev_queued_urb; 163 uhci_desc_t *bottom_qh; 164 uhci_desc_t *next_qh; // next helper QH 165 char use_loop; 166 char flags; 167} urb_priv_t, *purb_priv_t; 168 169struct virt_root_hub { 170 int devnum; /* Address of Root Hub endpoint */ 171 void *urb; 172 void *int_addr; 173 int send; 174 int interval; 175 int numports; 176 int c_p_r[8]; 177 struct timer_list rh_int_timer; 178}; 179 180typedef struct uhci { 181 int irq; 182 unsigned int io_addr; 183 unsigned int io_size; 184 unsigned int maxports; 185 int running; 186 187 int apm_state; 188 189 struct uhci *next; // chain of uhci device contexts 190 191 struct list_head urb_list; // list of all pending urbs 192 193 spinlock_t urb_list_lock; // lock to keep consistency 194 195 int unlink_urb_done; 196 atomic_t avoid_bulk; 197 198 struct usb_bus *bus; // our bus 199 200 __u32 *framelist; 201 dma_addr_t framelist_dma; 202 uhci_desc_t **iso_td; 203 uhci_desc_t *int_chain[8]; 204 uhci_desc_t *ls_control_chain; 205 uhci_desc_t *control_chain; 206 uhci_desc_t *bulk_chain; 207 uhci_desc_t *chain_end; 208 uhci_desc_t *td1ms; 209 uhci_desc_t *td32ms; 210 struct list_head free_desc; 211 spinlock_t qh_lock; 212 spinlock_t td_lock; 213 struct virt_root_hub rh; //private data of the virtual root hub 214 int loop_usage; // URBs using bandwidth reclamation 215 216 struct list_head urb_unlinked; // list of all unlinked urbs 217 long timeout_check; 218 int timeout_urbs; 219 struct pci_dev *uhci_pci; 220 struct pci_pool *desc_pool; 221 long last_error_time; // last error output in uhci_interrupt() 222} uhci_t, *puhci_t; 223 224 225#define MAKE_TD_ADDR(a) ((a)->dma_addr&~UHCI_PTR_QH) 226#define MAKE_QH_ADDR(a) ((a)->dma_addr|UHCI_PTR_QH) 227#define UHCI_GET_CURRENT_FRAME(uhci) (inw ((uhci)->io_addr + USBFRNUM)) 228 229#define CLEAN_TRANSFER_NO_DELETION 0 230#define CLEAN_TRANSFER_REGULAR 1 231#define CLEAN_TRANSFER_DELETION_MARK 2 232 233#define CLEAN_NOT_FORCED 0 234#define CLEAN_FORCED 1 235 236#define PROCESS_ISO_REGULAR 0 237#define PROCESS_ISO_FORCE 1 238 239#define UNLINK_ASYNC_STORE_URB 0 240#define UNLINK_ASYNC_DONT_STORE 1 241 242#define is_td_active(desc) (desc->hw.td.status & cpu_to_le32(TD_CTRL_ACTIVE)) 243 244#define set_qh_head(desc,val) (desc)->hw.qh.head=cpu_to_le32(val) 245#define set_qh_element(desc,val) (desc)->hw.qh.element=cpu_to_le32(val) 246#define set_td_link(desc,val) (desc)->hw.td.link=cpu_to_le32(val) 247#define set_td_ioc(desc) (desc)->hw.td.status |= cpu_to_le32(TD_CTRL_IOC) 248#define clr_td_ioc(desc) (desc)->hw.td.status &= cpu_to_le32(~TD_CTRL_IOC) 249 250 251/* ------------------------------------------------------------------------------------ 252 Virtual Root HUB 253 ------------------------------------------------------------------------------------ */ 254/* destination of request */ 255#define RH_INTERFACE 0x01 256#define RH_ENDPOINT 0x02 257#define RH_OTHER 0x03 258 259#define RH_CLASS 0x20 260#define RH_VENDOR 0x40 261 262/* Requests: bRequest << 8 | bmRequestType */ 263#define RH_GET_STATUS 0x0080 264#define RH_CLEAR_FEATURE 0x0100 265#define RH_SET_FEATURE 0x0300 266#define RH_SET_ADDRESS 0x0500 267#define RH_GET_DESCRIPTOR 0x0680 268#define RH_SET_DESCRIPTOR 0x0700 269#define RH_GET_CONFIGURATION 0x0880 270#define RH_SET_CONFIGURATION 0x0900 271#define RH_GET_STATE 0x0280 272#define RH_GET_INTERFACE 0x0A80 273#define RH_SET_INTERFACE 0x0B00 274#define RH_SYNC_FRAME 0x0C80 275/* Our Vendor Specific Request */ 276#define RH_SET_EP 0x2000 277 278 279/* Hub port features */ 280#define RH_PORT_CONNECTION 0x00 281#define RH_PORT_ENABLE 0x01 282#define RH_PORT_SUSPEND 0x02 283#define RH_PORT_OVER_CURRENT 0x03 284#define RH_PORT_RESET 0x04 285#define RH_PORT_POWER 0x08 286#define RH_PORT_LOW_SPEED 0x09 287#define RH_C_PORT_CONNECTION 0x10 288#define RH_C_PORT_ENABLE 0x11 289#define RH_C_PORT_SUSPEND 0x12 290#define RH_C_PORT_OVER_CURRENT 0x13 291#define RH_C_PORT_RESET 0x14 292 293/* Hub features */ 294#define RH_C_HUB_LOCAL_POWER 0x00 295#define RH_C_HUB_OVER_CURRENT 0x01 296 297#define RH_DEVICE_REMOTE_WAKEUP 0x00 298#define RH_ENDPOINT_STALL 0x01 299 300/* Our Vendor Specific feature */ 301#define RH_REMOVE_EP 0x00 302 303 304#define RH_ACK 0x01 305#define RH_REQ_ERR -1 306#define RH_NACK 0x00 307 308#endif 309