1/*********************************************************************** 2 * Copyright 2001 MontaVista Software Inc. 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 4 * 5 * drivers/sound/nec_vrc5477.c 6 * AC97 sound dirver for NEC Vrc5477 chip (an integrated, 7 * multi-function controller chip for MIPS CPUs) 8 * 9 * VRA support Copyright 2001 Bradley D. LaRonde <brad@ltc.com> 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 *********************************************************************** 16 */ 17 18/* 19 * This code is derived from ite8172.c, which is written by Steve Longerbeam. 20 * 21 * Features: 22 * Currently we only support the following capabilities: 23 * . mono output to PCM L/R (line out). 24 * . stereo output to PCM L/R (line out). 25 * . mono input from PCM L (line in). 26 * . stereo output from PCM (line in). 27 * . sampling rate at 48k or variable sampling rate 28 * . support /dev/dsp, /dev/mixer devices, standard OSS devices. 29 * . only support 16-bit PCM format (hardware limit, no software 30 * translation) 31 * . support duplex, but no trigger or realtime. 32 * 33 * Specifically the following are not supported: 34 * . app-set frag size. 35 * . mmap'ed buffer access 36 */ 37 38/* 39 * Original comments from ite8172.c file. 40 */ 41 42/* 43 * 44 * Notes: 45 * 46 * 1. Much of the OSS buffer allocation, ioctl's, and mmap'ing are 47 * taken, slightly modified or not at all, from the ES1371 driver, 48 * so refer to the credits in es1371.c for those. The rest of the 49 * code (probe, open, read, write, the ISR, etc.) is new. 50 * 2. The following support is untested: 51 * * Memory mapping the audio buffers, and the ioctl controls that go 52 * with it. 53 * * S/PDIF output. 54 * 3. The following is not supported: 55 * * I2S input. 56 * * legacy audio mode. 57 * 4. Support for volume button interrupts is implemented but doesn't 58 * work yet. 59 * 60 * Revision history 61 * 02.08.2001 0.1 Initial release 62 */ 63 64#include <linux/version.h> 65#include <linux/module.h> 66#include <linux/string.h> 67#include <linux/kernel.h> 68#include <linux/ioport.h> 69#include <linux/sched.h> 70#include <linux/delay.h> 71#include <linux/sound.h> 72#include <linux/slab.h> 73#include <linux/soundcard.h> 74#include <linux/pci.h> 75#include <linux/init.h> 76#include <linux/poll.h> 77#include <linux/bitops.h> 78#include <linux/proc_fs.h> 79#include <linux/spinlock.h> 80#include <linux/smp_lock.h> 81#include <linux/ac97_codec.h> 82#include <linux/wrapper.h> 83#include <asm/io.h> 84#include <asm/dma.h> 85#include <asm/uaccess.h> 86#include <asm/hardirq.h> 87 88/* -------------------debug macros -------------------------------------- */ 89/* #undef VRC5477_AC97_DEBUG */ 90#define VRC5477_AC97_DEBUG 91 92#undef VRC5477_AC97_VERBOSE_DEBUG 93/* #define VRC5477_AC97_VERBOSE_DEBUG */ 94 95#if defined(VRC5477_AC97_VERBOSE_DEBUG) 96#define VRC5477_AC97_DEBUG 97#endif 98 99#if defined(VRC5477_AC97_DEBUG) 100#include <linux/kernel.h> 101#define ASSERT(x) if (!(x)) { \ 102 panic("assertion failed at %s:%d: %s\n", __FILE__, __LINE__, #x); } 103#else 104#define ASSERT(x) 105#endif /* VRC5477_AC97_DEBUG */ 106 107#if defined(VRC5477_AC97_VERBOSE_DEBUG) 108static u16 inTicket=0; /* check sync between intr & write */ 109static u16 outTicket=0; 110#endif 111 112/* --------------------------------------------------------------------- */ 113 114#undef OSS_DOCUMENTED_MIXER_SEMANTICS 115 116static const unsigned sample_shift[] = { 0, 1, 1, 2 }; 117 118#define VRC5477_INT_CLR 0x0 119#define VRC5477_INT_STATUS 0x0 120#define VRC5477_CODEC_WR 0x4 121#define VRC5477_CODEC_RD 0x8 122#define VRC5477_CTRL 0x18 123#define VRC5477_ACLINK_CTRL 0x1c 124#define VRC5477_INT_MASK 0x24 125 126#define VRC5477_DAC1_CTRL 0x30 127#define VRC5477_DAC1L 0x34 128#define VRC5477_DAC1_BADDR 0x38 129#define VRC5477_DAC2_CTRL 0x3c 130#define VRC5477_DAC2L 0x40 131#define VRC5477_DAC2_BADDR 0x44 132#define VRC5477_DAC3_CTRL 0x48 133#define VRC5477_DAC3L 0x4c 134#define VRC5477_DAC3_BADDR 0x50 135 136#define VRC5477_ADC1_CTRL 0x54 137#define VRC5477_ADC1L 0x58 138#define VRC5477_ADC1_BADDR 0x5c 139#define VRC5477_ADC2_CTRL 0x60 140#define VRC5477_ADC2L 0x64 141#define VRC5477_ADC2_BADDR 0x68 142#define VRC5477_ADC3_CTRL 0x6c 143#define VRC5477_ADC3L 0x70 144#define VRC5477_ADC3_BADDR 0x74 145 146#define VRC5477_CODEC_WR_RWC (1 << 23) 147 148#define VRC5477_CODEC_RD_RRDYA (1 << 31) 149#define VRC5477_CODEC_RD_RRDYD (1 << 30) 150 151#define VRC5477_ACLINK_CTRL_RST_ON (1 << 15) 152#define VRC5477_ACLINK_CTRL_RST_TIME 0x7f 153#define VRC5477_ACLINK_CTRL_SYNC_ON (1 << 30) 154#define VRC5477_ACLINK_CTRL_CK_STOP_ON (1 << 31) 155 156#define VRC5477_CTRL_DAC2ENB (1 << 15) 157#define VRC5477_CTRL_ADC2ENB (1 << 14) 158#define VRC5477_CTRL_DAC1ENB (1 << 13) 159#define VRC5477_CTRL_ADC1ENB (1 << 12) 160 161#define VRC5477_INT_MASK_NMASK (1 << 31) 162#define VRC5477_INT_MASK_DAC1END (1 << 5) 163#define VRC5477_INT_MASK_DAC2END (1 << 4) 164#define VRC5477_INT_MASK_DAC3END (1 << 3) 165#define VRC5477_INT_MASK_ADC1END (1 << 2) 166#define VRC5477_INT_MASK_ADC2END (1 << 1) 167#define VRC5477_INT_MASK_ADC3END (1 << 0) 168 169#define VRC5477_DMA_ACTIVATION (1 << 31) 170#define VRC5477_DMA_WIP (1 << 30) 171 172 173#define VRC5477_AC97_MODULE_NAME "NEC_Vrc5477_audio" 174#define PFX VRC5477_AC97_MODULE_NAME ": " 175 176/* --------------------------------------------------------------------- */ 177 178struct vrc5477_ac97_state { 179 /* list of vrc5477_ac97 devices */ 180 struct list_head devs; 181 182 /* the corresponding pci_dev structure */ 183 struct pci_dev *dev; 184 185 /* soundcore stuff */ 186 int dev_audio; 187 188 /* hardware resources */ 189 unsigned long io; 190 unsigned int irq; 191 192#ifdef VRC5477_AC97_DEBUG 193 /* debug /proc entry */ 194 struct proc_dir_entry *ps; 195 struct proc_dir_entry *ac97_ps; 196#endif /* VRC5477_AC97_DEBUG */ 197 198 struct ac97_codec codec; 199 200 unsigned dacChannels, adcChannels; 201 unsigned short dacRate, adcRate; 202 unsigned short extended_status; 203 204 spinlock_t lock; 205 struct semaphore open_sem; 206 mode_t open_mode; 207 wait_queue_head_t open_wait; 208 209 struct dmabuf { 210 void *lbuf, *rbuf; 211 dma_addr_t lbufDma, rbufDma; 212 unsigned bufOrder; 213 unsigned numFrag; 214 unsigned fragShift; 215 unsigned fragSize; /* redundant */ 216 unsigned fragTotalSize; /* = numFrag * fragSize(real) */ 217 unsigned nextIn; 218 unsigned nextOut; 219 int count; 220 unsigned error; /* over/underrun */ 221 wait_queue_head_t wait; 222 /* OSS stuff */ 223 unsigned stopped:1; 224 unsigned ready:1; 225 } dma_dac, dma_adc; 226 227 #define WORK_BUF_SIZE 2048 228 struct { 229 u16 lchannel; 230 u16 rchannel; 231 } workBuf[WORK_BUF_SIZE/4]; 232}; 233 234/* --------------------------------------------------------------------- */ 235 236static LIST_HEAD(devs); 237 238/* --------------------------------------------------------------------- */ 239 240static inline unsigned ld2(unsigned int x) 241{ 242 unsigned r = 0; 243 244 if (x >= 0x10000) { 245 x >>= 16; 246 r += 16; 247 } 248 if (x >= 0x100) { 249 x >>= 8; 250 r += 8; 251 } 252 if (x >= 0x10) { 253 x >>= 4; 254 r += 4; 255 } 256 if (x >= 4) { 257 x >>= 2; 258 r += 2; 259 } 260 if (x >= 2) 261 r++; 262 return r; 263} 264 265/* --------------------------------------------------------------------- */ 266 267static u16 rdcodec(struct ac97_codec *codec, u8 addr) 268{ 269 struct vrc5477_ac97_state *s = 270 (struct vrc5477_ac97_state *)codec->private_data; 271 unsigned long flags; 272 u32 result; 273 274 spin_lock_irqsave(&s->lock, flags); 275 276 /* wait until we can access codec registers */ 277 while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000); 278 279 /* write the address and "read" command to codec */ 280 addr = addr & 0x7f; 281 outl((addr << 16) | VRC5477_CODEC_WR_RWC, s->io + VRC5477_CODEC_WR); 282 283 /* get the return result */ 284 udelay(100); 285 while ( (result = inl(s->io + VRC5477_CODEC_RD)) & 286 (VRC5477_CODEC_RD_RRDYA | VRC5477_CODEC_RD_RRDYD) ) { 287 /* we get either addr or data, or both */ 288 if (result & VRC5477_CODEC_RD_RRDYA) { 289 ASSERT(addr == ((result >> 16) & 0x7f) ); 290 } 291 if (result & VRC5477_CODEC_RD_RRDYD) { 292 break; 293 } 294 } 295 296 spin_unlock_irqrestore(&s->lock, flags); 297 298 return result & 0xffff;; 299} 300 301 302static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data) 303{ 304 struct vrc5477_ac97_state *s = 305 (struct vrc5477_ac97_state *)codec->private_data; 306 unsigned long flags; 307 308 spin_lock_irqsave(&s->lock, flags); 309 310 /* wait until we can access codec registers */ 311 while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000); 312 313 /* write the address and value to codec */ 314 outl((addr << 16) | data, s->io + VRC5477_CODEC_WR); 315 316 spin_unlock_irqrestore(&s->lock, flags); 317} 318 319 320static void waitcodec(struct ac97_codec *codec) 321{ 322 struct vrc5477_ac97_state *s = 323 (struct vrc5477_ac97_state *)codec->private_data; 324 325 /* wait until we can access codec registers */ 326 while (inl(s->io + VRC5477_CODEC_WR) & 0x80000000); 327} 328 329static int ac97_codec_not_present(struct ac97_codec *codec) 330{ 331 struct vrc5477_ac97_state *s = 332 (struct vrc5477_ac97_state *)codec->private_data; 333 unsigned long flags; 334 unsigned short count = 0xffff; 335 336 spin_lock_irqsave(&s->lock, flags); 337 338 /* wait until we can access codec registers */ 339 do { 340 if (!(inl(s->io + VRC5477_CODEC_WR) & 0x80000000)) 341 break; 342 } while (--count); 343 344 if (count == 0) { 345 spin_unlock_irqrestore(&s->lock, flags); 346 return -1; 347 } 348 349 /* write 0 to reset */ 350 outl((AC97_RESET << 16) | 0, s->io + VRC5477_CODEC_WR); 351 352 /* test whether we get a response from ac97 chip */ 353 count = 0xffff; 354 do { 355 if (!(inl(s->io + VRC5477_CODEC_WR) & 0x80000000)) 356 break; 357 } while (--count); 358 359 if (count == 0) { 360 spin_unlock_irqrestore(&s->lock, flags); 361 return -1; 362 } 363 spin_unlock_irqrestore(&s->lock, flags); 364 return 0; 365} 366 367/* --------------------------------------------------------------------- */ 368 369static void vrc5477_ac97_delay(int msec) 370{ 371 unsigned long tmo; 372 signed long tmo2; 373 374 if (in_interrupt()) 375 return; 376 377 tmo = jiffies + (msec*HZ)/1000; 378 for (;;) { 379 tmo2 = tmo - jiffies; 380 if (tmo2 <= 0) 381 break; 382 schedule_timeout(tmo2); 383 } 384} 385 386 387static void set_adc_rate(struct vrc5477_ac97_state *s, unsigned rate) 388{ 389 wrcodec(&s->codec, AC97_PCM_LR_ADC_RATE, rate); 390 s->adcRate = rate; 391} 392 393 394static void set_dac_rate(struct vrc5477_ac97_state *s, unsigned rate) 395{ 396 if(s->extended_status & AC97_EXTSTAT_VRA) { 397 wrcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE, rate); 398 s->dacRate = rdcodec(&s->codec, AC97_PCM_FRONT_DAC_RATE); 399 } 400} 401 402 403/* --------------------------------------------------------------------- */ 404 405static inline void 406stop_dac(struct vrc5477_ac97_state *s) 407{ 408 struct dmabuf* db = &s->dma_dac; 409 unsigned long flags; 410 u32 temp; 411 412 spin_lock_irqsave(&s->lock, flags); 413 414 if (db->stopped) { 415 spin_unlock_irqrestore(&s->lock, flags); 416 return; 417 } 418 419 /* deactivate the dma */ 420 outl(0, s->io + VRC5477_DAC1_CTRL); 421 outl(0, s->io + VRC5477_DAC2_CTRL); 422 423 /* wait for DAM completely stop */ 424 while (inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP); 425 while (inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP); 426 427 /* disable dac slots in aclink */ 428 temp = inl(s->io + VRC5477_CTRL); 429 temp &= ~ (VRC5477_CTRL_DAC1ENB | VRC5477_CTRL_DAC2ENB); 430 outl (temp, s->io + VRC5477_CTRL); 431 432 /* disable interrupts */ 433 temp = inl(s->io + VRC5477_INT_MASK); 434 temp &= ~ (VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END); 435 outl (temp, s->io + VRC5477_INT_MASK); 436 437 /* clear pending ones */ 438 outl(VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END, 439 s->io + VRC5477_INT_CLR); 440 441 db->stopped = 1; 442 443 spin_unlock_irqrestore(&s->lock, flags); 444} 445 446static void start_dac(struct vrc5477_ac97_state *s) 447{ 448 struct dmabuf* db = &s->dma_dac; 449 unsigned long flags; 450 u32 dmaLength; 451 u32 temp; 452 453 spin_lock_irqsave(&s->lock, flags); 454 455 if (!db->stopped) { 456 spin_unlock_irqrestore(&s->lock, flags); 457 return; 458 } 459 460 /* we should have some data to do the DMA trasnfer */ 461 ASSERT(db->count >= db->fragSize); 462 463 /* clear pending fales interrupts */ 464 outl(VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END, 465 s->io + VRC5477_INT_CLR); 466 467 /* enable interrupts */ 468 temp = inl(s->io + VRC5477_INT_MASK); 469 temp |= VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END; 470 outl(temp, s->io + VRC5477_INT_MASK); 471 472 /* setup dma base addr */ 473 outl(db->lbufDma + db->nextOut, s->io + VRC5477_DAC1_BADDR); 474 if (s->dacChannels == 1) { 475 outl(db->lbufDma + db->nextOut, s->io + VRC5477_DAC2_BADDR); 476 } else { 477 outl(db->rbufDma + db->nextOut, s->io + VRC5477_DAC2_BADDR); 478 } 479 480 /* set dma length, in the unit of 0x10 bytes */ 481 dmaLength = db->fragSize >> 4; 482 outl(dmaLength, s->io + VRC5477_DAC1L); 483 outl(dmaLength, s->io + VRC5477_DAC2L); 484 485 /* activate dma */ 486 outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_DAC1_CTRL); 487 outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_DAC2_CTRL); 488 489 /* enable dac slots - we should hear the music now! */ 490 temp = inl(s->io + VRC5477_CTRL); 491 temp |= (VRC5477_CTRL_DAC1ENB | VRC5477_CTRL_DAC2ENB); 492 outl (temp, s->io + VRC5477_CTRL); 493 494 /* it is time to setup next dma transfer */ 495 ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP); 496 ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP); 497 498 temp = db->nextOut + db->fragSize; 499 if (temp >= db->fragTotalSize) { 500 ASSERT(temp == db->fragTotalSize); 501 temp = 0; 502 } 503 504 outl(db->lbufDma + temp, s->io + VRC5477_DAC1_BADDR); 505 if (s->dacChannels == 1) { 506 outl(db->lbufDma + temp, s->io + VRC5477_DAC2_BADDR); 507 } else { 508 outl(db->rbufDma + temp, s->io + VRC5477_DAC2_BADDR); 509 } 510 511 db->stopped = 0; 512 513#if defined(VRC5477_AC97_VERBOSE_DEBUG) 514 outTicket = *(u16*)(db->lbuf+db->nextOut); 515 if (db->count > db->fragSize) { 516 ASSERT((u16)(outTicket+1) == *(u16*)(db->lbuf+temp)); 517 } 518#endif 519 520 spin_unlock_irqrestore(&s->lock, flags); 521} 522 523static inline void stop_adc(struct vrc5477_ac97_state *s) 524{ 525 struct dmabuf* db = &s->dma_adc; 526 unsigned long flags; 527 u32 temp; 528 529 spin_lock_irqsave(&s->lock, flags); 530 531 if (db->stopped) { 532 spin_unlock_irqrestore(&s->lock, flags); 533 return; 534 } 535 536 /* deactivate the dma */ 537 outl(0, s->io + VRC5477_ADC1_CTRL); 538 outl(0, s->io + VRC5477_ADC2_CTRL); 539 540 /* disable adc slots in aclink */ 541 temp = inl(s->io + VRC5477_CTRL); 542 temp &= ~ (VRC5477_CTRL_ADC1ENB | VRC5477_CTRL_ADC2ENB); 543 outl (temp, s->io + VRC5477_CTRL); 544 545 /* disable interrupts */ 546 temp = inl(s->io + VRC5477_INT_MASK); 547 temp &= ~ (VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END); 548 outl (temp, s->io + VRC5477_INT_MASK); 549 550 /* clear pending ones */ 551 outl(VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END, 552 s->io + VRC5477_INT_CLR); 553 554 db->stopped = 1; 555 556 spin_unlock_irqrestore(&s->lock, flags); 557} 558 559static void start_adc(struct vrc5477_ac97_state *s) 560{ 561 struct dmabuf* db = &s->dma_adc; 562 unsigned long flags; 563 u32 dmaLength; 564 u32 temp; 565 566 spin_lock_irqsave(&s->lock, flags); 567 568 if (!db->stopped) { 569 spin_unlock_irqrestore(&s->lock, flags); 570 return; 571 } 572 573 /* we should at least have some free space in the buffer */ 574 ASSERT(db->count < db->fragTotalSize - db->fragSize * 2); 575 576 /* clear pending ones */ 577 outl(VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END, 578 s->io + VRC5477_INT_CLR); 579 580 /* enable interrupts */ 581 temp = inl(s->io + VRC5477_INT_MASK); 582 temp |= VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END; 583 outl(temp, s->io + VRC5477_INT_MASK); 584 585 /* setup dma base addr */ 586 outl(db->lbufDma + db->nextIn, s->io + VRC5477_ADC1_BADDR); 587 outl(db->rbufDma + db->nextIn, s->io + VRC5477_ADC2_BADDR); 588 589 /* setup dma length */ 590 dmaLength = db->fragSize >> 4; 591 outl(dmaLength, s->io + VRC5477_ADC1L); 592 outl(dmaLength, s->io + VRC5477_ADC2L); 593 594 /* activate dma */ 595 outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_ADC1_CTRL); 596 outl(VRC5477_DMA_ACTIVATION, s->io + VRC5477_ADC2_CTRL); 597 598 /* enable adc slots */ 599 temp = inl(s->io + VRC5477_CTRL); 600 temp |= (VRC5477_CTRL_ADC1ENB | VRC5477_CTRL_ADC2ENB); 601 outl (temp, s->io + VRC5477_CTRL); 602 603 /* it is time to setup next dma transfer */ 604 temp = db->nextIn + db->fragSize; 605 if (temp >= db->fragTotalSize) { 606 ASSERT(temp == db->fragTotalSize); 607 temp = 0; 608 } 609 outl(db->lbufDma + temp, s->io + VRC5477_ADC1_BADDR); 610 outl(db->rbufDma + temp, s->io + VRC5477_ADC2_BADDR); 611 612 db->stopped = 0; 613 614 spin_unlock_irqrestore(&s->lock, flags); 615} 616 617/* --------------------------------------------------------------------- */ 618 619#define DMABUF_DEFAULTORDER (16-PAGE_SHIFT) 620#define DMABUF_MINORDER 1 621 622static inline void dealloc_dmabuf(struct vrc5477_ac97_state *s, 623 struct dmabuf *db) 624{ 625 if (db->lbuf) { 626 ASSERT(db->rbuf); 627 pci_free_consistent(s->dev, PAGE_SIZE << db->bufOrder, 628 db->lbuf, db->lbufDma); 629 pci_free_consistent(s->dev, PAGE_SIZE << db->bufOrder, 630 db->rbuf, db->rbufDma); 631 db->lbuf = db->rbuf = NULL; 632 } 633 db->nextIn = db->nextOut = 0; 634 db->ready = 0; 635} 636 637static int prog_dmabuf(struct vrc5477_ac97_state *s, 638 struct dmabuf *db, 639 unsigned rate) 640{ 641 int order; 642 unsigned bufsize; 643 644 if (!db->lbuf) { 645 ASSERT(!db->rbuf); 646 647 db->ready = 0; 648 for (order = DMABUF_DEFAULTORDER; 649 order >= DMABUF_MINORDER; 650 order--) { 651 db->lbuf = pci_alloc_consistent(s->dev, 652 PAGE_SIZE << order, 653 &db->lbufDma); 654 db->rbuf = pci_alloc_consistent(s->dev, 655 PAGE_SIZE << order, 656 &db->rbufDma); 657 if (db->lbuf && db->rbuf) break; 658 if (db->lbuf) { 659 ASSERT(!db->rbuf); 660 pci_free_consistent(s->dev, 661 PAGE_SIZE << order, 662 db->lbuf, 663 db->lbufDma); 664 } 665 } 666 if (!db->lbuf) { 667 ASSERT(!db->rbuf); 668 return -ENOMEM; 669 } 670 671 db->bufOrder = order; 672 } 673 674 db->count = 0; 675 db->nextIn = db->nextOut = 0; 676 677 bufsize = PAGE_SIZE << db->bufOrder; 678 db->fragShift = ld2(rate * 2 / 100); 679 if (db->fragShift < 4) db->fragShift = 4; 680 681 db->numFrag = bufsize >> db->fragShift; 682 while (db->numFrag < 4 && db->fragShift > 4) { 683 db->fragShift--; 684 db->numFrag = bufsize >> db->fragShift; 685 } 686 db->fragSize = 1 << db->fragShift; 687 db->fragTotalSize = db->numFrag << db->fragShift; 688 memset(db->lbuf, 0, db->fragTotalSize); 689 memset(db->rbuf, 0, db->fragTotalSize); 690 691 db->ready = 1; 692 693 return 0; 694} 695 696static inline int prog_dmabuf_adc(struct vrc5477_ac97_state *s) 697{ 698 stop_adc(s); 699 return prog_dmabuf(s, &s->dma_adc, s->adcRate); 700} 701 702static inline int prog_dmabuf_dac(struct vrc5477_ac97_state *s) 703{ 704 stop_dac(s); 705 return prog_dmabuf(s, &s->dma_dac, s->dacRate); 706} 707 708 709/* --------------------------------------------------------------------- */ 710/* hold spinlock for the following! */ 711 712static inline void vrc5477_ac97_adc_interrupt(struct vrc5477_ac97_state *s) 713{ 714 struct dmabuf* adc = &s->dma_adc; 715 unsigned temp; 716 717 /* we need two frags avaiable because one is already being used 718 * and the other will be used when next interrupt happens. 719 */ 720 if (adc->count >= adc->fragTotalSize - adc->fragSize) { 721 stop_adc(s); 722 adc->error++; 723 printk(KERN_INFO PFX "adc overrun\n"); 724 return; 725 } 726 727 /* set the base addr for next DMA transfer */ 728 temp = adc->nextIn + 2*adc->fragSize; 729 if (temp >= adc->fragTotalSize) { 730 ASSERT( (temp == adc->fragTotalSize) || 731 (temp == adc->fragTotalSize + adc->fragSize) ); 732 temp -= adc->fragTotalSize; 733 } 734 outl(adc->lbufDma + temp, s->io + VRC5477_ADC1_BADDR); 735 outl(adc->rbufDma + temp, s->io + VRC5477_ADC2_BADDR); 736 737 /* adjust nextIn */ 738 adc->nextIn += adc->fragSize; 739 if (adc->nextIn >= adc->fragTotalSize) { 740 ASSERT(adc->nextIn == adc->fragTotalSize); 741 adc->nextIn = 0; 742 } 743 744 /* adjust count */ 745 adc->count += adc->fragSize; 746 747 /* wake up anybody listening */ 748 if (waitqueue_active(&adc->wait)) { 749 wake_up_interruptible(&adc->wait); 750 } 751} 752 753static inline void vrc5477_ac97_dac_interrupt(struct vrc5477_ac97_state *s) 754{ 755 struct dmabuf* dac = &s->dma_dac; 756 unsigned temp; 757 758 /* next DMA transfer should already started */ 759 // ASSERT(inl(s->io + VRC5477_DAC1_CTRL) & VRC5477_DMA_WIP); 760 // ASSERT(inl(s->io + VRC5477_DAC2_CTRL) & VRC5477_DMA_WIP); 761 762 /* let us set for next next DMA transfer */ 763 temp = dac->nextOut + dac->fragSize*2; 764 if (temp >= dac->fragTotalSize) { 765 ASSERT( (temp == dac->fragTotalSize) || 766 (temp == dac->fragTotalSize + dac->fragSize) ); 767 temp -= dac->fragTotalSize; 768 } 769 outl(dac->lbufDma + temp, s->io + VRC5477_DAC1_BADDR); 770 if (s->dacChannels == 1) { 771 outl(dac->lbufDma + temp, s->io + VRC5477_DAC2_BADDR); 772 } else { 773 outl(dac->rbufDma + temp, s->io + VRC5477_DAC2_BADDR); 774 } 775 776#if defined(VRC5477_AC97_VERBOSE_DEBUG) 777 if (*(u16*)(dac->lbuf + dac->nextOut) != outTicket) { 778 printk("assert fail: - %d vs %d\n", 779 *(u16*)(dac->lbuf + dac->nextOut), 780 outTicket); 781 ASSERT(1 == 0); 782 } 783#endif 784 785 /* adjust nextOut pointer */ 786 dac->nextOut += dac->fragSize; 787 if (dac->nextOut >= dac->fragTotalSize) { 788 ASSERT(dac->nextOut == dac->fragTotalSize); 789 dac->nextOut = 0; 790 } 791 792 /* adjust count */ 793 dac->count -= dac->fragSize; 794 if (dac->count <=0 ) { 795 /* buffer under run */ 796 dac->count = 0; 797 dac->nextIn = dac->nextOut; 798 stop_dac(s); 799 } 800 801#if defined(VRC5477_AC97_VERBOSE_DEBUG) 802 if (dac->count) { 803 outTicket ++; 804 ASSERT(*(u16*)(dac->lbuf + dac->nextOut) == outTicket); 805 } 806#endif 807 808 /* we cannot have both under run and someone is waiting on us */ 809 ASSERT(! (waitqueue_active(&dac->wait) && (dac->count <= 0)) ); 810 811 /* wake up anybody listening */ 812 if (waitqueue_active(&dac->wait)) 813 wake_up_interruptible(&dac->wait); 814} 815 816static void vrc5477_ac97_interrupt(int irq, void *dev_id, struct pt_regs *regs) 817{ 818 struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)dev_id; 819 u32 irqStatus; 820 u32 adcInterrupts, dacInterrupts; 821 822 spin_lock(&s->lock); 823 824 /* get irqStatus and clear the detected ones */ 825 irqStatus = inl(s->io + VRC5477_INT_STATUS); 826 outl(irqStatus, s->io + VRC5477_INT_CLR); 827 828 /* let us see what we get */ 829 dacInterrupts = VRC5477_INT_MASK_DAC1END | VRC5477_INT_MASK_DAC2END; 830 adcInterrupts = VRC5477_INT_MASK_ADC1END | VRC5477_INT_MASK_ADC2END; 831 if (irqStatus & dacInterrupts) { 832 /* we should get both interrupts, but just in case ... */ 833 if (irqStatus & VRC5477_INT_MASK_DAC1END) { 834 vrc5477_ac97_dac_interrupt(s); 835 } 836 if ( (irqStatus & dacInterrupts) != dacInterrupts ) { 837 printk(KERN_WARNING "vrc5477_ac97 : dac interrupts not in sync!!!\n"); 838 stop_dac(s); 839 start_dac(s); 840 } 841 } else if (irqStatus & adcInterrupts) { 842 /* we should get both interrupts, but just in case ... */ 843 if(irqStatus & VRC5477_INT_MASK_ADC1END) { 844 vrc5477_ac97_adc_interrupt(s); 845 } 846 if ( (irqStatus & adcInterrupts) != adcInterrupts ) { 847 printk(KERN_WARNING "vrc5477_ac97 : adc interrupts not in sync!!!\n"); 848 stop_adc(s); 849 start_adc(s); 850 } 851 } 852 853 spin_unlock(&s->lock); 854} 855 856/* --------------------------------------------------------------------- */ 857 858static int vrc5477_ac97_open_mixdev(struct inode *inode, struct file *file) 859{ 860 int minor = MINOR(inode->i_rdev); 861 struct list_head *list; 862 struct vrc5477_ac97_state *s; 863 864 for (list = devs.next; ; list = list->next) { 865 if (list == &devs) 866 return -ENODEV; 867 s = list_entry(list, struct vrc5477_ac97_state, devs); 868 if (s->codec.dev_mixer == minor) 869 break; 870 } 871 file->private_data = s; 872 return 0; 873} 874 875static int vrc5477_ac97_release_mixdev(struct inode *inode, struct file *file) 876{ 877 return 0; 878} 879 880 881static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, 882 unsigned long arg) 883{ 884 return codec->mixer_ioctl(codec, cmd, arg); 885} 886 887static int vrc5477_ac97_ioctl_mixdev(struct inode *inode, struct file *file, 888 unsigned int cmd, unsigned long arg) 889{ 890 struct vrc5477_ac97_state *s = 891 (struct vrc5477_ac97_state *)file->private_data; 892 struct ac97_codec *codec = &s->codec; 893 894 return mixdev_ioctl(codec, cmd, arg); 895} 896 897static /*const*/ struct file_operations vrc5477_ac97_mixer_fops = { 898 owner: THIS_MODULE, 899 llseek: no_llseek, 900 ioctl: vrc5477_ac97_ioctl_mixdev, 901 open: vrc5477_ac97_open_mixdev, 902 release: vrc5477_ac97_release_mixdev, 903}; 904 905/* --------------------------------------------------------------------- */ 906 907static int drain_dac(struct vrc5477_ac97_state *s, int nonblock) 908{ 909 unsigned long flags; 910 int count, tmo; 911 912 if (!s->dma_dac.ready) 913 return 0; 914 915 for (;;) { 916 spin_lock_irqsave(&s->lock, flags); 917 count = s->dma_dac.count; 918 spin_unlock_irqrestore(&s->lock, flags); 919 if (count <= 0) 920 break; 921 if (signal_pending(current)) 922 break; 923 if (nonblock) 924 return -EBUSY; 925 tmo = 1000 * count / s->dacRate / 2; 926 vrc5477_ac97_delay(tmo); 927 } 928 if (signal_pending(current)) 929 return -ERESTARTSYS; 930 return 0; 931} 932 933/* --------------------------------------------------------------------- */ 934 935static int inline 936copy_two_channel_adc_to_user(struct vrc5477_ac97_state *s, 937 char *buffer, 938 int copyCount) 939{ 940 struct dmabuf *db = &s->dma_adc; 941 int bufStart = db->nextOut; 942 for (; copyCount > 0; ) { 943 int i; 944 int count = copyCount; 945 if (count > WORK_BUF_SIZE/2) count = WORK_BUF_SIZE/2; 946 for (i=0; i< count/2; i++) { 947 s->workBuf[i].lchannel = 948 *(u16*)(db->lbuf + bufStart + i*2); 949 s->workBuf[i].rchannel = 950 *(u16*)(db->rbuf + bufStart + i*2); 951 } 952 if (copy_to_user(buffer, s->workBuf, count*2)) { 953 return -1; 954 } 955 956 copyCount -= count; 957 bufStart += count; 958 ASSERT(bufStart <= db->fragTotalSize); 959 buffer += count *2; 960 } 961 return 0; 962} 963 964/* return the total bytes that is copied */ 965static int inline 966copy_adc_to_user(struct vrc5477_ac97_state *s, 967 char * buffer, 968 size_t count, 969 int avail) 970{ 971 struct dmabuf *db = &s->dma_adc; 972 int copyCount=0; 973 int copyFragCount=0; 974 int totalCopyCount = 0; 975 int totalCopyFragCount = 0; 976 unsigned long flags; 977 978 /* adjust count to signel channel byte count */ 979 count >>= s->adcChannels - 1; 980 981 /* we may have to "copy" twice as ring buffer wraps around */ 982 for (; (avail > 0) && (count > 0); ) { 983 /* determine max possible copy count for single channel */ 984 copyCount = count; 985 if (copyCount > avail) { 986 copyCount = avail; 987 } 988 if (copyCount + db->nextOut > db->fragTotalSize) { 989 copyCount = db->fragTotalSize - db->nextOut; 990 ASSERT((copyCount % db->fragSize) == 0); 991 } 992 993 copyFragCount = (copyCount-1) >> db->fragShift; 994 copyFragCount = (copyFragCount+1) << db->fragShift; 995 ASSERT(copyFragCount >= copyCount); 996 997 /* we copy differently based on adc channels */ 998 if (s->adcChannels == 1) { 999 if (copy_to_user(buffer, 1000 db->lbuf + db->nextOut, 1001 copyCount)) 1002 return -1; 1003 } else { 1004 /* *sigh* we have to mix two streams into one */ 1005 if (copy_two_channel_adc_to_user(s, buffer, copyCount)) 1006 return -1; 1007 } 1008 1009 count -= copyCount; 1010 totalCopyCount += copyCount; 1011 avail -= copyFragCount; 1012 totalCopyFragCount += copyFragCount; 1013 1014 buffer += copyCount << (s->adcChannels-1); 1015 1016 db->nextOut += copyFragCount; 1017 if (db->nextOut >= db->fragTotalSize) { 1018 ASSERT(db->nextOut == db->fragTotalSize); 1019 db->nextOut = 0; 1020 } 1021 1022 ASSERT((copyFragCount % db->fragSize) == 0); 1023 ASSERT( (count == 0) || (copyCount == copyFragCount)); 1024 } 1025 1026 spin_lock_irqsave(&s->lock, flags); 1027 db->count -= totalCopyFragCount; 1028 spin_unlock_irqrestore(&s->lock, flags); 1029 1030 return totalCopyCount << (s->adcChannels-1); 1031} 1032 1033static ssize_t 1034vrc5477_ac97_read(struct file *file, 1035 char *buffer, 1036 size_t count, 1037 loff_t *ppos) 1038{ 1039 struct vrc5477_ac97_state *s = 1040 (struct vrc5477_ac97_state *)file->private_data; 1041 struct dmabuf *db = &s->dma_adc; 1042 ssize_t ret = 0; 1043 unsigned long flags; 1044 int copyCount; 1045 size_t avail; 1046 1047 if (ppos != &file->f_pos) 1048 return -ESPIPE; 1049 if (!access_ok(VERIFY_WRITE, buffer, count)) 1050 return -EFAULT; 1051 1052 ASSERT(db->ready); 1053 1054 while (count > 0) { 1055 // wait for samples in capture buffer 1056 do { 1057 spin_lock_irqsave(&s->lock, flags); 1058 if (db->stopped) 1059 start_adc(s); 1060 avail = db->count; 1061 spin_unlock_irqrestore(&s->lock, flags); 1062 if (avail <= 0) { 1063 if (file->f_flags & O_NONBLOCK) { 1064 if (!ret) 1065 ret = -EAGAIN; 1066 return ret; 1067 } 1068 interruptible_sleep_on(&db->wait); 1069 if (signal_pending(current)) { 1070 if (!ret) 1071 ret = -ERESTARTSYS; 1072 return ret; 1073 } 1074 } 1075 } while (avail <= 0); 1076 1077 ASSERT( (avail % db->fragSize) == 0); 1078 copyCount = copy_adc_to_user(s, buffer, count, avail); 1079 if (copyCount <=0 ) { 1080 if (!ret) ret = -EFAULT; 1081 return ret; 1082 } 1083 1084 count -= copyCount; 1085 buffer += copyCount; 1086 ret += copyCount; 1087 } // while (count > 0) 1088 1089 return ret; 1090} 1091 1092static int inline 1093copy_two_channel_dac_from_user(struct vrc5477_ac97_state *s, 1094 const char *buffer, 1095 int copyCount) 1096{ 1097 struct dmabuf *db = &s->dma_dac; 1098 int bufStart = db->nextIn; 1099 1100 ASSERT(db->ready); 1101 1102 for (; copyCount > 0; ) { 1103 int i; 1104 int count = copyCount; 1105 if (count > WORK_BUF_SIZE/2) count = WORK_BUF_SIZE/2; 1106 if (copy_from_user(s->workBuf, buffer, count*2)) { 1107 return -1; 1108 } 1109 for (i=0; i< count/2; i++) { 1110 *(u16*)(db->lbuf + bufStart + i*2) = 1111 s->workBuf[i].lchannel; 1112 *(u16*)(db->rbuf + bufStart + i*2) = 1113 s->workBuf[i].rchannel; 1114 } 1115 1116 copyCount -= count; 1117 bufStart += count; 1118 ASSERT(bufStart <= db->fragTotalSize); 1119 buffer += count *2; 1120 } 1121 return 0; 1122 1123} 1124 1125/* return the total bytes that is copied */ 1126static int inline 1127copy_dac_from_user(struct vrc5477_ac97_state *s, 1128 const char *buffer, 1129 size_t count, 1130 int avail) 1131{ 1132 struct dmabuf *db = &s->dma_dac; 1133 int copyCount=0; 1134 int copyFragCount=0; 1135 int totalCopyCount = 0; 1136 int totalCopyFragCount = 0; 1137 unsigned long flags; 1138#if defined(VRC5477_AC97_VERBOSE_DEBUG) 1139 int i; 1140#endif 1141 1142 /* adjust count to signel channel byte count */ 1143 count >>= s->dacChannels - 1; 1144 1145 /* we may have to "copy" twice as ring buffer wraps around */ 1146 for (; (avail > 0) && (count > 0); ) { 1147 /* determine max possible copy count for single channel */ 1148 copyCount = count; 1149 if (copyCount > avail) { 1150 copyCount = avail; 1151 } 1152 if (copyCount + db->nextIn > db->fragTotalSize) { 1153 copyCount = db->fragTotalSize - db->nextIn; 1154 ASSERT(copyCount > 0); 1155 } 1156 1157 copyFragCount = copyCount; 1158 ASSERT(copyFragCount >= copyCount); 1159 1160 /* we copy differently based on the number channels */ 1161 if (s->dacChannels == 1) { 1162 if (copy_from_user(db->lbuf + db->nextIn, 1163 buffer, 1164 copyCount)) 1165 return -1; 1166 /* fill gaps with 0 */ 1167 memset(db->lbuf + db->nextIn + copyCount, 1168 0, 1169 copyFragCount - copyCount); 1170 } else { 1171 /* we have demux the stream into two separate ones */ 1172 if (copy_two_channel_dac_from_user(s, buffer, copyCount)) 1173 return -1; 1174 /* fill gaps with 0 */ 1175 memset(db->lbuf + db->nextIn + copyCount, 1176 0, 1177 copyFragCount - copyCount); 1178 memset(db->rbuf + db->nextIn + copyCount, 1179 0, 1180 copyFragCount - copyCount); 1181 } 1182 1183#if defined(VRC5477_AC97_VERBOSE_DEBUG) 1184 for (i=0; i< copyFragCount; i+= db->fragSize) { 1185 *(u16*)(db->lbuf + db->nextIn + i) = inTicket ++; 1186 } 1187#endif 1188 1189 count -= copyCount; 1190 totalCopyCount =+ copyCount; 1191 avail -= copyFragCount; 1192 totalCopyFragCount += copyFragCount; 1193 1194 buffer += copyCount << (s->dacChannels - 1); 1195 1196 db->nextIn += copyFragCount; 1197 if (db->nextIn >= db->fragTotalSize) { 1198 ASSERT(db->nextIn == db->fragTotalSize); 1199 db->nextIn = 0; 1200 } 1201 1202 ASSERT( (count == 0) || (copyCount == copyFragCount)); 1203 } 1204 1205 spin_lock_irqsave(&s->lock, flags); 1206 db->count += totalCopyFragCount; 1207 if (db->stopped) { 1208 start_dac(s); 1209 } 1210 1211 /* nextIn should not be equal to nextOut unless we are full */ 1212 ASSERT( ( (db->count == db->fragTotalSize) && 1213 (db->nextIn == db->nextOut) ) || 1214 ( (db->count < db->fragTotalSize) && 1215 (db->nextIn != db->nextOut) ) ); 1216 1217 spin_unlock_irqrestore(&s->lock, flags); 1218 1219 return totalCopyCount << (s->dacChannels-1); 1220 1221} 1222 1223static ssize_t vrc5477_ac97_write(struct file *file, const char *buffer, 1224 size_t count, loff_t *ppos) 1225{ 1226 struct vrc5477_ac97_state *s = 1227 (struct vrc5477_ac97_state *)file->private_data; 1228 struct dmabuf *db = &s->dma_dac; 1229 ssize_t ret; 1230 unsigned long flags; 1231 int copyCount, avail; 1232 1233 if (ppos != &file->f_pos) 1234 return -ESPIPE; 1235 if (!access_ok(VERIFY_READ, buffer, count)) 1236 return -EFAULT; 1237 ret = 0; 1238 1239 while (count > 0) { 1240 // wait for space in playback buffer 1241 do { 1242 spin_lock_irqsave(&s->lock, flags); 1243 avail = db->fragTotalSize - db->count; 1244 spin_unlock_irqrestore(&s->lock, flags); 1245 if (avail <= 0) { 1246 if (file->f_flags & O_NONBLOCK) { 1247 if (!ret) 1248 ret = -EAGAIN; 1249 return ret; 1250 } 1251 interruptible_sleep_on(&db->wait); 1252 if (signal_pending(current)) { 1253 if (!ret) 1254 ret = -ERESTARTSYS; 1255 return ret; 1256 } 1257 } 1258 } while (avail <= 0); 1259 1260 copyCount = copy_dac_from_user(s, buffer, count, avail); 1261 if (copyCount < 0) { 1262 if (!ret) ret = -EFAULT; 1263 return ret; 1264 } 1265 1266 count -= copyCount; 1267 buffer += copyCount; 1268 ret += copyCount; 1269 } // while (count > 0) 1270 1271 return ret; 1272} 1273 1274/* No kernel lock - we have our own spinlock */ 1275static unsigned int vrc5477_ac97_poll(struct file *file, 1276 struct poll_table_struct *wait) 1277{ 1278 struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)file->private_data; 1279 unsigned long flags; 1280 unsigned int mask = 0; 1281 1282 if (file->f_mode & FMODE_WRITE) 1283 poll_wait(file, &s->dma_dac.wait, wait); 1284 if (file->f_mode & FMODE_READ) 1285 poll_wait(file, &s->dma_adc.wait, wait); 1286 spin_lock_irqsave(&s->lock, flags); 1287 if (file->f_mode & FMODE_READ) { 1288 if (s->dma_adc.count >= (signed)s->dma_adc.fragSize) 1289 mask |= POLLIN | POLLRDNORM; 1290 } 1291 if (file->f_mode & FMODE_WRITE) { 1292 if ((signed)s->dma_dac.fragTotalSize >= 1293 s->dma_dac.count + (signed)s->dma_dac.fragSize) 1294 mask |= POLLOUT | POLLWRNORM; 1295 } 1296 spin_unlock_irqrestore(&s->lock, flags); 1297 return mask; 1298} 1299 1300#ifdef VRC5477_AC97_DEBUG 1301static struct ioctl_str_t { 1302 unsigned int cmd; 1303 const char* str; 1304} ioctl_str[] = { 1305 {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"}, 1306 {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"}, 1307 {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"}, 1308 {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"}, 1309 {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"}, 1310 {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"}, 1311 {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"}, 1312 {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"}, 1313 {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"}, 1314 {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"}, 1315 {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"}, 1316 {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"}, 1317 {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"}, 1318 {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"}, 1319 {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"}, 1320 {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"}, 1321 {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"}, 1322 {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"}, 1323 {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"}, 1324 {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"}, 1325 {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"}, 1326 {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"}, 1327 {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"}, 1328 {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"}, 1329 {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"}, 1330 {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"}, 1331 {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"}, 1332 {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"}, 1333 {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"}, 1334 {OSS_GETVERSION, "OSS_GETVERSION"}, 1335 {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"}, 1336 {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"}, 1337 {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"}, 1338 {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"} 1339}; 1340#endif 1341 1342static int vrc5477_ac97_ioctl(struct inode *inode, struct file *file, 1343 unsigned int cmd, unsigned long arg) 1344{ 1345 struct vrc5477_ac97_state *s = (struct vrc5477_ac97_state *)file->private_data; 1346 unsigned long flags; 1347 audio_buf_info abinfo; 1348 int count; 1349 int val, ret; 1350 1351#ifdef VRC5477_AC97_DEBUG 1352 for (count=0; count<sizeof(ioctl_str)/sizeof(ioctl_str[0]); count++) { 1353 if (ioctl_str[count].cmd == cmd) 1354 break; 1355 } 1356 if (count < sizeof(ioctl_str)/sizeof(ioctl_str[0])) 1357 printk(KERN_INFO PFX "ioctl %s\n", ioctl_str[count].str); 1358 else 1359 printk(KERN_INFO PFX "ioctl unknown, 0x%x\n", cmd); 1360#endif 1361 1362 switch (cmd) { 1363 case OSS_GETVERSION: 1364 return put_user(SOUND_VERSION, (int *)arg); 1365 1366 case SNDCTL_DSP_SYNC: 1367 if (file->f_mode & FMODE_WRITE) 1368 return drain_dac(s, file->f_flags & O_NONBLOCK); 1369 return 0; 1370 1371 case SNDCTL_DSP_SETDUPLEX: 1372 return 0; 1373 1374 case SNDCTL_DSP_GETCAPS: 1375 return put_user(DSP_CAP_DUPLEX, (int *)arg); 1376 1377 case SNDCTL_DSP_RESET: 1378 if (file->f_mode & FMODE_WRITE) { 1379 stop_dac(s); 1380 synchronize_irq(); 1381 s->dma_dac.count = 0; 1382 s->dma_dac.nextIn = s->dma_dac.nextOut = 0; 1383 } 1384 if (file->f_mode & FMODE_READ) { 1385 stop_adc(s); 1386 synchronize_irq(); 1387 s->dma_adc.count = 0; 1388 s->dma_adc.nextIn = s->dma_adc.nextOut = 0; 1389 } 1390 return 0; 1391 1392 case SNDCTL_DSP_SPEED: 1393 if (get_user(val, (int *)arg)) 1394 return -EFAULT; 1395 if (val >= 0) { 1396 if (file->f_mode & FMODE_READ) { 1397 stop_adc(s); 1398 set_adc_rate(s, val); 1399 if ((ret = prog_dmabuf_adc(s))) 1400 return ret; 1401 } 1402 if (file->f_mode & FMODE_WRITE) { 1403 stop_dac(s); 1404 set_dac_rate(s, val); 1405 if ((ret = prog_dmabuf_dac(s))) 1406 return ret; 1407 } 1408 } 1409 return put_user((file->f_mode & FMODE_READ) ? 1410 s->adcRate : s->dacRate, (int *)arg); 1411 1412 case SNDCTL_DSP_STEREO: 1413 if (get_user(val, (int *)arg)) 1414 return -EFAULT; 1415 if (file->f_mode & FMODE_READ) { 1416 stop_adc(s); 1417 if (val) 1418 s->adcChannels = 2; 1419 else 1420 s->adcChannels = 1; 1421 if ((ret = prog_dmabuf_adc(s))) 1422 return ret; 1423 } 1424 if (file->f_mode & FMODE_WRITE) { 1425 stop_dac(s); 1426 if (val) 1427 s->dacChannels = 2; 1428 else 1429 s->dacChannels = 1; 1430 if ((ret = prog_dmabuf_dac(s))) 1431 return ret; 1432 } 1433 return 0; 1434 1435 case SNDCTL_DSP_CHANNELS: 1436 if (get_user(val, (int *)arg)) 1437 return -EFAULT; 1438 if (val != 0) { 1439 if ( (val != 1) && (val != 2)) val = 2; 1440 1441 if (file->f_mode & FMODE_READ) { 1442 stop_adc(s); 1443 s->dacChannels = val; 1444 if ((ret = prog_dmabuf_adc(s))) 1445 return ret; 1446 } 1447 if (file->f_mode & FMODE_WRITE) { 1448 stop_dac(s); 1449 s->dacChannels = val; 1450 if ((ret = prog_dmabuf_dac(s))) 1451 return ret; 1452 } 1453 } 1454 return put_user(val, (int *)arg); 1455 1456 case SNDCTL_DSP_GETFMTS: /* Returns a mask */ 1457 return put_user(AFMT_S16_LE, (int *)arg); 1458 1459 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/ 1460 if (get_user(val, (int *)arg)) 1461 return -EFAULT; 1462 if (val != AFMT_QUERY) { 1463 if (val != AFMT_S16_LE) return -EINVAL; 1464 if (file->f_mode & FMODE_READ) { 1465 stop_adc(s); 1466 if ((ret = prog_dmabuf_adc(s))) 1467 return ret; 1468 } 1469 if (file->f_mode & FMODE_WRITE) { 1470 stop_dac(s); 1471 if ((ret = prog_dmabuf_dac(s))) 1472 return ret; 1473 } 1474 } else { 1475 val = AFMT_S16_LE; 1476 } 1477 return put_user(val, (int *)arg); 1478 1479 case SNDCTL_DSP_POST: 1480 return 0; 1481 1482 case SNDCTL_DSP_GETTRIGGER: 1483 case SNDCTL_DSP_SETTRIGGER: 1484 /* NO trigger */ 1485 return -EINVAL; 1486 1487 case SNDCTL_DSP_GETOSPACE: 1488 if (!(file->f_mode & FMODE_WRITE)) 1489 return -EINVAL; 1490 abinfo.fragsize = s->dma_dac.fragSize << (s->dacChannels-1); 1491 spin_lock_irqsave(&s->lock, flags); 1492 count = s->dma_dac.count; 1493 spin_unlock_irqrestore(&s->lock, flags); 1494 abinfo.bytes = (s->dma_dac.fragTotalSize - count) << 1495 (s->dacChannels-1); 1496 abinfo.fragstotal = s->dma_dac.numFrag; 1497 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragShift >> 1498 (s->dacChannels-1); 1499 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; 1500 1501 case SNDCTL_DSP_GETISPACE: 1502 if (!(file->f_mode & FMODE_READ)) 1503 return -EINVAL; 1504 abinfo.fragsize = s->dma_adc.fragSize << (s->adcChannels-1); 1505 spin_lock_irqsave(&s->lock, flags); 1506 count = s->dma_adc.count; 1507 spin_unlock_irqrestore(&s->lock, flags); 1508 if (count < 0) 1509 count = 0; 1510 abinfo.bytes = count << (s->adcChannels-1); 1511 abinfo.fragstotal = s->dma_adc.numFrag; 1512 abinfo.fragments = (abinfo.bytes >> s->dma_adc.fragShift) >> 1513 (s->adcChannels-1); 1514 return copy_to_user((void *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0; 1515 1516 case SNDCTL_DSP_NONBLOCK: 1517 file->f_flags |= O_NONBLOCK; 1518 return 0; 1519 1520 case SNDCTL_DSP_GETODELAY: 1521 if (!(file->f_mode & FMODE_WRITE)) 1522 return -EINVAL; 1523 spin_lock_irqsave(&s->lock, flags); 1524 count = s->dma_dac.count; 1525 spin_unlock_irqrestore(&s->lock, flags); 1526 return put_user(count, (int *)arg); 1527 1528 case SNDCTL_DSP_GETIPTR: 1529 case SNDCTL_DSP_GETOPTR: 1530 /* we cannot get DMA ptr */ 1531 return -EINVAL; 1532 1533 case SNDCTL_DSP_GETBLKSIZE: 1534 if (file->f_mode & FMODE_WRITE) 1535 return put_user(s->dma_dac.fragSize << (s->dacChannels-1), (int *)arg); 1536 else 1537 return put_user(s->dma_adc.fragSize << (s->adcChannels-1), (int *)arg); 1538 1539 case SNDCTL_DSP_SETFRAGMENT: 1540 /* we ignore fragment size request */ 1541 return 0; 1542 1543 case SNDCTL_DSP_SUBDIVIDE: 1544 /* what is this for? [jsun] */ 1545 return 0; 1546 1547 case SOUND_PCM_READ_RATE: 1548 return put_user((file->f_mode & FMODE_READ) ? 1549 s->adcRate : s->dacRate, (int *)arg); 1550 1551 case SOUND_PCM_READ_CHANNELS: 1552 if (file->f_mode & FMODE_READ) 1553 return put_user(s->adcChannels, (int *)arg); 1554 else 1555 return put_user(s->dacChannels ? 2 : 1, (int *)arg); 1556 1557 case SOUND_PCM_READ_BITS: 1558 return put_user(16, (int *)arg); 1559 1560 case SOUND_PCM_WRITE_FILTER: 1561 case SNDCTL_DSP_SETSYNCRO: 1562 case SOUND_PCM_READ_FILTER: 1563 return -EINVAL; 1564 } 1565 1566 return mixdev_ioctl(&s->codec, cmd, arg); 1567} 1568 1569 1570static int vrc5477_ac97_open(struct inode *inode, struct file *file) 1571{ 1572 int minor = MINOR(inode->i_rdev); 1573 DECLARE_WAITQUEUE(wait, current); 1574 unsigned long flags; 1575 struct list_head *list; 1576 struct vrc5477_ac97_state *s; 1577 int ret=0; 1578 1579 for (list = devs.next; ; list = list->next) { 1580 if (list == &devs) 1581 return -ENODEV; 1582 s = list_entry(list, struct vrc5477_ac97_state, devs); 1583 if (!((s->dev_audio ^ minor) & ~0xf)) 1584 break; 1585 } 1586 file->private_data = s; 1587 1588 /* wait for device to become free */ 1589 down(&s->open_sem); 1590 while (s->open_mode & file->f_mode) { 1591 1592 if (file->f_flags & O_NONBLOCK) { 1593 up(&s->open_sem); 1594 return -EBUSY; 1595 } 1596 add_wait_queue(&s->open_wait, &wait); 1597 __set_current_state(TASK_INTERRUPTIBLE); 1598 up(&s->open_sem); 1599 schedule(); 1600 remove_wait_queue(&s->open_wait, &wait); 1601 set_current_state(TASK_RUNNING); 1602 if (signal_pending(current)) 1603 return -ERESTARTSYS; 1604 down(&s->open_sem); 1605 } 1606 1607 spin_lock_irqsave(&s->lock, flags); 1608 1609 if (file->f_mode & FMODE_READ) { 1610 /* set default settings */ 1611 set_adc_rate(s, 48000); 1612 s->adcChannels = 2; 1613 1614 ret = prog_dmabuf_adc(s); 1615 if (ret) goto bailout; 1616 } 1617 if (file->f_mode & FMODE_WRITE) { 1618 /* set default settings */ 1619 set_dac_rate(s, 48000); 1620 s->dacChannels = 2; 1621 1622 ret = prog_dmabuf_dac(s); 1623 if (ret) goto bailout; 1624 } 1625 1626 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); 1627 1628 bailout: 1629 spin_unlock_irqrestore(&s->lock, flags); 1630 1631 up(&s->open_sem); 1632 return ret; 1633} 1634 1635static int vrc5477_ac97_release(struct inode *inode, struct file *file) 1636{ 1637 struct vrc5477_ac97_state *s = 1638 (struct vrc5477_ac97_state *)file->private_data; 1639 1640 lock_kernel(); 1641 if (file->f_mode & FMODE_WRITE) 1642 drain_dac(s, file->f_flags & O_NONBLOCK); 1643 down(&s->open_sem); 1644 if (file->f_mode & FMODE_WRITE) { 1645 stop_dac(s); 1646 dealloc_dmabuf(s, &s->dma_dac); 1647 } 1648 if (file->f_mode & FMODE_READ) { 1649 stop_adc(s); 1650 dealloc_dmabuf(s, &s->dma_adc); 1651 } 1652 s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE); 1653 up(&s->open_sem); 1654 wake_up(&s->open_wait); 1655 unlock_kernel(); 1656 return 0; 1657} 1658 1659static /*const*/ struct file_operations vrc5477_ac97_audio_fops = { 1660 owner: THIS_MODULE, 1661 llseek: no_llseek, 1662 read: vrc5477_ac97_read, 1663 write: vrc5477_ac97_write, 1664 poll: vrc5477_ac97_poll, 1665 ioctl: vrc5477_ac97_ioctl, 1666 // mmap: vrc5477_ac97_mmap, 1667 open: vrc5477_ac97_open, 1668 release: vrc5477_ac97_release, 1669}; 1670 1671 1672/* --------------------------------------------------------------------- */ 1673 1674 1675/* --------------------------------------------------------------------- */ 1676 1677/* 1678 * for debugging purposes, we'll create a proc device that dumps the 1679 * CODEC chipstate 1680 */ 1681 1682#ifdef VRC5477_AC97_DEBUG 1683 1684struct { 1685 const char *regname; 1686 unsigned regaddr; 1687} vrc5477_ac97_regs[] = { 1688 {"VRC5477_INT_STATUS", VRC5477_INT_STATUS}, 1689 {"VRC5477_CODEC_WR", VRC5477_CODEC_WR}, 1690 {"VRC5477_CODEC_RD", VRC5477_CODEC_RD}, 1691 {"VRC5477_CTRL", VRC5477_CTRL}, 1692 {"VRC5477_ACLINK_CTRL", VRC5477_ACLINK_CTRL}, 1693 {"VRC5477_INT_MASK", VRC5477_INT_MASK}, 1694 {"VRC5477_DAC1_CTRL", VRC5477_DAC1_CTRL}, 1695 {"VRC5477_DAC1L", VRC5477_DAC1L}, 1696 {"VRC5477_DAC1_BADDR", VRC5477_DAC1_BADDR}, 1697 {"VRC5477_DAC2_CTRL", VRC5477_DAC2_CTRL}, 1698 {"VRC5477_DAC2L", VRC5477_DAC2L}, 1699 {"VRC5477_DAC2_BADDR", VRC5477_DAC2_BADDR}, 1700 {"VRC5477_DAC3_CTRL", VRC5477_DAC3_CTRL}, 1701 {"VRC5477_DAC3L", VRC5477_DAC3L}, 1702 {"VRC5477_DAC3_BADDR", VRC5477_DAC3_BADDR}, 1703 {"VRC5477_ADC1_CTRL", VRC5477_ADC1_CTRL}, 1704 {"VRC5477_ADC1L", VRC5477_ADC1L}, 1705 {"VRC5477_ADC1_BADDR", VRC5477_ADC1_BADDR}, 1706 {"VRC5477_ADC2_CTRL", VRC5477_ADC2_CTRL}, 1707 {"VRC5477_ADC2L", VRC5477_ADC2L}, 1708 {"VRC5477_ADC2_BADDR", VRC5477_ADC2_BADDR}, 1709 {"VRC5477_ADC3_CTRL", VRC5477_ADC3_CTRL}, 1710 {"VRC5477_ADC3L", VRC5477_ADC3L}, 1711 {"VRC5477_ADC3_BADDR", VRC5477_ADC3_BADDR}, 1712 {NULL, 0x0} 1713}; 1714 1715static int proc_vrc5477_ac97_dump (char *buf, char **start, off_t fpos, 1716 int length, int *eof, void *data) 1717{ 1718 struct vrc5477_ac97_state *s; 1719 int cnt, len = 0; 1720 1721 if (list_empty(&devs)) 1722 return 0; 1723 s = list_entry(devs.next, struct vrc5477_ac97_state, devs); 1724 1725 /* print out header */ 1726 len += sprintf(buf + len, "\n\t\tVrc5477 Audio Debug\n\n"); 1727 1728 // print out digital controller state 1729 len += sprintf (buf + len, "NEC Vrc5477 Audio Controller registers\n"); 1730 len += sprintf (buf + len, "---------------------------------\n"); 1731 for (cnt=0; vrc5477_ac97_regs[cnt].regname != NULL; cnt++) { 1732 len+= sprintf (buf + len, "%-20s = %08x\n", 1733 vrc5477_ac97_regs[cnt].regname, 1734 inl(s->io + vrc5477_ac97_regs[cnt].regaddr)); 1735 } 1736 1737 /* print out driver state */ 1738 len += sprintf (buf + len, "NEC Vrc5477 Audio driver states\n"); 1739 len += sprintf (buf + len, "---------------------------------\n"); 1740 len += sprintf (buf + len, "dacChannels = %d\n", s->dacChannels); 1741 len += sprintf (buf + len, "adcChannels = %d\n", s->adcChannels); 1742 len += sprintf (buf + len, "dacRate = %d\n", s->dacRate); 1743 len += sprintf (buf + len, "adcRate = %d\n", s->adcRate); 1744 1745 len += sprintf (buf + len, "dma_dac is %s ready\n", 1746 s->dma_dac.ready? "" : "not"); 1747 if (s->dma_dac.ready) { 1748 len += sprintf (buf + len, "dma_dac is %s stopped.\n", 1749 s->dma_dac.stopped? "" : "not"); 1750 len += sprintf (buf + len, "dma_dac.fragSize = %x\n", 1751 s->dma_dac.fragSize); 1752 len += sprintf (buf + len, "dma_dac.fragShift = %x\n", 1753 s->dma_dac.fragShift); 1754 len += sprintf (buf + len, "dma_dac.numFrag = %x\n", 1755 s->dma_dac.numFrag); 1756 len += sprintf (buf + len, "dma_dac.fragTotalSize = %x\n", 1757 s->dma_dac.fragTotalSize); 1758 len += sprintf (buf + len, "dma_dac.nextIn = %x\n", 1759 s->dma_dac.nextIn); 1760 len += sprintf (buf + len, "dma_dac.nextOut = %x\n", 1761 s->dma_dac.nextOut); 1762 len += sprintf (buf + len, "dma_dac.count = %x\n", 1763 s->dma_dac.count); 1764 } 1765 1766 len += sprintf (buf + len, "dma_adc is %s ready\n", 1767 s->dma_adc.ready? "" : "not"); 1768 if (s->dma_adc.ready) { 1769 len += sprintf (buf + len, "dma_adc is %s stopped.\n", 1770 s->dma_adc.stopped? "" : "not"); 1771 len += sprintf (buf + len, "dma_adc.fragSize = %x\n", 1772 s->dma_adc.fragSize); 1773 len += sprintf (buf + len, "dma_adc.fragShift = %x\n", 1774 s->dma_adc.fragShift); 1775 len += sprintf (buf + len, "dma_adc.numFrag = %x\n", 1776 s->dma_adc.numFrag); 1777 len += sprintf (buf + len, "dma_adc.fragTotalSize = %x\n", 1778 s->dma_adc.fragTotalSize); 1779 len += sprintf (buf + len, "dma_adc.nextIn = %x\n", 1780 s->dma_adc.nextIn); 1781 len += sprintf (buf + len, "dma_adc.nextOut = %x\n", 1782 s->dma_adc.nextOut); 1783 len += sprintf (buf + len, "dma_adc.count = %x\n", 1784 s->dma_adc.count); 1785 } 1786 1787 /* print out CODEC state */ 1788 len += sprintf (buf + len, "\nAC97 CODEC registers\n"); 1789 len += sprintf (buf + len, "----------------------\n"); 1790 for (cnt=0; cnt <= 0x7e; cnt = cnt +2) 1791 len+= sprintf (buf + len, "reg %02x = %04x\n", 1792 cnt, rdcodec(&s->codec, cnt)); 1793 1794 if (fpos >=len){ 1795 *start = buf; 1796 *eof =1; 1797 return 0; 1798 } 1799 *start = buf + fpos; 1800 if ((len -= fpos) > length) 1801 return length; 1802 *eof =1; 1803 return len; 1804 1805} 1806#endif /* VRC5477_AC97_DEBUG */ 1807 1808/* --------------------------------------------------------------------- */ 1809 1810/* maximum number of devices; only used for command line params */ 1811#define NR_DEVICE 5 1812 1813static unsigned int devindex = 0; 1814 1815MODULE_AUTHOR("Monta Vista Software, jsun@mvista.com or jsun@junsun.net"); 1816MODULE_DESCRIPTION("NEC Vrc5477 audio (AC97) Driver"); 1817MODULE_LICENSE("GPL"); 1818 1819static int __devinit vrc5477_ac97_probe(struct pci_dev *pcidev, 1820 const struct pci_device_id *pciid) 1821{ 1822 struct vrc5477_ac97_state *s; 1823#ifdef VRC5477_AC97_DEBUG 1824 char proc_str[80]; 1825#endif 1826 1827 if (pcidev->irq == 0) 1828 return -1; 1829 1830 if (!(s = kmalloc(sizeof(struct vrc5477_ac97_state), GFP_KERNEL))) { 1831 printk(KERN_ERR PFX "alloc of device struct failed\n"); 1832 return -1; 1833 } 1834 memset(s, 0, sizeof(struct vrc5477_ac97_state)); 1835 1836 init_waitqueue_head(&s->dma_adc.wait); 1837 init_waitqueue_head(&s->dma_dac.wait); 1838 init_waitqueue_head(&s->open_wait); 1839 init_MUTEX(&s->open_sem); 1840 spin_lock_init(&s->lock); 1841 1842 s->dev = pcidev; 1843 s->io = pci_resource_start(pcidev, 0); 1844 s->irq = pcidev->irq; 1845 1846 s->codec.private_data = s; 1847 s->codec.id = 0; 1848 s->codec.codec_read = rdcodec; 1849 s->codec.codec_write = wrcodec; 1850 s->codec.codec_wait = waitcodec; 1851 1852 /* setting some other default values such as 1853 * adcChannels, adcRate is done in open() so that 1854 * no persistent state across file opens. 1855 */ 1856 1857 /* test if get response from ac97, if not return */ 1858 if (ac97_codec_not_present(&(s->codec))) { 1859 printk(KERN_ERR PFX "no ac97 codec\n"); 1860 goto err_region; 1861 1862 } 1863 1864 if (!request_region(s->io, pci_resource_len(pcidev,0), 1865 VRC5477_AC97_MODULE_NAME)) { 1866 printk(KERN_ERR PFX "io ports %#lx->%#lx in use\n", 1867 s->io, s->io + pci_resource_len(pcidev,0)-1); 1868 goto err_region; 1869 } 1870 if (request_irq(s->irq, vrc5477_ac97_interrupt, SA_INTERRUPT, 1871 VRC5477_AC97_MODULE_NAME, s)) { 1872 printk(KERN_ERR PFX "irq %u in use\n", s->irq); 1873 goto err_irq; 1874 } 1875 1876 printk(KERN_INFO PFX "IO at %#lx, IRQ %d\n", s->io, s->irq); 1877 1878 /* register devices */ 1879 if ((s->dev_audio = register_sound_dsp(&vrc5477_ac97_audio_fops, -1)) < 0) 1880 goto err_dev1; 1881 if ((s->codec.dev_mixer = 1882 register_sound_mixer(&vrc5477_ac97_mixer_fops, -1)) < 0) 1883 goto err_dev2; 1884 1885#ifdef VRC5477_AC97_DEBUG 1886 /* intialize the debug proc device */ 1887 s->ps = create_proc_read_entry(VRC5477_AC97_MODULE_NAME, 0, NULL, 1888 proc_vrc5477_ac97_dump, NULL); 1889#endif /* VRC5477_AC97_DEBUG */ 1890 1891 /* enable pci io and bus mastering */ 1892 if (pci_enable_device(pcidev)) 1893 goto err_dev3; 1894 pci_set_master(pcidev); 1895 1896 /* cold reset the AC97 */ 1897 outl(VRC5477_ACLINK_CTRL_RST_ON | VRC5477_ACLINK_CTRL_RST_TIME, 1898 s->io + VRC5477_ACLINK_CTRL); 1899 while (inl(s->io + VRC5477_ACLINK_CTRL) & VRC5477_ACLINK_CTRL_RST_ON); 1900 1901 /* codec init */ 1902 if (!ac97_probe_codec(&s->codec)) 1903 goto err_dev3; 1904 1905#ifdef VRC5477_AC97_DEBUG 1906 sprintf(proc_str, "driver/%s/%d/ac97", 1907 VRC5477_AC97_MODULE_NAME, s->codec.id); 1908 s->ac97_ps = create_proc_read_entry (proc_str, 0, NULL, 1909 ac97_read_proc, &s->codec); 1910 /* TODO : why this proc file does not show up? */ 1911#endif 1912 1913 /* Try to enable variable rate audio mode. */ 1914 wrcodec(&s->codec, AC97_EXTENDED_STATUS, 1915 rdcodec(&s->codec, AC97_EXTENDED_STATUS) | AC97_EXTSTAT_VRA); 1916 /* Did we enable it? */ 1917 if(rdcodec(&s->codec, AC97_EXTENDED_STATUS) & AC97_EXTSTAT_VRA) 1918 s->extended_status |= AC97_EXTSTAT_VRA; 1919 else { 1920 s->dacRate = 48000; 1921 printk(KERN_INFO PFX "VRA mode not enabled; rate fixed at %d.", 1922 s->dacRate); 1923 } 1924 1925 /* let us get the default volumne louder */ 1926 wrcodec(&s->codec, 0x2, 0x1010); /* master volume, middle */ 1927 wrcodec(&s->codec, 0xc, 0x10); /* phone volume, middle */ 1928 // wrcodec(&s->codec, 0xe, 0x10); /* misc volume, middle */ 1929 wrcodec(&s->codec, 0x10, 0x8000); /* line-in 2 line-out disable */ 1930 wrcodec(&s->codec, 0x18, 0x0707); /* PCM out (line out) middle */ 1931 1932 1933 /* by default we select line in the input */ 1934 wrcodec(&s->codec, 0x1a, 0x0404); 1935 wrcodec(&s->codec, 0x1c, 0x0f0f); 1936 wrcodec(&s->codec, 0x1e, 0x07); 1937 1938 /* enable the master interrupt but disable all others */ 1939 outl(VRC5477_INT_MASK_NMASK, s->io + VRC5477_INT_MASK); 1940 1941 /* store it in the driver field */ 1942 pci_set_drvdata(pcidev, s); 1943 pcidev->dma_mask = 0xffffffff; 1944 /* put it into driver list */ 1945 list_add_tail(&s->devs, &devs); 1946 /* increment devindex */ 1947 if (devindex < NR_DEVICE-1) 1948 devindex++; 1949 return 0; 1950 1951 err_dev3: 1952 unregister_sound_mixer(s->codec.dev_mixer); 1953 err_dev2: 1954 unregister_sound_dsp(s->dev_audio); 1955 err_dev1: 1956 printk(KERN_ERR PFX "cannot register misc device\n"); 1957 free_irq(s->irq, s); 1958 err_irq: 1959 release_region(s->io, pci_resource_len(pcidev,0)); 1960 err_region: 1961 kfree(s); 1962 return -1; 1963} 1964 1965static void __devinit vrc5477_ac97_remove(struct pci_dev *dev) 1966{ 1967 struct vrc5477_ac97_state *s = pci_get_drvdata(dev); 1968 1969 if (!s) 1970 return; 1971 list_del(&s->devs); 1972 1973#ifdef VRC5477_AC97_DEBUG 1974 if (s->ps) 1975 remove_proc_entry(VRC5477_AC97_MODULE_NAME, NULL); 1976#endif /* VRC5477_AC97_DEBUG */ 1977 1978 synchronize_irq(); 1979 free_irq(s->irq, s); 1980 release_region(s->io, pci_resource_len(dev,0)); 1981 unregister_sound_dsp(s->dev_audio); 1982 unregister_sound_mixer(s->codec.dev_mixer); 1983 kfree(s); 1984 pci_set_drvdata(dev, NULL); 1985} 1986 1987 1988static struct pci_device_id id_table[] __devinitdata = { 1989 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_VRC5477_AC97, 1990 PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 1991 { 0, } 1992}; 1993 1994MODULE_DEVICE_TABLE(pci, id_table); 1995 1996static struct pci_driver vrc5477_ac97_driver = { 1997 name: VRC5477_AC97_MODULE_NAME, 1998 id_table: id_table, 1999 probe: vrc5477_ac97_probe, 2000 remove: vrc5477_ac97_remove 2001}; 2002 2003static int __init init_vrc5477_ac97(void) 2004{ 2005 if (!pci_present()) /* No PCI bus in this machine! */ 2006 return -ENODEV; 2007 printk("Vrc5477 AC97 driver: version v0.2 time " __TIME__ " " __DATE__ " by Jun Sun\n"); 2008 return pci_module_init(&vrc5477_ac97_driver); 2009} 2010 2011static void __exit cleanup_vrc5477_ac97(void) 2012{ 2013 printk(KERN_INFO PFX "unloading\n"); 2014 pci_unregister_driver(&vrc5477_ac97_driver); 2015} 2016 2017module_init(init_vrc5477_ac97); 2018module_exit(cleanup_vrc5477_ac97); 2019 2020