1#ifndef __HAL2_H 2#define __HAL2_H 3 4/* 5 * Driver for HAL2 sound processors 6 * Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se> 7 * Copyright (c) 2001 Ladislav Michl <ladis@psi.cz> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 */ 23 24#include <asm/addrspace.h> 25#include <asm/sgi/sgihpc.h> 26#include <linux/spinlock.h> 27#include <linux/types.h> 28 29#define H2_HAL2_BASE 0x58000 30#define H2_CTL_PIO (H2_HAL2_BASE + 0 * 0x400) 31#define H2_AES_PIO (H2_HAL2_BASE + 1 * 0x400) 32#define H2_VOL_PIO (H2_HAL2_BASE + 2 * 0x400) 33#define H2_SYN_PIO (H2_HAL2_BASE + 3 * 0x400) 34 35/* Indirect status register */ 36 37#define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */ 38#define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */ 39#define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */ 40#define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */ 41#define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */ 42 43/* Revision register */ 44 45#define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */ 46#define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */ 47#define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */ 48#define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */ 49 50/* Indirect address register */ 51 52/* 53 * Address of indirect internal register to be accessed. A write to this 54 * register initiates read or write access to the indirect registers in the 55 * HAL2. Note that there af four indirect data registers for write access to 56 * registers larger than 16 byte. 57 */ 58 59#define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */ 60 /* block the register resides in */ 61 /* 1=DMA Port */ 62 /* 9=Global DMA Control */ 63 /* 2=Bresenham */ 64 /* 3=Unix Timer */ 65#define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */ 66 /* blockin which the indirect */ 67 /* register resides */ 68 /* If IAR_TYPE_M=DMA Port: */ 69 /* 1=Synth In */ 70 /* 2=AES In */ 71 /* 3=AES Out */ 72 /* 4=DAC Out */ 73 /* 5=ADC Out */ 74 /* 6=Synth Control */ 75 /* If IAR_TYPE_M=Global DMA Control: */ 76 /* 1=Control */ 77 /* If IAR_TYPE_M=Bresenham: */ 78 /* 1=Bresenham Clock Gen 1 */ 79 /* 2=Bresenham Clock Gen 2 */ 80 /* 3=Bresenham Clock Gen 3 */ 81 /* If IAR_TYPE_M=Unix Timer: */ 82 /* 1=Unix Timer */ 83#define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */ 84#define H2_IAR_PARAM 0x000C /* Parameter Select */ 85#define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */ 86 /* 00:word0 */ 87 /* 01:word1 */ 88 /* 10:word2 */ 89 /* 11:word3 */ 90/* 91 * HAL2 internal addressing 92 * 93 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the 94 * Indirect Data registers. Write the address to the Indirect Address register 95 * to transfer the data. 96 * 97 * We define the H2IR_* to the read address and H2IW_* to the write address and 98 * H2I_* to be fields in whatever register is referred to. 99 * 100 * When we write to indirect registers which are larger than one word (16 bit) 101 * we have to fill more than one indirect register before writing. When we read 102 * back however we have to read several times, each time with different Read 103 * Back Indexes (there are defs for doing this easily). 104 */ 105 106/* 107 * Relay Control 108 */ 109#define H2I_RELAY_C 0x9100 110#define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */ 111 112/* DMA port enable */ 113 114#define H2I_DMA_PORT_EN 0x9104 115#define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */ 116#define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */ 117#define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */ 118#define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */ 119#define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */ 120 121#define H2I_DMA_END 0x9108 /* global dma endian select */ 122#define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */ 123#define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */ 124#define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */ 125#define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */ 126#define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */ 127 /* 0=b_end 1=l_end */ 128 129#define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */ 130 131#define H2I_SYNTH_C 0x1104 /* Synth DMA control */ 132 133#define H2I_AESRX_C 0x1204 /* AES RX dma control */ 134 135#define H2I_C_TS_EN 0x20 /* Timestamp enable */ 136#define H2I_C_TS_FRMT 0x40 /* Timestamp format */ 137#define H2I_C_NAUDIO 0x80 /* Sign extend */ 138 139/* AESRX CTL, 16 bit */ 140 141#define H2I_AESTX_C 0x1304 /* AES TX DMA control */ 142#define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */ 143#define H2I_AESTX_C_CLKID_M 0x18 144#define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */ 145#define H2I_AESTX_C_DATAT_M 0x300 146 147/* CODEC registers */ 148 149#define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */ 150#define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */ 151#define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */ 152#define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */ 153 154/* Bits in CTL1 register */ 155 156#define H2I_C1_DMA_SHIFT 0 /* DMA channel */ 157#define H2I_C1_DMA_M 0x7 158#define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */ 159#define H2I_C1_CLKID_M 0x18 160#define H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */ 161#define H2I_C1_DATAT_M 0x300 162 163/* Bits in CTL2 register */ 164 165#define H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */ 166#define H2I_C2_R_GAIN_M 0xf 167#define H2I_C2_L_GAIN_SHIFT 4 /* left a/d input gain */ 168#define H2I_C2_L_GAIN_M 0xf0 169#define H2I_C2_R_SEL 0x100 /* right input select */ 170#define H2I_C2_L_SEL 0x200 /* left input select */ 171#define H2I_C2_MUTE 0x400 /* mute */ 172#define H2I_C2_DO1 0x00010000 /* digital output port bit 0 */ 173#define H2I_C2_DO2 0x00020000 /* digital output port bit 1 */ 174#define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */ 175#define H2I_C2_R_ATT_M 0x007c0000 /* attenuation */ 176#define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */ 177#define H2I_C2_L_ATT_M 0x0f800000 /* attenuation */ 178 179#define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */ 180 181/* Clock generator CTL 1, 16 bit */ 182 183#define H2I_BRES1_C1 0x2104 184#define H2I_BRES2_C1 0x2204 185#define H2I_BRES3_C1 0x2304 186 187#define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */ 188#define H2I_BRES_C1_M 0x03 189 190/* Clock generator CTL 2, 32 bit */ 191 192#define H2I_BRES1_C2 0x2108 193#define H2I_BRES2_C2 0x2208 194#define H2I_BRES3_C2 0x2308 195 196#define H2I_BRES_C2_INC_SHIFT 0 /* increment value */ 197#define H2I_BRES_C2_INC_M 0xffff 198#define H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */ 199#define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */ 200 201/* Unix timer, 64 bit */ 202 203#define H2I_UTIME 0x3104 204#define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */ 205#define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */ 206#define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */ 207#define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */ 208#define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */ 209 210typedef volatile u32 hal2_reg_t; 211 212typedef struct stru_hal2_ctl_regs hal2_ctl_regs_t; 213struct stru_hal2_ctl_regs { 214 hal2_reg_t _unused0[4]; 215 hal2_reg_t isr; /* 0x10 Status Register */ 216 hal2_reg_t _unused1[3]; 217 hal2_reg_t rev; /* 0x20 Revision Register */ 218 hal2_reg_t _unused2[3]; 219 hal2_reg_t iar; /* 0x30 Indirect Address Register */ 220 hal2_reg_t _unused3[3]; 221 hal2_reg_t idr0; /* 0x40 Indirect Data Register 0 */ 222 hal2_reg_t _unused4[3]; 223 hal2_reg_t idr1; /* 0x50 Indirect Data Register 1 */ 224 hal2_reg_t _unused5[3]; 225 hal2_reg_t idr2; /* 0x60 Indirect Data Register 2 */ 226 hal2_reg_t _unused6[3]; 227 hal2_reg_t idr3; /* 0x70 Indirect Data Register 3 */ 228}; 229 230typedef struct stru_hal2_aes_regs hal2_aes_regs_t; 231struct stru_hal2_aes_regs { 232 hal2_reg_t rx_stat[2]; /* Status registers */ 233 hal2_reg_t rx_cr[2]; /* Control registers */ 234 hal2_reg_t rx_ud[4]; /* User data window */ 235 hal2_reg_t rx_st[24]; /* Channel status data */ 236 237 hal2_reg_t tx_stat[1]; /* Status register */ 238 hal2_reg_t tx_cr[3]; /* Control registers */ 239 hal2_reg_t tx_ud[4]; /* User data window */ 240 hal2_reg_t tx_st[24]; /* Channel status data */ 241}; 242 243typedef struct stru_hal2_vol_regs hal2_vol_regs_t; 244struct stru_hal2_vol_regs { 245 hal2_reg_t right; /* 0x00 Right volume */ 246 hal2_reg_t left; /* 0x04 Left volume */ 247}; 248 249typedef struct stru_hal2_syn_regs hal2_syn_regs_t; 250struct stru_hal2_syn_regs { 251 hal2_reg_t _unused0[2]; 252 hal2_reg_t page; /* DOC Page register */ 253 hal2_reg_t regsel; /* DOC Register selection */ 254 hal2_reg_t dlow; /* DOC Data low */ 255 hal2_reg_t dhigh; /* DOC Data high */ 256 hal2_reg_t irq; /* IRQ Status */ 257 hal2_reg_t dram; /* DRAM Access */ 258}; 259 260/* HAL2 specific structures */ 261 262typedef struct stru_hal2_pbus hal2_pbus_t; 263struct stru_hal2_pbus { 264 struct hpc3_pbus_dmacregs *pbus; 265 int pbusnr; 266 unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */ 267}; 268 269typedef struct stru_hal2_binfo hal2_binfo_t; 270typedef struct stru_hal2_buffer hal2_buf_t; 271struct stru_hal2_binfo { 272 volatile struct hpc_dma_desc desc; 273 hal2_buf_t *next; /* pointer to next buffer */ 274 int cnt; /* bytes in buffer */ 275}; 276#define H2_BUFFER_SIZE (PAGE_SIZE - \ 277 ((sizeof(hal2_binfo_t) - 1) / 8 + 1) * 8) 278struct stru_hal2_buffer { 279 hal2_binfo_t info; 280 char data[H2_BUFFER_SIZE] __attribute__((aligned(8))); 281}; 282 283typedef struct stru_hal2_codec hal2_codec_t; 284struct stru_hal2_codec { 285 hal2_buf_t *head; 286 hal2_buf_t *tail; 287 hal2_pbus_t pbus; 288 unsigned int format; /* Audio data format */ 289 int voices; /* mono/stereo */ 290 unsigned int sample_rate; 291 unsigned int master; /* Master frequency */ 292 unsigned short mod; /* MOD value */ 293 unsigned short inc; /* INC value */ 294 295 wait_queue_head_t dma_wait; 296 spinlock_t lock; 297 struct semaphore sem; 298 299 int usecount; /* recording and playback are 300 * independent */ 301}; 302 303#define H2_MIX_OUTPUT_ATT 0 304#define H2_MIX_INPUT_GAIN 1 305#define H2_MIXERS 2 306typedef struct stru_hal2_mixer hal2_mixer_t; 307struct stru_hal2_mixer { 308 int modcnt; 309 unsigned int volume[H2_MIXERS]; 310}; 311 312typedef struct stru_hal2_card hal2_card_t; 313struct stru_hal2_card { 314 int dev_dsp; /* audio device */ 315 int dev_mixer; /* mixer device */ 316 int dev_midi; /* midi device */ 317 318 hal2_ctl_regs_t *ctl_regs; /* HAL2 ctl registers */ 319 hal2_aes_regs_t *aes_regs; /* HAL2 vol registers */ 320 hal2_vol_regs_t *vol_regs; /* HAL2 aes registers */ 321 hal2_syn_regs_t *syn_regs; /* HAL2 syn registers */ 322 323 hal2_codec_t dac; 324 hal2_codec_t adc; 325 hal2_mixer_t mixer; 326}; 327 328#endif /* __HAL2_H */ 329