1//**************************************************************************** 2// 3// HWDEFS.H - Definitions of the registers and data structures used by the 4// CS4281 5// 6// Copyright (c) 1999,2000,2001 Crystal Semiconductor Corp. 7// 8//**************************************************************************** 9 10#ifndef _H_HWDEFS 11#define _H_HWDEFS 12 13//**************************************************************************** 14// 15// The following define the offsets of the registers located in the PCI 16// configuration space of the CS4281 part. 17// 18//**************************************************************************** 19#define PCICONFIG_DEVID_VENID 0x00000000L 20#define PCICONFIG_STATUS_COMMAND 0x00000004L 21#define PCICONFIG_CLASS_REVISION 0x00000008L 22#define PCICONFIG_LATENCY_TIMER 0x0000000CL 23#define PCICONFIG_BA0 0x00000010L 24#define PCICONFIG_BA1 0x00000014L 25#define PCICONFIG_SUBSYSID_SUBSYSVENID 0x0000002CL 26#define PCICONFIG_INTERRUPT 0x0000003CL 27 28//**************************************************************************** 29// 30// The following define the offsets of the registers accessed via base address 31// register zero on the CS4281 part. 32// 33//**************************************************************************** 34#define BA0_HISR 0x00000000L 35#define BA0_HICR 0x00000008L 36#define BA0_HIMR 0x0000000CL 37#define BA0_IIER 0x00000010L 38#define BA0_HDSR0 0x000000F0L 39#define BA0_HDSR1 0x000000F4L 40#define BA0_HDSR2 0x000000F8L 41#define BA0_HDSR3 0x000000FCL 42#define BA0_DCA0 0x00000110L 43#define BA0_DCC0 0x00000114L 44#define BA0_DBA0 0x00000118L 45#define BA0_DBC0 0x0000011CL 46#define BA0_DCA1 0x00000120L 47#define BA0_DCC1 0x00000124L 48#define BA0_DBA1 0x00000128L 49#define BA0_DBC1 0x0000012CL 50#define BA0_DCA2 0x00000130L 51#define BA0_DCC2 0x00000134L 52#define BA0_DBA2 0x00000138L 53#define BA0_DBC2 0x0000013CL 54#define BA0_DCA3 0x00000140L 55#define BA0_DCC3 0x00000144L 56#define BA0_DBA3 0x00000148L 57#define BA0_DBC3 0x0000014CL 58#define BA0_DMR0 0x00000150L 59#define BA0_DCR0 0x00000154L 60#define BA0_DMR1 0x00000158L 61#define BA0_DCR1 0x0000015CL 62#define BA0_DMR2 0x00000160L 63#define BA0_DCR2 0x00000164L 64#define BA0_DMR3 0x00000168L 65#define BA0_DCR3 0x0000016CL 66#define BA0_DLMR 0x00000170L 67#define BA0_DLSR 0x00000174L 68#define BA0_FCR0 0x00000180L 69#define BA0_FCR1 0x00000184L 70#define BA0_FCR2 0x00000188L 71#define BA0_FCR3 0x0000018CL 72#define BA0_FPDR0 0x00000190L 73#define BA0_FPDR1 0x00000194L 74#define BA0_FPDR2 0x00000198L 75#define BA0_FPDR3 0x0000019CL 76#define BA0_FCHS 0x0000020CL 77#define BA0_FSIC0 0x00000210L 78#define BA0_FSIC1 0x00000214L 79#define BA0_FSIC2 0x00000218L 80#define BA0_FSIC3 0x0000021CL 81#define BA0_PCICFG00 0x00000300L 82#define BA0_PCICFG04 0x00000304L 83#define BA0_PCICFG08 0x00000308L 84#define BA0_PCICFG0C 0x0000030CL 85#define BA0_PCICFG10 0x00000310L 86#define BA0_PCICFG14 0x00000314L 87#define BA0_PCICFG18 0x00000318L 88#define BA0_PCICFG1C 0x0000031CL 89#define BA0_PCICFG20 0x00000320L 90#define BA0_PCICFG24 0x00000324L 91#define BA0_PCICFG28 0x00000328L 92#define BA0_PCICFG2C 0x0000032CL 93#define BA0_PCICFG30 0x00000330L 94#define BA0_PCICFG34 0x00000334L 95#define BA0_PCICFG38 0x00000338L 96#define BA0_PCICFG3C 0x0000033CL 97#define BA0_PCICFG40 0x00000340L 98#define BA0_PMCS 0x00000344L 99#define BA0_CWPR 0x000003E0L 100#define BA0_EPPMC 0x000003E4L 101#define BA0_GPIOR 0x000003E8L 102#define BA0_SPMC 0x000003ECL 103#define BA0_CFLR 0x000003F0L 104#define BA0_IISR 0x000003F4L 105#define BA0_TMS 0x000003F8L 106#define BA0_SSVID 0x000003FCL 107#define BA0_CLKCR1 0x00000400L 108#define BA0_FRR 0x00000410L 109#define BA0_SLT12O 0x0000041CL 110#define BA0_SERMC 0x00000420L 111#define BA0_SERC1 0x00000428L 112#define BA0_SERC2 0x0000042CL 113#define BA0_SLT12M 0x0000045CL 114#define BA0_ACCTL 0x00000460L 115#define BA0_ACSTS 0x00000464L 116#define BA0_ACOSV 0x00000468L 117#define BA0_ACCAD 0x0000046CL 118#define BA0_ACCDA 0x00000470L 119#define BA0_ACISV 0x00000474L 120#define BA0_ACSAD 0x00000478L 121#define BA0_ACSDA 0x0000047CL 122#define BA0_JSPT 0x00000480L 123#define BA0_JSCTL 0x00000484L 124#define BA0_MIDCR 0x00000490L 125#define BA0_MIDCMD 0x00000494L 126#define BA0_MIDSR 0x00000494L 127#define BA0_MIDWP 0x00000498L 128#define BA0_MIDRP 0x0000049CL 129#define BA0_AODSD1 0x000004A8L 130#define BA0_AODSD2 0x000004ACL 131#define BA0_CFGI 0x000004B0L 132#define BA0_SLT12M2 0x000004DCL 133#define BA0_ACSTS2 0x000004E4L 134#define BA0_ACISV2 0x000004F4L 135#define BA0_ACSAD2 0x000004F8L 136#define BA0_ACSDA2 0x000004FCL 137#define BA0_IOTGP 0x00000500L 138#define BA0_IOTSB 0x00000504L 139#define BA0_IOTFM 0x00000508L 140#define BA0_IOTDMA 0x0000050CL 141#define BA0_IOTAC0 0x00000500L 142#define BA0_IOTAC1 0x00000504L 143#define BA0_IOTAC2 0x00000508L 144#define BA0_IOTAC3 0x0000050CL 145#define BA0_IOTPCP 0x0000052CL 146#define BA0_IOTCC 0x00000530L 147#define BA0_IOTCR 0x0000058CL 148#define BA0_PCPRR 0x00000600L 149#define BA0_PCPGR 0x00000604L 150#define BA0_PCPCR 0x00000608L 151#define BA0_PCPCIEN 0x00000608L 152#define BA0_SBMAR 0x00000700L 153#define BA0_SBMDR 0x00000704L 154#define BA0_SBRR 0x00000708L 155#define BA0_SBRDP 0x0000070CL 156#define BA0_SBWDP 0x00000710L 157#define BA0_SBWBS 0x00000710L 158#define BA0_SBRBS 0x00000714L 159#define BA0_FMSR 0x00000730L 160#define BA0_B0AP 0x00000730L 161#define BA0_FMDP 0x00000734L 162#define BA0_B1AP 0x00000738L 163#define BA0_B1DP 0x0000073CL 164#define BA0_SSPM 0x00000740L 165#define BA0_DACSR 0x00000744L 166#define BA0_ADCSR 0x00000748L 167#define BA0_SSCR 0x0000074CL 168#define BA0_FMLVC 0x00000754L 169#define BA0_FMRVC 0x00000758L 170#define BA0_SRCSA 0x0000075CL 171#define BA0_PPLVC 0x00000760L 172#define BA0_PPRVC 0x00000764L 173#define BA0_PASR 0x00000768L 174#define BA0_CASR 0x0000076CL 175 176//**************************************************************************** 177// 178// The following define the offsets of the AC97 shadow registers, which appear 179// as a virtual extension to the base address register zero memory range. 180// 181//**************************************************************************** 182#define AC97_REG_OFFSET_MASK 0x0000007EL 183#define AC97_CODEC_NUMBER_MASK 0x00003000L 184 185#define BA0_AC97_RESET 0x00001000L 186#define BA0_AC97_MASTER_VOLUME 0x00001002L 187#define BA0_AC97_HEADPHONE_VOLUME 0x00001004L 188#define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L 189#define BA0_AC97_MASTER_TONE 0x00001008L 190#define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL 191#define BA0_AC97_PHONE_VOLUME 0x0000100CL 192#define BA0_AC97_MIC_VOLUME 0x0000100EL 193#define BA0_AC97_LINE_IN_VOLUME 0x00001010L 194#define BA0_AC97_CD_VOLUME 0x00001012L 195#define BA0_AC97_VIDEO_VOLUME 0x00001014L 196#define BA0_AC97_AUX_VOLUME 0x00001016L 197#define BA0_AC97_PCM_OUT_VOLUME 0x00001018L 198#define BA0_AC97_RECORD_SELECT 0x0000101AL 199#define BA0_AC97_RECORD_GAIN 0x0000101CL 200#define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL 201#define BA0_AC97_GENERAL_PURPOSE 0x00001020L 202#define BA0_AC97_3D_CONTROL 0x00001022L 203#define BA0_AC97_MODEM_RATE 0x00001024L 204#define BA0_AC97_POWERDOWN 0x00001026L 205#define BA0_AC97_EXT_AUDIO_ID 0x00001028L 206#define BA0_AC97_EXT_AUDIO_POWER 0x0000102AL 207#define BA0_AC97_PCM_FRONT_DAC_RATE 0x0000102CL 208#define BA0_AC97_PCM_SURR_DAC_RATE 0x0000102EL 209#define BA0_AC97_PCM_LFE_DAC_RATE 0x00001030L 210#define BA0_AC97_PCM_LR_ADC_RATE 0x00001032L 211#define BA0_AC97_MIC_ADC_RATE 0x00001034L 212#define BA0_AC97_6CH_VOL_C_LFE 0x00001036L 213#define BA0_AC97_6CH_VOL_SURROUND 0x00001038L 214#define BA0_AC97_RESERVED_3A 0x0000103AL 215#define BA0_AC97_EXT_MODEM_ID 0x0000103CL 216#define BA0_AC97_EXT_MODEM_POWER 0x0000103EL 217#define BA0_AC97_LINE1_CODEC_RATE 0x00001040L 218#define BA0_AC97_LINE2_CODEC_RATE 0x00001042L 219#define BA0_AC97_HANDSET_CODEC_RATE 0x00001044L 220#define BA0_AC97_LINE1_CODEC_LEVEL 0x00001046L 221#define BA0_AC97_LINE2_CODEC_LEVEL 0x00001048L 222#define BA0_AC97_HANDSET_CODEC_LEVEL 0x0000104AL 223#define BA0_AC97_GPIO_PIN_CONFIG 0x0000104CL 224#define BA0_AC97_GPIO_PIN_TYPE 0x0000104EL 225#define BA0_AC97_GPIO_PIN_STICKY 0x00001050L 226#define BA0_AC97_GPIO_PIN_WAKEUP 0x00001052L 227#define BA0_AC97_GPIO_PIN_STATUS 0x00001054L 228#define BA0_AC97_MISC_MODEM_AFE_STAT 0x00001056L 229#define BA0_AC97_RESERVED_58 0x00001058L 230#define BA0_AC97_CRYSTAL_REV_N_FAB_ID 0x0000105AL 231#define BA0_AC97_TEST_AND_MISC_CTRL 0x0000105CL 232#define BA0_AC97_AC_MODE 0x0000105EL 233#define BA0_AC97_MISC_CRYSTAL_CONTROL 0x00001060L 234#define BA0_AC97_LINE1_HYPRID_CTRL 0x00001062L 235#define BA0_AC97_VENDOR_RESERVED_64 0x00001064L 236#define BA0_AC97_VENDOR_RESERVED_66 0x00001066L 237#define BA0_AC97_SPDIF_CONTROL 0x00001068L 238#define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL 239#define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL 240#define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL 241#define BA0_AC97_VENDOR_RESERVED_70 0x00001070L 242#define BA0_AC97_VENDOR_RESERVED_72 0x00001072L 243#define BA0_AC97_VENDOR_RESERVED_74 0x00001074L 244#define BA0_AC97_CAL_ADDRESS 0x00001076L 245#define BA0_AC97_CAL_DATA 0x00001078L 246#define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL 247#define BA0_AC97_VENDOR_ID1 0x0000107CL 248#define BA0_AC97_VENDOR_ID2 0x0000107EL 249 250//**************************************************************************** 251// 252// The following define the offsets of the registers and memories accessed via 253// base address register one on the CS4281 part. 254// 255//**************************************************************************** 256 257//**************************************************************************** 258// 259// The following defines are for the flags in the PCI device ID/vendor ID 260// register. 261// 262//**************************************************************************** 263#define PDV_VENID_MASK 0x0000FFFFL 264#define PDV_DEVID_MASK 0xFFFF0000L 265#define PDV_VENID_SHIFT 0L 266#define PDV_DEVID_SHIFT 16L 267#define VENID_CIRRUS_LOGIC 0x1013L 268#define DEVID_CS4281 0x6005L 269 270//**************************************************************************** 271// 272// The following defines are for the flags in the PCI status and command 273// register. 274// 275//**************************************************************************** 276#define PSC_IO_SPACE_ENABLE 0x00000001L 277#define PSC_MEMORY_SPACE_ENABLE 0x00000002L 278#define PSC_BUS_MASTER_ENABLE 0x00000004L 279#define PSC_SPECIAL_CYCLES 0x00000008L 280#define PSC_MWI_ENABLE 0x00000010L 281#define PSC_VGA_PALETTE_SNOOP 0x00000020L 282#define PSC_PARITY_RESPONSE 0x00000040L 283#define PSC_WAIT_CONTROL 0x00000080L 284#define PSC_SERR_ENABLE 0x00000100L 285#define PSC_FAST_B2B_ENABLE 0x00000200L 286#define PSC_UDF_MASK 0x007F0000L 287#define PSC_FAST_B2B_CAPABLE 0x00800000L 288#define PSC_PARITY_ERROR_DETECTED 0x01000000L 289#define PSC_DEVSEL_TIMING_MASK 0x06000000L 290#define PSC_TARGET_ABORT_SIGNALLED 0x08000000L 291#define PSC_RECEIVED_TARGET_ABORT 0x10000000L 292#define PSC_RECEIVED_MASTER_ABORT 0x20000000L 293#define PSC_SIGNALLED_SERR 0x40000000L 294#define PSC_DETECTED_PARITY_ERROR 0x80000000L 295#define PSC_UDF_SHIFT 16L 296#define PSC_DEVSEL_TIMING_SHIFT 25L 297 298//**************************************************************************** 299// 300// The following defines are for the flags in the PCI class/revision ID 301// register. 302// 303//**************************************************************************** 304#define PCR_REVID_MASK 0x000000FFL 305#define PCR_INTERFACE_MASK 0x0000FF00L 306#define PCR_SUBCLASS_MASK 0x00FF0000L 307#define PCR_CLASS_MASK 0xFF000000L 308#define PCR_REVID_SHIFT 0L 309#define PCR_INTERFACE_SHIFT 8L 310#define PCR_SUBCLASS_SHIFT 16L 311#define PCR_CLASS_SHIFT 24L 312 313//**************************************************************************** 314// 315// The following defines are for the flags in the PCI latency timer register. 316// 317//**************************************************************************** 318#define PLT_CACHE_LINE_SIZE_MASK 0x000000FFL 319#define PLT_LATENCY_TIMER_MASK 0x0000FF00L 320#define PLT_HEADER_TYPE_MASK 0x00FF0000L 321#define PLT_BIST_MASK 0xFF000000L 322#define PLT_CACHE_LINE_SIZE_SHIFT 0L 323#define PLT_LATENCY_TIMER_SHIFT 8L 324#define PLT_HEADER_TYPE_SHIFT 16L 325#define PLT_BIST_SHIFT 24L 326 327//**************************************************************************** 328// 329// The following defines are for the flags in the PCI base address registers. 330// 331//**************************************************************************** 332#define PBAR_MEMORY_SPACE_INDICATOR 0x00000001L 333#define PBAR_LOCATION_TYPE_MASK 0x00000006L 334#define PBAR_NOT_PREFETCHABLE 0x00000008L 335#define PBAR_ADDRESS_MASK 0xFFFFFFF0L 336#define PBAR_LOCATION_TYPE_SHIFT 1L 337 338//**************************************************************************** 339// 340// The following defines are for the flags in the PCI subsystem ID/subsystem 341// vendor ID register. 342// 343//**************************************************************************** 344#define PSS_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFFL 345#define PSS_SUBSYSTEM_ID_MASK 0xFFFF0000L 346#define PSS_SUBSYSTEM_VENDOR_ID_SHIFT 0L 347#define PSS_SUBSYSTEM_ID_SHIFT 16L 348 349//**************************************************************************** 350// 351// The following defines are for the flags in the PCI interrupt register. 352// 353//**************************************************************************** 354#define PI_LINE_MASK 0x000000FFL 355#define PI_PIN_MASK 0x0000FF00L 356#define PI_MIN_GRANT_MASK 0x00FF0000L 357#define PI_MAX_LATENCY_MASK 0xFF000000L 358#define PI_LINE_SHIFT 0L 359#define PI_PIN_SHIFT 8L 360#define PI_MIN_GRANT_SHIFT 16L 361#define PI_MAX_LATENCY_SHIFT 24L 362 363//**************************************************************************** 364// 365// The following defines are for the flags in the host interrupt status 366// register. 367// 368//**************************************************************************** 369#define HISR_HVOLMASK 0x00000003L 370#define HISR_VDNI 0x00000001L 371#define HISR_VUPI 0x00000002L 372#define HISR_GP1I 0x00000004L 373#define HISR_GP3I 0x00000008L 374#define HISR_GPSI 0x00000010L 375#define HISR_GPPI 0x00000020L 376#define HISR_DMAI 0x00040000L 377#define HISR_FIFOI 0x00100000L 378#define HISR_HVOL 0x00200000L 379#define HISR_MIDI 0x00400000L 380#define HISR_SBINT 0x00800000L 381#define HISR_INTENA 0x80000000L 382#define HISR_DMA_MASK 0x00000F00L 383#define HISR_FIFO_MASK 0x0000F000L 384#define HISR_DMA_SHIFT 8L 385#define HISR_FIFO_SHIFT 12L 386#define HISR_FIFO0 0x00001000L 387#define HISR_FIFO1 0x00002000L 388#define HISR_FIFO2 0x00004000L 389#define HISR_FIFO3 0x00008000L 390#define HISR_DMA0 0x00000100L 391#define HISR_DMA1 0x00000200L 392#define HISR_DMA2 0x00000400L 393#define HISR_DMA3 0x00000800L 394#define HISR_RESERVED 0x40000000L 395 396//**************************************************************************** 397// 398// The following defines are for the flags in the host interrupt control 399// register. 400// 401//**************************************************************************** 402#define HICR_IEV 0x00000001L 403#define HICR_CHGM 0x00000002L 404 405//**************************************************************************** 406// 407// The following defines are for the flags in the DMA Mode Register n 408// (DMRn) 409// 410//**************************************************************************** 411#define DMRn_TR_MASK 0x0000000CL 412#define DMRn_TR_SHIFT 2L 413#define DMRn_AUTO 0x00000010L 414#define DMRn_TR_READ 0x00000008L 415#define DMRn_TR_WRITE 0x00000004L 416#define DMRn_TYPE_MASK 0x000000C0L 417#define DMRn_TYPE_SHIFT 6L 418#define DMRn_SIZE8 0x00010000L 419#define DMRn_MONO 0x00020000L 420#define DMRn_BEND 0x00040000L 421#define DMRn_USIGN 0x00080000L 422#define DMRn_SIZE20 0x00100000L 423#define DMRn_SWAPC 0x00400000L 424#define DMRn_CBC 0x01000000L 425#define DMRn_TBC 0x02000000L 426#define DMRn_POLL 0x10000000L 427#define DMRn_DMA 0x20000000L 428#define DMRn_FSEL_MASK 0xC0000000L 429#define DMRn_FSEL_SHIFT 30L 430#define DMRn_FSEL0 0x00000000L 431#define DMRn_FSEL1 0x40000000L 432#define DMRn_FSEL2 0x80000000L 433#define DMRn_FSEL3 0xC0000000L 434 435//**************************************************************************** 436// 437// The following defines are for the flags in the DMA Command Register n 438// (DCRn) 439// 440//**************************************************************************** 441#define DCRn_HTCIE 0x00020000L 442#define DCRn_TCIE 0x00010000L 443#define DCRn_MSK 0x00000001L 444 445//**************************************************************************** 446// 447// The following defines are for the flags in the FIFO Control 448// register n.(FCRn) 449// 450//**************************************************************************** 451#define FCRn_OF_MASK 0x0000007FL 452#define FCRn_OF_SHIFT 0L 453#define FCRn_SZ_MASK 0x00007F00L 454#define FCRn_SZ_SHIFT 8L 455#define FCRn_LS_MASK 0x001F0000L 456#define FCRn_LS_SHIFT 16L 457#define FCRn_RS_MASK 0x1F000000L 458#define FCRn_RS_SHIFT 24L 459#define FCRn_FEN 0x80000000L 460#define FCRn_PSH 0x20000000L 461#define FCRn_DACZ 0x40000000L 462 463//**************************************************************************** 464// 465// The following defines are for the flags in the serial port Power Management 466// control register.(SPMC) 467// 468//**************************************************************************** 469#define SPMC_RSTN 0x00000001L 470#define SPMC_ASYN 0x00000002L 471#define SPMC_WUP1 0x00000004L 472#define SPMC_WUP2 0x00000008L 473#define SPMC_ASDI2E 0x00000100L 474#define SPMC_ESSPD 0x00000200L 475#define SPMC_GISPEN 0x00004000L 476#define SPMC_GIPPEN 0x00008000L 477 478//**************************************************************************** 479// 480// The following defines are for the flags in the Configuration Load register. 481// (CFLR) 482// 483//**************************************************************************** 484#define CFLR_CLOCK_SOURCE_MASK 0x00000003L 485#define CFLR_CLOCK_SOURCE_AC97 0x00000001L 486 487#define CFLR_CB0_MASK 0x000000FFL 488#define CFLR_CB1_MASK 0x0000FF00L 489#define CFLR_CB2_MASK 0x00FF0000L 490#define CFLR_CB3_MASK 0xFF000000L 491#define CFLR_CB0_SHIFT 0L 492#define CFLR_CB1_SHIFT 8L 493#define CFLR_CB2_SHIFT 16L 494#define CFLR_CB3_SHIFT 24L 495 496#define IOTCR_DMA0 0x00000000L 497#define IOTCR_DMA1 0x00000400L 498#define IOTCR_DMA2 0x00000800L 499#define IOTCR_DMA3 0x00000C00L 500#define IOTCR_CCLS 0x00000100L 501#define IOTCR_PCPCI 0x00000200L 502#define IOTCR_DDMA 0x00000300L 503 504#define SBWBS_WBB 0x00000080L 505 506//**************************************************************************** 507// 508// The following defines are for the flags in the SRC Slot Assignment Register 509// (SRCSA) 510// 511//**************************************************************************** 512#define SRCSA_PLSS_MASK 0x0000001FL 513#define SRCSA_PLSS_SHIFT 0L 514#define SRCSA_PRSS_MASK 0x00001F00L 515#define SRCSA_PRSS_SHIFT 8L 516#define SRCSA_CLSS_MASK 0x001F0000L 517#define SRCSA_CLSS_SHIFT 16L 518#define SRCSA_CRSS_MASK 0x1F000000L 519#define SRCSA_CRSS_SHIFT 24L 520 521//**************************************************************************** 522// 523// The following defines are for the flags in the Sound System Power Management 524// register.(SSPM) 525// 526//**************************************************************************** 527#define SSPM_FPDN 0x00000080L 528#define SSPM_MIXEN 0x00000040L 529#define SSPM_CSRCEN 0x00000020L 530#define SSPM_PSRCEN 0x00000010L 531#define SSPM_JSEN 0x00000008L 532#define SSPM_ACLEN 0x00000004L 533#define SSPM_FMEN 0x00000002L 534 535//**************************************************************************** 536// 537// The following defines are for the flags in the Sound System Control 538// Register. (SSCR) 539// 540//**************************************************************************** 541#define SSCR_SB 0x00000004L 542#define SSCR_HVC 0x00000008L 543#define SSCR_LPFIFO 0x00000040L 544#define SSCR_LPSRC 0x00000080L 545#define SSCR_XLPSRC 0x00000100L 546#define SSCR_MVMD 0x00010000L 547#define SSCR_MVAD 0x00020000L 548#define SSCR_MVLD 0x00040000L 549#define SSCR_MVCS 0x00080000L 550 551//**************************************************************************** 552// 553// The following defines are for the flags in the Clock Control Register 1. 554// (CLKCR1) 555// 556//**************************************************************************** 557#define CLKCR1_DLLSS_MASK 0x0000000CL 558#define CLKCR1_DLLSS_SHIFT 2L 559#define CLKCR1_DLLP 0x00000010L 560#define CLKCR1_SWCE 0x00000020L 561#define CLKCR1_DLLOS 0x00000040L 562#define CLKCR1_CKRA 0x00010000L 563#define CLKCR1_CKRN 0x00020000L 564#define CLKCR1_DLLRDY 0x01000000L 565#define CLKCR1_CLKON 0x02000000L 566 567//**************************************************************************** 568// 569// The following defines are for the flags in the Sound Blaster Read Buffer 570// Status.(SBRBS) 571// 572//**************************************************************************** 573#define SBRBS_RD_MASK 0x0000007FL 574#define SBRBS_RD_SHIFT 0L 575#define SBRBS_RBF 0x00000080L 576 577//**************************************************************************** 578// 579// The following defines are for the flags in the serial port master control 580// register.(SERMC) 581// 582//**************************************************************************** 583#define SERMC_MSPE 0x00000001L 584#define SERMC_PTC_MASK 0x0000000EL 585#define SERMC_PTC_SHIFT 1L 586#define SERMC_PTC_AC97 0x00000002L 587#define SERMC_PLB 0x00000010L 588#define SERMC_PXLB 0x00000020L 589#define SERMC_LOFV 0x00080000L 590#define SERMC_SLB 0x00100000L 591#define SERMC_SXLB 0x00200000L 592#define SERMC_ODSEN1 0x01000000L 593#define SERMC_ODSEN2 0x02000000L 594 595//**************************************************************************** 596// 597// The following defines are for the flags in the General Purpose I/O Register. 598// (GPIOR) 599// 600//**************************************************************************** 601#define GPIOR_VDNS 0x00000001L 602#define GPIOR_VUPS 0x00000002L 603#define GPIOR_GP1S 0x00000004L 604#define GPIOR_GP3S 0x00000008L 605#define GPIOR_GPSS 0x00000010L 606#define GPIOR_GPPS 0x00000020L 607#define GPIOR_GP1D 0x00000400L 608#define GPIOR_GP3D 0x00000800L 609#define GPIOR_VDNLT 0x00010000L 610#define GPIOR_VDNPO 0x00020000L 611#define GPIOR_VDNST 0x00040000L 612#define GPIOR_VDNW 0x00080000L 613#define GPIOR_VUPLT 0x00100000L 614#define GPIOR_VUPPO 0x00200000L 615#define GPIOR_VUPST 0x00400000L 616#define GPIOR_VUPW 0x00800000L 617#define GPIOR_GP1OE 0x01000000L 618#define GPIOR_GP1PT 0x02000000L 619#define GPIOR_GP1ST 0x04000000L 620#define GPIOR_GP1W 0x08000000L 621#define GPIOR_GP3OE 0x10000000L 622#define GPIOR_GP3PT 0x20000000L 623#define GPIOR_GP3ST 0x40000000L 624#define GPIOR_GP3W 0x80000000L 625 626//**************************************************************************** 627// 628// The following defines are for the flags in the clock control register 1. 629// 630//**************************************************************************** 631#define CLKCR1_PLLSS_MASK 0x0000000CL 632#define CLKCR1_PLLSS_SERIAL 0x00000000L 633#define CLKCR1_PLLSS_CRYSTAL 0x00000004L 634#define CLKCR1_PLLSS_PCI 0x00000008L 635#define CLKCR1_PLLSS_RESERVED 0x0000000CL 636#define CLKCR1_PLLP 0x00000010L 637#define CLKCR1_SWCE 0x00000020L 638#define CLKCR1_PLLOS 0x00000040L 639 640//**************************************************************************** 641// 642// The following defines are for the flags in the feature reporting register. 643// 644//**************************************************************************** 645#define FRR_FAB_MASK 0x00000003L 646#define FRR_MASK_MASK 0x0000001CL 647#define FRR_ID_MASK 0x00003000L 648#define FRR_FAB_SHIFT 0L 649#define FRR_MASK_SHIFT 2L 650#define FRR_ID_SHIFT 12L 651 652//**************************************************************************** 653// 654// The following defines are for the flags in the serial port 1 configuration 655// register. 656// 657//**************************************************************************** 658#define SERC1_VALUE 0x00000003L 659#define SERC1_SO1EN 0x00000001L 660#define SERC1_SO1F_MASK 0x0000000EL 661#define SERC1_SO1F_CS423X 0x00000000L 662#define SERC1_SO1F_AC97 0x00000002L 663#define SERC1_SO1F_DAC 0x00000004L 664#define SERC1_SO1F_SPDIF 0x00000006L 665 666//**************************************************************************** 667// 668// The following defines are for the flags in the serial port 2 configuration 669// register. 670// 671//**************************************************************************** 672#define SERC2_VALUE 0x00000003L 673#define SERC2_SI1EN 0x00000001L 674#define SERC2_SI1F_MASK 0x0000000EL 675#define SERC2_SI1F_CS423X 0x00000000L 676#define SERC2_SI1F_AC97 0x00000002L 677#define SERC2_SI1F_ADC 0x00000004L 678#define SERC2_SI1F_SPDIF 0x00000006L 679 680//**************************************************************************** 681// 682// The following defines are for the flags in the AC97 control register. 683// 684//**************************************************************************** 685#define ACCTL_ESYN 0x00000002L 686#define ACCTL_VFRM 0x00000004L 687#define ACCTL_DCV 0x00000008L 688#define ACCTL_CRW 0x00000010L 689#define ACCTL_TC 0x00000040L 690 691//**************************************************************************** 692// 693// The following defines are for the flags in the AC97 status register. 694// 695//**************************************************************************** 696#define ACSTS_CRDY 0x00000001L 697#define ACSTS_VSTS 0x00000002L 698 699//**************************************************************************** 700// 701// The following defines are for the flags in the AC97 output slot valid 702// register. 703// 704//**************************************************************************** 705#define ACOSV_SLV3 0x00000001L 706#define ACOSV_SLV4 0x00000002L 707#define ACOSV_SLV5 0x00000004L 708#define ACOSV_SLV6 0x00000008L 709#define ACOSV_SLV7 0x00000010L 710#define ACOSV_SLV8 0x00000020L 711#define ACOSV_SLV9 0x00000040L 712#define ACOSV_SLV10 0x00000080L 713#define ACOSV_SLV11 0x00000100L 714#define ACOSV_SLV12 0x00000200L 715 716//**************************************************************************** 717// 718// The following defines are for the flags in the AC97 command address 719// register. 720// 721//**************************************************************************** 722#define ACCAD_CI_MASK 0x0000007FL 723#define ACCAD_CI_SHIFT 0L 724 725//**************************************************************************** 726// 727// The following defines are for the flags in the AC97 command data register. 728// 729//**************************************************************************** 730#define ACCDA_CD_MASK 0x0000FFFFL 731#define ACCDA_CD_SHIFT 0L 732 733//**************************************************************************** 734// 735// The following defines are for the flags in the AC97 input slot valid 736// register. 737// 738//**************************************************************************** 739#define ACISV_ISV3 0x00000001L 740#define ACISV_ISV4 0x00000002L 741#define ACISV_ISV5 0x00000004L 742#define ACISV_ISV6 0x00000008L 743#define ACISV_ISV7 0x00000010L 744#define ACISV_ISV8 0x00000020L 745#define ACISV_ISV9 0x00000040L 746#define ACISV_ISV10 0x00000080L 747#define ACISV_ISV11 0x00000100L 748#define ACISV_ISV12 0x00000200L 749 750//**************************************************************************** 751// 752// The following defines are for the flags in the AC97 status address 753// register. 754// 755//**************************************************************************** 756#define ACSAD_SI_MASK 0x0000007FL 757#define ACSAD_SI_SHIFT 0L 758 759//**************************************************************************** 760// 761// The following defines are for the flags in the AC97 status data register. 762// 763//**************************************************************************** 764#define ACSDA_SD_MASK 0x0000FFFFL 765#define ACSDA_SD_SHIFT 0L 766 767//**************************************************************************** 768// 769// The following defines are for the flags in the I/O trap address and control 770// registers (all 12). 771// 772//**************************************************************************** 773#define IOTAC_SA_MASK 0x0000FFFFL 774#define IOTAC_MSK_MASK 0x000F0000L 775#define IOTAC_IODC_MASK 0x06000000L 776#define IOTAC_IODC_16_BIT 0x00000000L 777#define IOTAC_IODC_10_BIT 0x02000000L 778#define IOTAC_IODC_12_BIT 0x04000000L 779#define IOTAC_WSPI 0x08000000L 780#define IOTAC_RSPI 0x10000000L 781#define IOTAC_WSE 0x20000000L 782#define IOTAC_WE 0x40000000L 783#define IOTAC_RE 0x80000000L 784#define IOTAC_SA_SHIFT 0L 785#define IOTAC_MSK_SHIFT 16L 786 787//**************************************************************************** 788// 789// The following defines are for the flags in the PC/PCI master enable 790// register. 791// 792//**************************************************************************** 793#define PCPCIEN_EN 0x00000001L 794 795//**************************************************************************** 796// 797// The following defines are for the flags in the joystick poll/trigger 798// register. 799// 800//**************************************************************************** 801#define JSPT_CAX 0x00000001L 802#define JSPT_CAY 0x00000002L 803#define JSPT_CBX 0x00000004L 804#define JSPT_CBY 0x00000008L 805#define JSPT_BA1 0x00000010L 806#define JSPT_BA2 0x00000020L 807#define JSPT_BB1 0x00000040L 808#define JSPT_BB2 0x00000080L 809 810//**************************************************************************** 811// 812// The following defines are for the flags in the joystick control register. 813// The TBF bit has been moved from MIDSR register to JSCTL register bit 8. 814// 815//**************************************************************************** 816#define JSCTL_SP_MASK 0x00000003L 817#define JSCTL_SP_SLOW 0x00000000L 818#define JSCTL_SP_MEDIUM_SLOW 0x00000001L 819#define JSCTL_SP_MEDIUM_FAST 0x00000002L 820#define JSCTL_SP_FAST 0x00000003L 821#define JSCTL_ARE 0x00000004L 822#define JSCTL_TBF 0x00000100L 823 824 825//**************************************************************************** 826// 827// The following defines are for the flags in the MIDI control register. 828// 829//**************************************************************************** 830#define MIDCR_TXE 0x00000001L 831#define MIDCR_RXE 0x00000002L 832#define MIDCR_RIE 0x00000004L 833#define MIDCR_TIE 0x00000008L 834#define MIDCR_MLB 0x00000010L 835#define MIDCR_MRST 0x00000020L 836 837//**************************************************************************** 838// 839// The following defines are for the flags in the MIDI status register. 840// 841//**************************************************************************** 842#define MIDSR_RBE 0x00000080L 843#define MIDSR_RDA 0x00008000L 844 845//**************************************************************************** 846// 847// The following defines are for the flags in the MIDI write port register. 848// 849//**************************************************************************** 850#define MIDWP_MWD_MASK 0x000000FFL 851#define MIDWP_MWD_SHIFT 0L 852 853//**************************************************************************** 854// 855// The following defines are for the flags in the MIDI read port register. 856// 857//**************************************************************************** 858#define MIDRP_MRD_MASK 0x000000FFL 859#define MIDRP_MRD_SHIFT 0L 860 861//**************************************************************************** 862// 863// The following defines are for the flags in the configuration interface 864// register. 865// 866//**************************************************************************** 867#define CFGI_CLK 0x00000001L 868#define CFGI_DOUT 0x00000002L 869#define CFGI_DIN_EEN 0x00000004L 870#define CFGI_EELD 0x00000008L 871 872//**************************************************************************** 873// 874// The following defines are for the flags in the subsystem ID and vendor ID 875// register. 876// 877//**************************************************************************** 878#define SSVID_VID_MASK 0x0000FFFFL 879#define SSVID_SID_MASK 0xFFFF0000L 880#define SSVID_VID_SHIFT 0L 881#define SSVID_SID_SHIFT 16L 882 883//**************************************************************************** 884// 885// The following defines are for the flags in the GPIO pin interface register. 886// 887//**************************************************************************** 888#define GPIOR_VOLDN 0x00000001L 889#define GPIOR_VOLUP 0x00000002L 890#define GPIOR_SI2D 0x00000004L 891#define GPIOR_SI2OE 0x00000008L 892 893//**************************************************************************** 894// 895// The following defines are for the flags in the AC97 status register 2. 896// 897//**************************************************************************** 898#define ACSTS2_CRDY 0x00000001L 899#define ACSTS2_VSTS 0x00000002L 900 901//**************************************************************************** 902// 903// The following defines are for the flags in the AC97 input slot valid 904// register 2. 905// 906//**************************************************************************** 907#define ACISV2_ISV3 0x00000001L 908#define ACISV2_ISV4 0x00000002L 909#define ACISV2_ISV5 0x00000004L 910#define ACISV2_ISV6 0x00000008L 911#define ACISV2_ISV7 0x00000010L 912#define ACISV2_ISV8 0x00000020L 913#define ACISV2_ISV9 0x00000040L 914#define ACISV2_ISV10 0x00000080L 915#define ACISV2_ISV11 0x00000100L 916#define ACISV2_ISV12 0x00000200L 917 918//**************************************************************************** 919// 920// The following defines are for the flags in the AC97 status address 921// register 2. 922// 923//**************************************************************************** 924#define ACSAD2_SI_MASK 0x0000007FL 925#define ACSAD2_SI_SHIFT 0L 926 927//**************************************************************************** 928// 929// The following defines are for the flags in the AC97 status data register 2. 930// 931//**************************************************************************** 932#define ACSDA2_SD_MASK 0x0000FFFFL 933#define ACSDA2_SD_SHIFT 0L 934 935//**************************************************************************** 936// 937// The following defines are for the flags in the I/O trap control register. 938// 939//**************************************************************************** 940#define IOTCR_ITD 0x00000001L 941#define IOTCR_HRV 0x00000002L 942#define IOTCR_SRV 0x00000004L 943#define IOTCR_DTI 0x00000008L 944#define IOTCR_DFI 0x00000010L 945#define IOTCR_DDP 0x00000020L 946#define IOTCR_JTE 0x00000040L 947#define IOTCR_PPE 0x00000080L 948 949//**************************************************************************** 950// 951// The following defines are for the flags in the I/O trap address and control 952// registers for Hardware Master Volume. 953// 954//**************************************************************************** 955#define IOTGP_SA_MASK 0x0000FFFFL 956#define IOTGP_MSK_MASK 0x000F0000L 957#define IOTGP_IODC_MASK 0x06000000L 958#define IOTGP_IODC_16_BIT 0x00000000L 959#define IOTGP_IODC_10_BIT 0x02000000L 960#define IOTGP_IODC_12_BIT 0x04000000L 961#define IOTGP_WSPI 0x08000000L 962#define IOTGP_RSPI 0x10000000L 963#define IOTGP_WSE 0x20000000L 964#define IOTGP_WE 0x40000000L 965#define IOTGP_RE 0x80000000L 966#define IOTGP_SA_SHIFT 0L 967#define IOTGP_MSK_SHIFT 16L 968 969//**************************************************************************** 970// 971// The following defines are for the flags in the I/O trap address and control 972// registers for Sound Blaster 973// 974//**************************************************************************** 975#define IOTSB_SA_MASK 0x0000FFFFL 976#define IOTSB_MSK_MASK 0x000F0000L 977#define IOTSB_IODC_MASK 0x06000000L 978#define IOTSB_IODC_16_BIT 0x00000000L 979#define IOTSB_IODC_10_BIT 0x02000000L 980#define IOTSB_IODC_12_BIT 0x04000000L 981#define IOTSB_WSPI 0x08000000L 982#define IOTSB_RSPI 0x10000000L 983#define IOTSB_WSE 0x20000000L 984#define IOTSB_WE 0x40000000L 985#define IOTSB_RE 0x80000000L 986#define IOTSB_SA_SHIFT 0L 987#define IOTSB_MSK_SHIFT 16L 988 989//**************************************************************************** 990// 991// The following defines are for the flags in the I/O trap address and control 992// registers for FM. 993// 994//**************************************************************************** 995#define IOTFM_SA_MASK 0x0000FFFFL 996#define IOTFM_MSK_MASK 0x000F0000L 997#define IOTFM_IODC_MASK 0x06000000L 998#define IOTFM_IODC_16_BIT 0x00000000L 999#define IOTFM_IODC_10_BIT 0x02000000L 1000#define IOTFM_IODC_12_BIT 0x04000000L 1001#define IOTFM_WSPI 0x08000000L 1002#define IOTFM_RSPI 0x10000000L 1003#define IOTFM_WSE 0x20000000L 1004#define IOTFM_WE 0x40000000L 1005#define IOTFM_RE 0x80000000L 1006#define IOTFM_SA_SHIFT 0L 1007#define IOTFM_MSK_SHIFT 16L 1008 1009//**************************************************************************** 1010// 1011// The following defines are for the flags in the PC/PCI request register. 1012// 1013//**************************************************************************** 1014#define PCPRR_RDC_MASK 0x00000007L 1015#define PCPRR_REQ 0x00008000L 1016#define PCPRR_RDC_SHIFT 0L 1017 1018//**************************************************************************** 1019// 1020// The following defines are for the flags in the PC/PCI grant register. 1021// 1022//**************************************************************************** 1023#define PCPGR_GDC_MASK 0x00000007L 1024#define PCPGR_VL 0x00008000L 1025#define PCPGR_GDC_SHIFT 0L 1026 1027//**************************************************************************** 1028// 1029// The following defines are for the flags in the PC/PCI Control Register. 1030// 1031//**************************************************************************** 1032#define PCPCR_EN 0x00000001L 1033 1034//**************************************************************************** 1035// 1036// The following defines are for the flags in the debug index register. 1037// 1038//**************************************************************************** 1039#define DREG_REGID_MASK 0x0000007FL 1040#define DREG_DEBUG 0x00000080L 1041#define DREG_RGBK_MASK 0x00000700L 1042#define DREG_TRAP 0x00000800L 1043#if !defined(NO_CS4612) 1044#if !defined(NO_CS4615) 1045#define DREG_TRAPX 0x00001000L 1046#endif 1047#endif 1048#define DREG_REGID_SHIFT 0L 1049#define DREG_RGBK_SHIFT 8L 1050#define DREG_RGBK_REGID_MASK 0x0000077FL 1051#define DREG_REGID_R0 0x00000010L 1052#define DREG_REGID_R1 0x00000011L 1053#define DREG_REGID_R2 0x00000012L 1054#define DREG_REGID_R3 0x00000013L 1055#define DREG_REGID_R4 0x00000014L 1056#define DREG_REGID_R5 0x00000015L 1057#define DREG_REGID_R6 0x00000016L 1058#define DREG_REGID_R7 0x00000017L 1059#define DREG_REGID_R8 0x00000018L 1060#define DREG_REGID_R9 0x00000019L 1061#define DREG_REGID_RA 0x0000001AL 1062#define DREG_REGID_RB 0x0000001BL 1063#define DREG_REGID_RC 0x0000001CL 1064#define DREG_REGID_RD 0x0000001DL 1065#define DREG_REGID_RE 0x0000001EL 1066#define DREG_REGID_RF 0x0000001FL 1067#define DREG_REGID_RA_BUS_LOW 0x00000020L 1068#define DREG_REGID_RA_BUS_HIGH 0x00000038L 1069#define DREG_REGID_YBUS_LOW 0x00000050L 1070#define DREG_REGID_YBUS_HIGH 0x00000058L 1071#define DREG_REGID_TRAP_0 0x00000100L 1072#define DREG_REGID_TRAP_1 0x00000101L 1073#define DREG_REGID_TRAP_2 0x00000102L 1074#define DREG_REGID_TRAP_3 0x00000103L 1075#define DREG_REGID_TRAP_4 0x00000104L 1076#define DREG_REGID_TRAP_5 0x00000105L 1077#define DREG_REGID_TRAP_6 0x00000106L 1078#define DREG_REGID_TRAP_7 0x00000107L 1079#define DREG_REGID_INDIRECT_ADDRESS 0x0000010EL 1080#define DREG_REGID_TOP_OF_STACK 0x0000010FL 1081#if !defined(NO_CS4612) 1082#if !defined(NO_CS4615) 1083#define DREG_REGID_TRAP_8 0x00000110L 1084#define DREG_REGID_TRAP_9 0x00000111L 1085#define DREG_REGID_TRAP_10 0x00000112L 1086#define DREG_REGID_TRAP_11 0x00000113L 1087#define DREG_REGID_TRAP_12 0x00000114L 1088#define DREG_REGID_TRAP_13 0x00000115L 1089#define DREG_REGID_TRAP_14 0x00000116L 1090#define DREG_REGID_TRAP_15 0x00000117L 1091#define DREG_REGID_TRAP_16 0x00000118L 1092#define DREG_REGID_TRAP_17 0x00000119L 1093#define DREG_REGID_TRAP_18 0x0000011AL 1094#define DREG_REGID_TRAP_19 0x0000011BL 1095#define DREG_REGID_TRAP_20 0x0000011CL 1096#define DREG_REGID_TRAP_21 0x0000011DL 1097#define DREG_REGID_TRAP_22 0x0000011EL 1098#define DREG_REGID_TRAP_23 0x0000011FL 1099#endif 1100#endif 1101#define DREG_REGID_RSA0_LOW 0x00000200L 1102#define DREG_REGID_RSA0_HIGH 0x00000201L 1103#define DREG_REGID_RSA1_LOW 0x00000202L 1104#define DREG_REGID_RSA1_HIGH 0x00000203L 1105#define DREG_REGID_RSA2 0x00000204L 1106#define DREG_REGID_RSA3 0x00000205L 1107#define DREG_REGID_RSI0_LOW 0x00000206L 1108#define DREG_REGID_RSI0_HIGH 0x00000207L 1109#define DREG_REGID_RSI1 0x00000208L 1110#define DREG_REGID_RSI2 0x00000209L 1111#define DREG_REGID_SAGUSTATUS 0x0000020AL 1112#define DREG_REGID_RSCONFIG01_LOW 0x0000020BL 1113#define DREG_REGID_RSCONFIG01_HIGH 0x0000020CL 1114#define DREG_REGID_RSCONFIG23_LOW 0x0000020DL 1115#define DREG_REGID_RSCONFIG23_HIGH 0x0000020EL 1116#define DREG_REGID_RSDMA01E 0x0000020FL 1117#define DREG_REGID_RSDMA23E 0x00000210L 1118#define DREG_REGID_RSD0_LOW 0x00000211L 1119#define DREG_REGID_RSD0_HIGH 0x00000212L 1120#define DREG_REGID_RSD1_LOW 0x00000213L 1121#define DREG_REGID_RSD1_HIGH 0x00000214L 1122#define DREG_REGID_RSD2_LOW 0x00000215L 1123#define DREG_REGID_RSD2_HIGH 0x00000216L 1124#define DREG_REGID_RSD3_LOW 0x00000217L 1125#define DREG_REGID_RSD3_HIGH 0x00000218L 1126#define DREG_REGID_SRAR_HIGH 0x0000021AL 1127#define DREG_REGID_SRAR_LOW 0x0000021BL 1128#define DREG_REGID_DMA_STATE 0x0000021CL 1129#define DREG_REGID_CURRENT_DMA_STREAM 0x0000021DL 1130#define DREG_REGID_NEXT_DMA_STREAM 0x0000021EL 1131#define DREG_REGID_CPU_STATUS 0x00000300L 1132#define DREG_REGID_MAC_MODE 0x00000301L 1133#define DREG_REGID_STACK_AND_REPEAT 0x00000302L 1134#define DREG_REGID_INDEX0 0x00000304L 1135#define DREG_REGID_INDEX1 0x00000305L 1136#define DREG_REGID_DMA_STATE_0_3 0x00000400L 1137#define DREG_REGID_DMA_STATE_4_7 0x00000404L 1138#define DREG_REGID_DMA_STATE_8_11 0x00000408L 1139#define DREG_REGID_DMA_STATE_12_15 0x0000040CL 1140#define DREG_REGID_DMA_STATE_16_19 0x00000410L 1141#define DREG_REGID_DMA_STATE_20_23 0x00000414L 1142#define DREG_REGID_DMA_STATE_24_27 0x00000418L 1143#define DREG_REGID_DMA_STATE_28_31 0x0000041CL 1144#define DREG_REGID_DMA_STATE_32_35 0x00000420L 1145#define DREG_REGID_DMA_STATE_36_39 0x00000424L 1146#define DREG_REGID_DMA_STATE_40_43 0x00000428L 1147#define DREG_REGID_DMA_STATE_44_47 0x0000042CL 1148#define DREG_REGID_DMA_STATE_48_51 0x00000430L 1149#define DREG_REGID_DMA_STATE_52_55 0x00000434L 1150#define DREG_REGID_DMA_STATE_56_59 0x00000438L 1151#define DREG_REGID_DMA_STATE_60_63 0x0000043CL 1152#define DREG_REGID_DMA_STATE_64_67 0x00000440L 1153#define DREG_REGID_DMA_STATE_68_71 0x00000444L 1154#define DREG_REGID_DMA_STATE_72_75 0x00000448L 1155#define DREG_REGID_DMA_STATE_76_79 0x0000044CL 1156#define DREG_REGID_DMA_STATE_80_83 0x00000450L 1157#define DREG_REGID_DMA_STATE_84_87 0x00000454L 1158#define DREG_REGID_DMA_STATE_88_91 0x00000458L 1159#define DREG_REGID_DMA_STATE_92_95 0x0000045CL 1160#define DREG_REGID_TRAP_SELECT 0x00000500L 1161#define DREG_REGID_TRAP_WRITE_0 0x00000500L 1162#define DREG_REGID_TRAP_WRITE_1 0x00000501L 1163#define DREG_REGID_TRAP_WRITE_2 0x00000502L 1164#define DREG_REGID_TRAP_WRITE_3 0x00000503L 1165#define DREG_REGID_TRAP_WRITE_4 0x00000504L 1166#define DREG_REGID_TRAP_WRITE_5 0x00000505L 1167#define DREG_REGID_TRAP_WRITE_6 0x00000506L 1168#define DREG_REGID_TRAP_WRITE_7 0x00000507L 1169#if !defined(NO_CS4612) 1170#if !defined(NO_CS4615) 1171#define DREG_REGID_TRAP_WRITE_8 0x00000510L 1172#define DREG_REGID_TRAP_WRITE_9 0x00000511L 1173#define DREG_REGID_TRAP_WRITE_10 0x00000512L 1174#define DREG_REGID_TRAP_WRITE_11 0x00000513L 1175#define DREG_REGID_TRAP_WRITE_12 0x00000514L 1176#define DREG_REGID_TRAP_WRITE_13 0x00000515L 1177#define DREG_REGID_TRAP_WRITE_14 0x00000516L 1178#define DREG_REGID_TRAP_WRITE_15 0x00000517L 1179#define DREG_REGID_TRAP_WRITE_16 0x00000518L 1180#define DREG_REGID_TRAP_WRITE_17 0x00000519L 1181#define DREG_REGID_TRAP_WRITE_18 0x0000051AL 1182#define DREG_REGID_TRAP_WRITE_19 0x0000051BL 1183#define DREG_REGID_TRAP_WRITE_20 0x0000051CL 1184#define DREG_REGID_TRAP_WRITE_21 0x0000051DL 1185#define DREG_REGID_TRAP_WRITE_22 0x0000051EL 1186#define DREG_REGID_TRAP_WRITE_23 0x0000051FL 1187#endif 1188#endif 1189#define DREG_REGID_MAC0_ACC0_LOW 0x00000600L 1190#define DREG_REGID_MAC0_ACC1_LOW 0x00000601L 1191#define DREG_REGID_MAC0_ACC2_LOW 0x00000602L 1192#define DREG_REGID_MAC0_ACC3_LOW 0x00000603L 1193#define DREG_REGID_MAC1_ACC0_LOW 0x00000604L 1194#define DREG_REGID_MAC1_ACC1_LOW 0x00000605L 1195#define DREG_REGID_MAC1_ACC2_LOW 0x00000606L 1196#define DREG_REGID_MAC1_ACC3_LOW 0x00000607L 1197#define DREG_REGID_MAC0_ACC0_MID 0x00000608L 1198#define DREG_REGID_MAC0_ACC1_MID 0x00000609L 1199#define DREG_REGID_MAC0_ACC2_MID 0x0000060AL 1200#define DREG_REGID_MAC0_ACC3_MID 0x0000060BL 1201#define DREG_REGID_MAC1_ACC0_MID 0x0000060CL 1202#define DREG_REGID_MAC1_ACC1_MID 0x0000060DL 1203#define DREG_REGID_MAC1_ACC2_MID 0x0000060EL 1204#define DREG_REGID_MAC1_ACC3_MID 0x0000060FL 1205#define DREG_REGID_MAC0_ACC0_HIGH 0x00000610L 1206#define DREG_REGID_MAC0_ACC1_HIGH 0x00000611L 1207#define DREG_REGID_MAC0_ACC2_HIGH 0x00000612L 1208#define DREG_REGID_MAC0_ACC3_HIGH 0x00000613L 1209#define DREG_REGID_MAC1_ACC0_HIGH 0x00000614L 1210#define DREG_REGID_MAC1_ACC1_HIGH 0x00000615L 1211#define DREG_REGID_MAC1_ACC2_HIGH 0x00000616L 1212#define DREG_REGID_MAC1_ACC3_HIGH 0x00000617L 1213#define DREG_REGID_RSHOUT_LOW 0x00000620L 1214#define DREG_REGID_RSHOUT_MID 0x00000628L 1215#define DREG_REGID_RSHOUT_HIGH 0x00000630L 1216 1217//**************************************************************************** 1218// 1219// The following defines are for the flags in the AC97 S/PDIF Control register. 1220// 1221//**************************************************************************** 1222#define SPDIF_CONTROL_SPDIF_EN 0x00008000L 1223#define SPDIF_CONTROL_VAL 0x00004000L 1224#define SPDIF_CONTROL_COPY 0x00000004L 1225#define SPDIF_CONTROL_CC0 0x00000010L 1226#define SPDIF_CONTROL_CC1 0x00000020L 1227#define SPDIF_CONTROL_CC2 0x00000040L 1228#define SPDIF_CONTROL_CC3 0x00000080L 1229#define SPDIF_CONTROL_CC4 0x00000100L 1230#define SPDIF_CONTROL_CC5 0x00000200L 1231#define SPDIF_CONTROL_CC6 0x00000400L 1232#define SPDIF_CONTROL_L 0x00000800L 1233 1234#endif // _H_HWDEFS 1235