1/* 2 * NCR 5380 defines 3 * 4 * Copyright 1993, Drew Eckhardt 5 * Visionary Computing 6 * (Unix consulting and custom programming) 7 * drew@colorado.edu 8 * +1 (303) 666-5836 9 * 10 * DISTRIBUTION RELEASE 7 11 * 12 * For more information, please consult 13 * 14 * NCR 5380 Family 15 * SCSI Protocol Controller 16 * Databook 17 * NCR Microelectronics 18 * 1635 Aeroplaza Drive 19 * Colorado Springs, CO 80916 20 * 1+ (719) 578-3400 21 * 1+ (800) 334-5454 22 */ 23 24/* 25 * $Log: NCR5380.h,v $ 26 * Revision 1.1.1.1 2008/10/15 03:26:48 james26_jang 27 * Initial. 28 * 29 * Revision 1.1.1.1 2008/07/21 09:15:20 james26_jang 30 * New UI, New QoS, New wireless driver(4.151.10.29), ipmonitor. 31 * 32 * Revision 1.1.1.1 2008/07/02 14:39:35 james26_jang 33 * 4.100.10.29, New QoS and New UI. 34 * 35 * Revision 1.1.1.1 2003/02/03 22:37:51 mhuang 36 * LINUX_2_4 branch snapshot from linux-mips.org CVS 37 * 38 */ 39 40#ifndef NCR5380_H 41#define NCR5380_H 42 43#define NCR5380_PUBLIC_RELEASE 7 44#define NCR53C400_PUBLIC_RELEASE 2 45 46#define NDEBUG_ARBITRATION 0x1 47#define NDEBUG_AUTOSENSE 0x2 48#define NDEBUG_DMA 0x4 49#define NDEBUG_HANDSHAKE 0x8 50#define NDEBUG_INFORMATION 0x10 51#define NDEBUG_INIT 0x20 52#define NDEBUG_INTR 0x40 53#define NDEBUG_LINKED 0x80 54#define NDEBUG_MAIN 0x100 55#define NDEBUG_NO_DATAOUT 0x200 56#define NDEBUG_NO_WRITE 0x400 57#define NDEBUG_PIO 0x800 58#define NDEBUG_PSEUDO_DMA 0x1000 59#define NDEBUG_QUEUES 0x2000 60#define NDEBUG_RESELECTION 0x4000 61#define NDEBUG_SELECTION 0x8000 62#define NDEBUG_USLEEP 0x10000 63#define NDEBUG_LAST_BYTE_SENT 0x20000 64#define NDEBUG_RESTART_SELECT 0x40000 65#define NDEBUG_EXTENDED 0x80000 66#define NDEBUG_C400_PREAD 0x100000 67#define NDEBUG_C400_PWRITE 0x200000 68#define NDEBUG_LISTS 0x400000 69 70#define NDEBUG_ANY 0xFFFFFFFFUL 71 72/* 73 * The contents of the OUTPUT DATA register are asserted on the bus when 74 * either arbitration is occurring or the phase-indicating signals ( 75 * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA 76 * bit in the INITIATOR COMMAND register is set. 77 */ 78 79#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */ 80#define CURRENT_SCSI_DATA_REG 0 /* ro same */ 81 82#define INITIATOR_COMMAND_REG 1 /* rw */ 83#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */ 84#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */ 85#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */ 86#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */ 87#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */ 88#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */ 89#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */ 90#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */ 91#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */ 92#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */ 93 94#ifdef DIFFERENTIAL 95#define ICR_BASE ICR_DIFF_ENABLE 96#else 97#define ICR_BASE 0 98#endif 99 100#define MODE_REG 2 101/* 102 * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 103 * transfer, causing the chip to hog the bus. You probably don't want 104 * this. 105 */ 106#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */ 107#define MR_TARGET 0x40 /* rw target mode */ 108#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */ 109#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */ 110#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */ 111#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */ 112#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */ 113#define MR_ARBITRATE 0x01 /* rw start arbitration */ 114 115#ifdef PARITY 116#define MR_BASE MR_ENABLE_PAR_CHECK 117#else 118#define MR_BASE 0 119#endif 120 121#define TARGET_COMMAND_REG 3 122#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */ 123#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */ 124#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */ 125#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */ 126#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */ 127 128#define STATUS_REG 4 /* ro */ 129/* 130 * Note : a set bit indicates an active signal, driven by us or another 131 * device. 132 */ 133#define SR_RST 0x80 134#define SR_BSY 0x40 135#define SR_REQ 0x20 136#define SR_MSG 0x10 137#define SR_CD 0x08 138#define SR_IO 0x04 139#define SR_SEL 0x02 140#define SR_DBP 0x01 141 142/* 143 * Setting a bit in this register will cause an interrupt to be generated when 144 * BSY is false and SEL true and this bit is asserted on the bus. 145 */ 146#define SELECT_ENABLE_REG 4 /* wo */ 147 148#define BUS_AND_STATUS_REG 5 /* ro */ 149#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */ 150#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */ 151#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */ 152#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */ 153#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */ 154#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */ 155#define BASR_ATN 0x02 /* ro BUS status */ 156#define BASR_ACK 0x01 /* ro BUS status */ 157 158/* Write any value to this register to start a DMA send */ 159#define START_DMA_SEND_REG 5 /* wo */ 160 161/* 162 * Used in DMA transfer mode, data is latched from the SCSI bus on 163 * the falling edge of REQ (ini) or ACK (tgt) 164 */ 165#define INPUT_DATA_REG 6 /* ro */ 166 167/* Write any value to this register to start a DMA receive */ 168#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */ 169 170/* Read this register to clear interrupt conditions */ 171#define RESET_PARITY_INTERRUPT_REG 7 /* ro */ 172 173/* Write any value to this register to start an ini mode DMA receive */ 174#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */ 175 176#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */ 177 178#define CSR_RESET 0x80 /* wo Resets 53c400 */ 179#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */ 180#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */ 181#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */ 182#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */ 183#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */ 184#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */ 185#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */ 186#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */ 187 188#define CSR_BASE CSR_53C80_INTR 189 190/* Number of 128-byte blocks to be transferred */ 191#define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */ 192 193/* Resume transfer after disconnect */ 194#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */ 195 196/* Access to host buffer stack */ 197#define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */ 198 199 200/* Note : PHASE_* macros are based on the values of the STATUS register */ 201#define PHASE_MASK (SR_MSG | SR_CD | SR_IO) 202 203#define PHASE_DATAOUT 0 204#define PHASE_DATAIN SR_IO 205#define PHASE_CMDOUT SR_CD 206#define PHASE_STATIN (SR_CD | SR_IO) 207#define PHASE_MSGOUT (SR_MSG | SR_CD) 208#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO) 209#define PHASE_UNKNOWN 0xff 210 211/* 212 * Convert status register phase to something we can use to set phase in 213 * the target register so we can get phase mismatch interrupts on DMA 214 * transfers. 215 */ 216 217#define PHASE_SR_TO_TCR(phase) ((phase) >> 2) 218 219/* 220 * The internal should_disconnect() function returns these based on the 221 * expected length of a disconnect if a device supports disconnect/ 222 * reconnect. 223 */ 224 225#define DISCONNECT_NONE 0 226#define DISCONNECT_TIME_TO_DATA 1 227#define DISCONNECT_LONG 2 228 229/* 230 * These are "special" values for the tag parameter passed to NCR5380_select. 231 */ 232 233#define TAG_NEXT -1 /* Use next free tag */ 234#define TAG_NONE -2 /* 235 * Establish I_T_L nexus instead of I_T_L_Q 236 * even on SCSI-II devices. 237 */ 238 239/* 240 * These are "special" values for the irq and dma_channel fields of the 241 * Scsi_Host structure 242 */ 243 244#define IRQ_NONE 255 245#define DMA_NONE 255 246#define IRQ_AUTO 254 247#define DMA_AUTO 254 248#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */ 249 250#define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */ 251#define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */ 252#define FLAG_NCR53C400 4 /* NCR53c400 */ 253#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */ 254#define FLAG_DTC3181E 16 /* DTC3181E */ 255 256#ifndef ASM 257struct NCR5380_hostdata { 258 NCR5380_implementation_fields; /* implementation specific */ 259 unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */ 260 unsigned char targets_present; /* targets we have connected 261 to, so we can call a select 262 failure a retryable condition */ 263 volatile unsigned char busy[8]; /* index = target, bit = lun */ 264#if defined(REAL_DMA) || defined(REAL_DMA_POLL) 265 volatile int dma_len; /* requested length of DMA */ 266#endif 267 volatile unsigned char last_message; /* last message OUT */ 268 volatile Scsi_Cmnd *connected; /* currently connected command */ 269 volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */ 270 volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */ 271 volatile int restart_select; /* we have disconnected, 272 used to restart 273 NCR5380_select() */ 274 volatile unsigned aborted:1; /* flag, says aborted */ 275 int flags; 276 unsigned long time_expires; /* in jiffies, set prior to sleeping */ 277 struct Scsi_Host *next_timer; 278 int select_time; /* timer in select for target response */ 279 volatile Scsi_Cmnd *selecting; 280#ifdef NCR5380_STATS 281 unsigned timebase; /* Base for time calcs */ 282 long time_read[8]; /* time to do reads */ 283 long time_write[8]; /* time to do writes */ 284 unsigned long bytes_read[8]; /* bytes read */ 285 unsigned long bytes_write[8]; /* bytes written */ 286 unsigned pendingr; 287 unsigned pendingw; 288#endif 289}; 290 291#ifdef __KERNEL__ 292static struct Scsi_Host *first_instance; /* linked list of 5380's */ 293 294#define dprintk(a,b) do {} while(0) 295#define NCR5380_dprint(a,b) do {} while(0) 296#define NCR5380_dprint_phase(a,b) do {} while(0) 297 298#if defined(AUTOPROBE_IRQ) 299static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible); 300#endif 301static void NCR5380_init(struct Scsi_Host *instance, int flags); 302static void NCR5380_information_transfer(struct Scsi_Host *instance); 303#ifndef DONT_USE_INTR 304static void NCR5380_intr(int irq, void *dev_id, struct pt_regs *regs); 305static void do_NCR5380_intr(int irq, void *dev_id, struct pt_regs *regs); 306#endif 307static void NCR5380_main(void); 308static void NCR5380_print_options(struct Scsi_Host *instance); 309static void NCR5380_print_phase(struct Scsi_Host *instance); 310static void NCR5380_print(struct Scsi_Host *instance); 311#ifndef NCR5380_abort 312static 313#endif 314int NCR5380_abort(Scsi_Cmnd * cmd); 315#ifndef NCR5380_reset 316static 317#endif 318int NCR5380_reset(Scsi_Cmnd * cmd, unsigned int reset_flags); 319#ifndef NCR5380_queue_command 320static 321#endif 322int NCR5380_queue_command(Scsi_Cmnd * cmd, void (*done) (Scsi_Cmnd *)); 323 324 325static void NCR5380_reselect(struct Scsi_Host *instance); 326static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd * cmd, int tag); 327#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL) 328static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data); 329#endif 330static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data); 331 332#if (defined(REAL_DMA) || defined(REAL_DMA_POLL)) 333 334#if defined(i386) || defined(__alpha__) 335 336/** 337 * NCR5380_pc_dma_setup - setup ISA DMA 338 * @instance: adapter to set up 339 * @ptr: block to transfer (virtual address) 340 * @count: number of bytes to transfer 341 * @mode: DMA controller mode to use 342 * 343 * Program the DMA controller ready to perform an ISA DMA transfer 344 * on this chip. 345 * 346 * Locks: takes and releases the ISA DMA lock. 347 */ 348 349static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode) 350{ 351 unsigned limit; 352 unsigned long bus_addr = virt_to_bus(ptr); 353 unsigned long flags; 354 355 if (instance->dma_channel <= 3) { 356 if (count > 65536) 357 count = 65536; 358 limit = 65536 - (bus_addr & 0xFFFF); 359 } else { 360 if (count > 65536 * 2) 361 count = 65536 * 2; 362 limit = 65536 * 2 - (bus_addr & 0x1FFFF); 363 } 364 365 if (count > limit) 366 count = limit; 367 368 if ((count & 1) || (bus_addr & 1)) 369 panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no); 370 371 flags=claim_dma_lock(); 372 disable_dma(instance->dma_channel); 373 clear_dma_ff(instance->dma_channel); 374 set_dma_addr(instance->dma_channel, bus_addr); 375 set_dma_count(instance->dma_channel, count); 376 set_dma_mode(instance->dma_channel, mode); 377 enable_dma(instance->dma_channel); 378 release_dma_lock(flags); 379 380 return count; 381} 382 383/** 384 * NCR5380_pc_dma_write_setup - setup ISA DMA write 385 * @instance: adapter to set up 386 * @ptr: block to transfer (virtual address) 387 * @count: number of bytes to transfer 388 * 389 * Program the DMA controller ready to perform an ISA DMA write to the 390 * SCSI controller. 391 * 392 * Locks: called routines take and release the ISA DMA lock. 393 */ 394 395static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count) 396{ 397 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE); 398} 399 400/** 401 * NCR5380_pc_dma_read_setup - setup ISA DMA read 402 * @instance: adapter to set up 403 * @ptr: block to transfer (virtual address) 404 * @count: number of bytes to transfer 405 * 406 * Program the DMA controller ready to perform an ISA DMA read from the 407 * SCSI controller. 408 * 409 * Locks: called routines take and release the ISA DMA lock. 410 */ 411 412static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count) 413{ 414 return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ); 415} 416 417/** 418 * NCR5380_pc_dma_residual - return bytes left 419 * @instance: adapter 420 * 421 * Reports the number of bytes left over after the DMA was terminated. 422 * 423 * Locks: takes and releases the ISA DMA lock. 424 */ 425 426static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance) 427{ 428 unsigned long flags; 429 int tmp; 430 431 flags = claim_dma_lock(); 432 clear_dma_ff(instance->dma_channel); 433 tmp = get_dma_residue(instance->dma_channel); 434 release_dma_lock(flags); 435 436 return tmp; 437} 438#endif /* defined(i386) || defined(__alpha__) */ 439#endif /* defined(REAL_DMA) */ 440#endif /* __KERNEL__ */ 441#endif /* ndef ASM */ 442#endif /* NCR5380_H */ 443