1/* $Id: zs.h,v 1.1.1.1 2008/10/15 03:26:47 james26_jang Exp $ 2 * zs.h: Definitions for the Sparc Zilog serial driver. 3 * 4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) 5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) 6 */ 7#ifndef _ZS_H 8#define _ZS_H 9 10/* Just one channel */ 11struct sun_zschannel { 12 volatile unsigned char control; 13 volatile unsigned char pad1; 14 volatile unsigned char data; 15 volatile unsigned char pad2; 16}; 17 18/* The address space layout for each zs chip. Yes they are 19 * backwards. 20 */ 21struct sun_zslayout { 22 struct sun_zschannel channelB; 23 struct sun_zschannel channelA; 24}; 25 26#define NUM_ZSREGS 16 27 28struct serial_struct { 29 int type; 30 int line; 31 int port; 32 int irq; 33 int flags; 34 int xmit_fifo_size; 35 int custom_divisor; 36 int baud_base; 37 unsigned short close_delay; 38 char reserved_char[2]; 39 int hub6; 40 unsigned short closing_wait; /* time to wait before closing */ 41 unsigned short closing_wait2; /* no longer used... */ 42 int reserved[4]; 43}; 44 45/* 46 * For the close wait times, 0 means wait forever for serial port to 47 * flush its output. 65535 means don't wait at all. 48 */ 49#define ZILOG_CLOSING_WAIT_INF 0 50#define ZILOG_CLOSING_WAIT_NONE 65535 51 52/* 53 * Definitions for ZILOG_struct (and serial_struct) flags field 54 */ 55#define ZILOG_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes 56 on the callout port */ 57#define ZILOG_FOURPORT 0x0002 /* Set OU1, OUT2 per AST Fourport settings */ 58#define ZILOG_SAK 0x0004 /* Secure Attention Key (Orange book) */ 59#define ZILOG_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */ 60 61#define ZILOG_SPD_MASK 0x0030 62#define ZILOG_SPD_HI 0x0010 /* Use 76800 instead of 38400 bps */ 63#define ZILOG_SPD_CUST 0x0030 /* Use user-specified divisor */ 64 65#define ZILOG_SKIP_TEST 0x0040 /* Skip UART test during autoconfiguration */ 66#define ZILOG_AUTO_IRQ 0x0080 /* Do automatic IRQ during autoconfiguration */ 67#define ZILOG_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */ 68#define ZILOG_PGRP_LOCKOUT 0x0200 /* Lock out cua opens based on pgrp */ 69#define ZILOG_CALLOUT_NOHUP 0x0400 /* Don't do hangups for cua device */ 70 71#define ZILOG_FLAGS 0x0FFF /* Possible legal ZILOG flags */ 72#define ZILOG_USR_MASK 0x0430 /* Legal flags that non-privileged 73 * users can set or reset */ 74 75/* Internal flags used only by kernel/chr_drv/serial.c */ 76#define ZILOG_INITIALIZED 0x80000000 /* Serial port was initialized */ 77#define ZILOG_CALLOUT_ACTIVE 0x40000000 /* Call out device is active */ 78#define ZILOG_NORMAL_ACTIVE 0x20000000 /* Normal device is active */ 79#define ZILOG_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */ 80#define ZILOG_CLOSING 0x08000000 /* Serial port is closing */ 81#define ZILOG_CTS_FLOW 0x04000000 /* Do CTS flow control */ 82#define ZILOG_CHECK_CD 0x02000000 /* i.e., CLOCAL */ 83 84/* Software state per channel */ 85 86#ifdef __KERNEL__ 87/* 88 * This is our internal structure for each serial port's state. 89 * 90 * Many fields are paralleled by the structure used by the serial_struct 91 * structure. 92 * 93 * For definitions of the flags field, see tty.h 94 */ 95 96struct sun_serial { 97 struct sun_serial *zs_next; /* For IRQ servicing chain */ 98 struct sun_zschannel *zs_channel; /* Channel registers */ 99 unsigned char read_reg_zero; 100 101 char soft_carrier; /* Use soft carrier on this channel */ 102 char cons_keyb; /* Channel runs the keyboard */ 103 char cons_mouse; /* Channel runs the mouse */ 104 char break_abort; /* Is serial console in, so process brk/abrt */ 105 char kgdb_channel; /* Kgdb is running on this channel */ 106 char is_cons; /* Is this our console. */ 107 108 char channelA; /* This is channel A. */ 109 char parity_mask; /* Mask out parity bits in data register. */ 110 111 /* We need to know the current clock divisor 112 * to read the bps rate the chip has currently 113 * loaded. 114 */ 115 unsigned char clk_divisor; /* May be 1, 16, 32, or 64 */ 116 int zs_baud; 117 118 /* Current write register values */ 119 unsigned char curregs[NUM_ZSREGS]; 120 121 char change_needed; 122 123 int magic; 124 int baud_base; 125 int port; 126 int irq; 127 int flags; /* defined in tty.h */ 128 int type; /* UART type */ 129 struct tty_struct *tty; 130 int read_status_mask; 131 int ignore_status_mask; 132 int timeout; 133 int xmit_fifo_size; 134 int custom_divisor; 135 int x_char; /* xon/xoff character */ 136 int close_delay; 137 unsigned short closing_wait; 138 unsigned short closing_wait2; 139 unsigned long event; 140 unsigned long last_active; 141 int line; 142 int count; /* # of fd on device */ 143 int blocked_open; /* # of blocked opens */ 144 long session; /* Session of opening process */ 145 long pgrp; /* pgrp of opening process */ 146 unsigned char *xmit_buf; 147 int xmit_head; 148 int xmit_tail; 149 int xmit_cnt; 150 struct tq_struct tqueue; 151 struct tq_struct tqueue_hangup; 152 struct termios normal_termios; 153 struct termios callout_termios; 154 wait_queue_head_t open_wait; 155 wait_queue_head_t close_wait; 156}; 157 158 159#define SERIAL_MAGIC 0x5301 160 161/* 162 * The size of the serial xmit buffer is 1 page, or 4096 bytes 163 */ 164#define SERIAL_XMIT_SIZE 4096 165 166/* 167 * Events are used to schedule things to happen at timer-interrupt 168 * time, instead of at rs interrupt time. 169 */ 170#define RS_EVENT_WRITE_WAKEUP 0 171 172#endif /* __KERNEL__ */ 173 174/* Conversion routines to/from brg time constants from/to bits 175 * per second. 176 */ 177#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) 178#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) 179 180/* The Zilog register set */ 181 182#define FLAG 0x7e 183 184/* Write Register 0 */ 185#define R0 0 /* Register selects */ 186#define R1 1 187#define R2 2 188#define R3 3 189#define R4 4 190#define R5 5 191#define R6 6 192#define R7 7 193#define R8 8 194#define R9 9 195#define R10 10 196#define R11 11 197#define R12 12 198#define R13 13 199#define R14 14 200#define R15 15 201 202#define NULLCODE 0 /* Null Code */ 203#define POINT_HIGH 0x8 /* Select upper half of registers */ 204#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 205#define SEND_ABORT 0x18 /* HDLC Abort */ 206#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 207#define RES_Tx_P 0x28 /* Reset TxINT Pending */ 208#define ERR_RES 0x30 /* Error Reset */ 209#define RES_H_IUS 0x38 /* Reset highest IUS */ 210 211#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 212#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 213#define RES_EOM_L 0xC0 /* Reset EOM latch */ 214 215/* Write Register 1 */ 216 217#define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 218#define TxINT_ENAB 0x2 /* Tx Int Enable */ 219#define PAR_SPEC 0x4 /* Parity is special condition */ 220 221#define RxINT_DISAB 0 /* Rx Int Disable */ 222#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ 223#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ 224#define INT_ERR_Rx 0x18 /* Int on error only */ 225#define RxINT_MASK 0x18 226 227#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */ 228#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */ 229#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */ 230 231/* Write Register #2 (Interrupt Vector) */ 232 233/* Write Register 3 */ 234 235#define RxENAB 0x1 /* Rx Enable */ 236#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ 237#define ADD_SM 0x4 /* Address Search Mode (SDLC) */ 238#define RxCRC_ENAB 0x8 /* Rx CRC Enable */ 239#define ENT_HM 0x10 /* Enter Hunt Mode */ 240#define AUTO_ENAB 0x20 /* Auto Enables */ 241#define Rx5 0x0 /* Rx 5 Bits/Character */ 242#define Rx7 0x40 /* Rx 7 Bits/Character */ 243#define Rx6 0x80 /* Rx 6 Bits/Character */ 244#define Rx8 0xc0 /* Rx 8 Bits/Character */ 245#define RxN_MASK 0xc0 246 247/* Write Register 4 */ 248 249#define PAR_ENAB 0x1 /* Parity Enable */ 250#define PAR_EVEN 0x2 /* Parity Even/Odd* */ 251 252#define SYNC_ENAB 0 /* Sync Modes Enable */ 253#define SB1 0x4 /* 1 stop bit/char */ 254#define SB15 0x8 /* 1.5 stop bits/char */ 255#define SB2 0xc /* 2 stop bits/char */ 256 257#define MONSYNC 0 /* 8 Bit Sync character */ 258#define BISYNC 0x10 /* 16 bit sync character */ 259#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ 260#define EXTSYNC 0x30 /* External Sync Mode */ 261 262#define X1CLK 0x0 /* x1 clock mode */ 263#define X16CLK 0x40 /* x16 clock mode */ 264#define X32CLK 0x80 /* x32 clock mode */ 265#define X64CLK 0xC0 /* x64 clock mode */ 266 267/* Write Register 5 */ 268 269#define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 270#define RTS 0x2 /* RTS */ 271#define SDLC_CRC 0x4 /* SDLC/CRC-16 */ 272#define TxENAB 0x8 /* Tx Enable */ 273#define SND_BRK 0x10 /* Send Break */ 274#define Tx5 0x0 /* Tx 5 bits (or less)/character */ 275#define Tx7 0x20 /* Tx 7 bits/character */ 276#define Tx6 0x40 /* Tx 6 bits/character */ 277#define Tx8 0x60 /* Tx 8 bits/character */ 278#define TxN_MASK 0x60 279#define DTR 0x80 /* DTR */ 280 281/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ 282 283/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ 284 285/* Write Register 8 (transmit buffer) */ 286 287/* Write Register 9 (Master interrupt control) */ 288#define VIS 1 /* Vector Includes Status */ 289#define NV 2 /* No Vector */ 290#define DLC 4 /* Disable Lower Chain */ 291#define MIE 8 /* Master Interrupt Enable */ 292#define STATHI 0x10 /* Status high */ 293#define NORESET 0 /* No reset on write to R9 */ 294#define CHRB 0x40 /* Reset channel B */ 295#define CHRA 0x80 /* Reset channel A */ 296#define FHWRES 0xc0 /* Force hardware reset */ 297 298/* Write Register 10 (misc control bits) */ 299#define BIT6 1 /* 6 bit/8bit sync */ 300#define LOOPMODE 2 /* SDLC Loop mode */ 301#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ 302#define MARKIDLE 8 /* Mark/flag on idle */ 303#define GAOP 0x10 /* Go active on poll */ 304#define NRZ 0 /* NRZ mode */ 305#define NRZI 0x20 /* NRZI mode */ 306#define FM1 0x40 /* FM1 (transition = 1) */ 307#define FM0 0x60 /* FM0 (transition = 0) */ 308#define CRCPS 0x80 /* CRC Preset I/O */ 309 310/* Write Register 11 (Clock Mode control) */ 311#define TRxCXT 0 /* TRxC = Xtal output */ 312#define TRxCTC 1 /* TRxC = Transmit clock */ 313#define TRxCBR 2 /* TRxC = BR Generator Output */ 314#define TRxCDP 3 /* TRxC = DPLL output */ 315#define TRxCOI 4 /* TRxC O/I */ 316#define TCRTxCP 0 /* Transmit clock = RTxC pin */ 317#define TCTRxCP 8 /* Transmit clock = TRxC pin */ 318#define TCBR 0x10 /* Transmit clock = BR Generator output */ 319#define TCDPLL 0x18 /* Transmit clock = DPLL output */ 320#define RCRTxCP 0 /* Receive clock = RTxC pin */ 321#define RCTRxCP 0x20 /* Receive clock = TRxC pin */ 322#define RCBR 0x40 /* Receive clock = BR Generator output */ 323#define RCDPLL 0x60 /* Receive clock = DPLL output */ 324#define RTxCX 0x80 /* RTxC Xtal/No Xtal */ 325 326/* Write Register 12 (lower byte of baud rate generator time constant) */ 327 328/* Write Register 13 (upper byte of baud rate generator time constant) */ 329 330/* Write Register 14 (Misc control bits) */ 331#define BRENAB 1 /* Baud rate generator enable */ 332#define BRSRC 2 /* Baud rate generator source */ 333#define DTRREQ 4 /* DTR/Request function */ 334#define AUTOECHO 8 /* Auto Echo */ 335#define LOOPBAK 0x10 /* Local loopback */ 336#define SEARCH 0x20 /* Enter search mode */ 337#define RMC 0x40 /* Reset missing clock */ 338#define DISDPLL 0x60 /* Disable DPLL */ 339#define SSBR 0x80 /* Set DPLL source = BR generator */ 340#define SSRTxC 0xa0 /* Set DPLL source = RTxC */ 341#define SFMM 0xc0 /* Set FM mode */ 342#define SNRZI 0xe0 /* Set NRZI mode */ 343 344/* Write Register 15 (external/status interrupt control) */ 345#define ZCIE 2 /* Zero count IE */ 346#define DCDIE 8 /* DCD IE */ 347#define SYNCIE 0x10 /* Sync/hunt IE */ 348#define CTSIE 0x20 /* CTS IE */ 349#define TxUIE 0x40 /* Tx Underrun/EOM IE */ 350#define BRKIE 0x80 /* Break/Abort IE */ 351 352 353/* Read Register 0 */ 354#define Rx_CH_AV 0x1 /* Rx Character Available */ 355#define ZCOUNT 0x2 /* Zero count */ 356#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */ 357#define DCD 0x8 /* DCD */ 358#define SYNC 0x10 /* Sync/hunt */ 359#define CTS 0x20 /* CTS */ 360#define TxEOM 0x40 /* Tx underrun */ 361#define BRK_ABRT 0x80 /* Break/Abort */ 362 363/* Read Register 1 */ 364#define ALL_SNT 0x1 /* All sent */ 365/* Residue Data for 8 Rx bits/char programmed */ 366#define RES3 0x8 /* 0/3 */ 367#define RES4 0x4 /* 0/4 */ 368#define RES5 0xc /* 0/5 */ 369#define RES6 0x2 /* 0/6 */ 370#define RES7 0xa /* 0/7 */ 371#define RES8 0x6 /* 0/8 */ 372#define RES18 0xe /* 1/8 */ 373#define RES28 0x0 /* 2/8 */ 374/* Special Rx Condition Interrupts */ 375#define PAR_ERR 0x10 /* Parity error */ 376#define Rx_OVR 0x20 /* Rx Overrun Error */ 377#define CRC_ERR 0x40 /* CRC/Framing Error */ 378#define END_FR 0x80 /* End of Frame (SDLC) */ 379 380/* Read Register 2 (channel b only) - Interrupt vector */ 381#define CHB_Tx_EMPTY 0x00 382#define CHB_EXT_STAT 0x02 383#define CHB_Rx_AVAIL 0x04 384#define CHB_SPECIAL 0x06 385#define CHA_Tx_EMPTY 0x08 386#define CHA_EXT_STAT 0x0a 387#define CHA_Rx_AVAIL 0x0c 388#define CHA_SPECIAL 0x0e 389#define STATUS_MASK 0x0e 390 391/* Read Register 3 (interrupt pending register) ch a only */ 392#define CHBEXT 0x1 /* Channel B Ext/Stat IP */ 393#define CHBTxIP 0x2 /* Channel B Tx IP */ 394#define CHBRxIP 0x4 /* Channel B Rx IP */ 395#define CHAEXT 0x8 /* Channel A Ext/Stat IP */ 396#define CHATxIP 0x10 /* Channel A Tx IP */ 397#define CHARxIP 0x20 /* Channel A Rx IP */ 398 399/* Read Register 8 (receive data register) */ 400 401/* Read Register 10 (misc status bits) */ 402#define ONLOOP 2 /* On loop */ 403#define LOOPSEND 0x10 /* Loop sending */ 404#define CLK2MIS 0x40 /* Two clocks missing */ 405#define CLK1MIS 0x80 /* One clock missing */ 406 407/* Read Register 12 (lower byte of baud rate generator constant) */ 408 409/* Read Register 13 (upper byte of baud rate generator constant) */ 410 411/* Read Register 15 (value of WR 15) */ 412 413/* Misc macros */ 414#define ZS_CLEARERR(channel) do { sbus_writeb(ERR_RES, &channel->control); \ 415 udelay(5); } while(0) 416 417#define ZS_CLEARSTAT(channel) do { sbus_writeb(RES_EXT_INT, &channel->control); \ 418 udelay(5); } while(0) 419 420#define ZS_CLEARFIFO(channel) do { sbus_readb(&channel->data); \ 421 udelay(2); \ 422 sbus_readb(&channel->data); \ 423 udelay(2); \ 424 sbus_readb(&channel->data); \ 425 udelay(2); } while(0) 426 427#endif /* !(_ZS_H) */ 428