1/* $Id: sungem.h,v 1.1.1.1 2008/10/15 03:26:40 james26_jang Exp $ 2 * sungem.h: Definitions for Sun GEM ethernet driver. 3 * 4 * Copyright (C) 2000 David S. Miller (davem@redhat.com) 5 */ 6 7#ifndef _SUNGEM_H 8#define _SUNGEM_H 9 10/* Global Registers */ 11#define GREG_SEBSTATE 0x0000UL /* SEB State Register */ 12#define GREG_CFG 0x0004UL /* Configuration Register */ 13#define GREG_STAT 0x000CUL /* Status Register */ 14#define GREG_IMASK 0x0010UL /* Interrupt Mask Register */ 15#define GREG_IACK 0x0014UL /* Interrupt ACK Register */ 16#define GREG_STAT2 0x001CUL /* Alias of GREG_STAT */ 17#define GREG_PCIESTAT 0x1000UL /* PCI Error Status Register */ 18#define GREG_PCIEMASK 0x1004UL /* PCI Error Mask Register */ 19#define GREG_BIFCFG 0x1008UL /* BIF Configuration Register */ 20#define GREG_BIFDIAG 0x100CUL /* BIF Diagnostics Register */ 21#define GREG_SWRST 0x1010UL /* Software Reset Register */ 22 23/* Global SEB State Register */ 24#define GREG_SEBSTATE_ARB 0x00000003 /* State of Arbiter */ 25#define GREG_SEBSTATE_RXWON 0x00000004 /* RX won internal arbitration */ 26 27/* Global Configuration Register */ 28#define GREG_CFG_IBURST 0x00000001 /* Infinite Burst */ 29#define GREG_CFG_TXDMALIM 0x0000003e /* TX DMA grant limit */ 30#define GREG_CFG_RXDMALIM 0x000007c0 /* RX DMA grant limit */ 31 32/* Global Interrupt Status Register. 33 * 34 * Reading this register automatically clears bits 0 through 6. 35 * This auto-clearing does not occur when the alias at GREG_STAT2 36 * is read instead. The rest of the interrupt bits only clear when 37 * the secondary interrupt status register corresponding to that 38 * bit is read (ie. if GREG_STAT_PCS is set, it will be cleared by 39 * reading PCS_ISTAT). 40 */ 41#define GREG_STAT_TXINTME 0x00000001 /* TX INTME frame transferred */ 42#define GREG_STAT_TXALL 0x00000002 /* All TX frames transferred */ 43#define GREG_STAT_TXDONE 0x00000004 /* One TX frame transferred */ 44#define GREG_STAT_RXDONE 0x00000010 /* One RX frame arrived */ 45#define GREG_STAT_RXNOBUF 0x00000020 /* No free RX buffers available */ 46#define GREG_STAT_RXTAGERR 0x00000040 /* RX tag framing is corrupt */ 47#define GREG_STAT_PCS 0x00002000 /* PCS signalled interrupt */ 48#define GREG_STAT_TXMAC 0x00004000 /* TX MAC signalled interrupt */ 49#define GREG_STAT_RXMAC 0x00008000 /* RX MAC signalled interrupt */ 50#define GREG_STAT_MAC 0x00010000 /* MAC Control signalled irq */ 51#define GREG_STAT_MIF 0x00020000 /* MIF signalled interrupt */ 52#define GREG_STAT_PCIERR 0x00040000 /* PCI Error interrupt */ 53#define GREG_STAT_TXNR 0xfff80000 /* == TXDMA_TXDONE reg val */ 54#define GREG_STAT_TXNR_SHIFT 19 55 56#define GREG_STAT_ABNORMAL (GREG_STAT_RXNOBUF | GREG_STAT_RXTAGERR | \ 57 GREG_STAT_PCS | GREG_STAT_TXMAC | GREG_STAT_RXMAC | \ 58 GREG_STAT_MAC | GREG_STAT_MIF | GREG_STAT_PCIERR) 59 60/* The layout of GREG_IMASK and GREG_IACK is identical to GREG_STAT. 61 * Bits set in GREG_IMASK will prevent that interrupt type from being 62 * signalled to the cpu. GREG_IACK can be used to clear specific top-level 63 * interrupt conditions in GREG_STAT, ie. it only works for bits 0 through 6. 64 * Setting the bit will clear that interrupt, clear bits will have no effect 65 * on GREG_STAT. 66 */ 67 68/* Global PCI Error Status Register */ 69#define GREG_PCIESTAT_BADACK 0x00000001 /* No ACK64# during ABS64 cycle */ 70#define GREG_PCIESTAT_DTRTO 0x00000002 /* Delayed transaction timeout */ 71#define GREG_PCIESTAT_OTHER 0x00000004 /* Other PCI error, check cfg space */ 72 73/* The layout of the GREG_PCIEMASK is identical to that of GREG_PCIESTAT. 74 * Bits set in GREG_PCIEMASK will prevent that interrupt type from being 75 * signalled to the cpu. 76 */ 77 78/* Global BIF Configuration Register */ 79#define GREG_BIFCFG_SLOWCLK 0x00000001 /* Set if PCI runs < 25Mhz */ 80#define GREG_BIFCFG_B64DIS 0x00000002 /* Disable 64bit wide data cycle*/ 81#define GREG_BIFCFG_M66EN 0x00000004 /* Set if on 66Mhz PCI segment */ 82 83/* Global BIF Diagnostics Register */ 84#define GREG_BIFDIAG_BURSTSM 0x007f0000 /* PCI Burst state machine */ 85#define GREG_BIFDIAG_BIFSM 0xff000000 /* BIF state machine */ 86 87/* Global Software Reset Register. 88 * 89 * This register is used to perform a global reset of the RX and TX portions 90 * of the GEM asic. Setting the RX or TX reset bit will start the reset. 91 * The driver _MUST_ poll these bits until they clear. One may not attempt 92 * to program any other part of GEM until the bits clear. 93 */ 94#define GREG_SWRST_TXRST 0x00000001 /* TX Software Reset */ 95#define GREG_SWRST_RXRST 0x00000002 /* RX Software Reset */ 96#define GREG_SWRST_RSTOUT 0x00000004 /* Force RST# pin active */ 97#define GREG_SWRST_CACHESIZE 0x00ff0000 /* RIO only: cache line size */ 98#define GREG_SWRST_CACHE_SHIFT 16 99 100/* TX DMA Registers */ 101#define TXDMA_KICK 0x2000UL /* TX Kick Register */ 102#define TXDMA_CFG 0x2004UL /* TX Configuration Register */ 103#define TXDMA_DBLOW 0x2008UL /* TX Desc. Base Low */ 104#define TXDMA_DBHI 0x200CUL /* TX Desc. Base High */ 105#define TXDMA_FWPTR 0x2014UL /* TX FIFO Write Pointer */ 106#define TXDMA_FSWPTR 0x2018UL /* TX FIFO Shadow Write Pointer */ 107#define TXDMA_FRPTR 0x201CUL /* TX FIFO Read Pointer */ 108#define TXDMA_FSRPTR 0x2020UL /* TX FIFO Shadow Read Pointer */ 109#define TXDMA_PCNT 0x2024UL /* TX FIFO Packet Counter */ 110#define TXDMA_SMACHINE 0x2028UL /* TX State Machine Register */ 111#define TXDMA_DPLOW 0x2030UL /* TX Data Pointer Low */ 112#define TXDMA_DPHI 0x2034UL /* TX Data Pointer High */ 113#define TXDMA_TXDONE 0x2100UL /* TX Completion Register */ 114#define TXDMA_FADDR 0x2104UL /* TX FIFO Address */ 115#define TXDMA_FTAG 0x2108UL /* TX FIFO Tag */ 116#define TXDMA_DLOW 0x210CUL /* TX FIFO Data Low */ 117#define TXDMA_DHIT1 0x2110UL /* TX FIFO Data HighT1 */ 118#define TXDMA_DHIT0 0x2114UL /* TX FIFO Data HighT0 */ 119#define TXDMA_FSZ 0x2118UL /* TX FIFO Size */ 120 121/* TX Kick Register. 122 * 123 * This 13-bit register is programmed by the driver to hold the descriptor 124 * entry index which follows the last valid transmit descriptor. 125 */ 126 127/* TX Completion Register. 128 * 129 * This 13-bit register is updated by GEM to hold to descriptor entry index 130 * which follows the last descriptor already processed by GEM. Note that 131 * this value is mirrored in GREG_STAT which eliminates the need to even 132 * access this register in the driver during interrupt processing. 133 */ 134 135/* TX Configuration Register. 136 * 137 * Note that TXDMA_CFG_FTHRESH, the TX FIFO Threshold, is an obsolete feature 138 * that was meant to be used with jumbo packets. It should be set to the 139 * maximum value of 0x4ff, else one risks getting TX MAC Underrun errors. 140 */ 141#define TXDMA_CFG_ENABLE 0x00000001 /* Enable TX DMA channel */ 142#define TXDMA_CFG_RINGSZ 0x0000001e /* TX descriptor ring size */ 143#define TXDMA_CFG_RINGSZ_32 0x00000000 /* 32 TX descriptors */ 144#define TXDMA_CFG_RINGSZ_64 0x00000002 /* 64 TX descriptors */ 145#define TXDMA_CFG_RINGSZ_128 0x00000004 /* 128 TX descriptors */ 146#define TXDMA_CFG_RINGSZ_256 0x00000006 /* 256 TX descriptors */ 147#define TXDMA_CFG_RINGSZ_512 0x00000008 /* 512 TX descriptors */ 148#define TXDMA_CFG_RINGSZ_1K 0x0000000a /* 1024 TX descriptors */ 149#define TXDMA_CFG_RINGSZ_2K 0x0000000c /* 2048 TX descriptors */ 150#define TXDMA_CFG_RINGSZ_4K 0x0000000e /* 4096 TX descriptors */ 151#define TXDMA_CFG_RINGSZ_8K 0x00000010 /* 8192 TX descriptors */ 152#define TXDMA_CFG_PIOSEL 0x00000020 /* Enable TX FIFO PIO from cpu */ 153#define TXDMA_CFG_FTHRESH 0x001ffc00 /* TX FIFO Threshold, obsolete */ 154#define TXDMA_CFG_PMODE 0x00200000 /* TXALL irq means TX FIFO empty*/ 155 156/* TX Descriptor Base Low/High. 157 * 158 * These two registers store the 53 most significant bits of the base address 159 * of the TX descriptor table. The 11 least significant bits are always 160 * zero. As a result, the TX descriptor table must be 2K aligned. 161 */ 162 163/* The rest of the TXDMA_* registers are for diagnostics and debug, I will document 164 * them later. -DaveM 165 */ 166 167/* Receive DMA Registers */ 168#define RXDMA_CFG 0x4000UL /* RX Configuration Register */ 169#define RXDMA_DBLOW 0x4004UL /* RX Descriptor Base Low */ 170#define RXDMA_DBHI 0x4008UL /* RX Descriptor Base High */ 171#define RXDMA_FWPTR 0x400CUL /* RX FIFO Write Pointer */ 172#define RXDMA_FSWPTR 0x4010UL /* RX FIFO Shadow Write Pointer */ 173#define RXDMA_FRPTR 0x4014UL /* RX FIFO Read Pointer */ 174#define RXDMA_PCNT 0x4018UL /* RX FIFO Packet Counter */ 175#define RXDMA_SMACHINE 0x401CUL /* RX State Machine Register */ 176#define RXDMA_PTHRESH 0x4020UL /* Pause Thresholds */ 177#define RXDMA_DPLOW 0x4024UL /* RX Data Pointer Low */ 178#define RXDMA_DPHI 0x4028UL /* RX Data Pointer High */ 179#define RXDMA_KICK 0x4100UL /* RX Kick Register */ 180#define RXDMA_DONE 0x4104UL /* RX Completion Register */ 181#define RXDMA_BLANK 0x4108UL /* RX Blanking Register */ 182#define RXDMA_FADDR 0x410CUL /* RX FIFO Address */ 183#define RXDMA_FTAG 0x4110UL /* RX FIFO Tag */ 184#define RXDMA_DLOW 0x4114UL /* RX FIFO Data Low */ 185#define RXDMA_DHIT1 0x4118UL /* RX FIFO Data HighT0 */ 186#define RXDMA_DHIT0 0x411CUL /* RX FIFO Data HighT1 */ 187#define RXDMA_FSZ 0x4120UL /* RX FIFO Size */ 188 189/* RX Configuration Register. */ 190#define RXDMA_CFG_ENABLE 0x00000001 /* Enable RX DMA channel */ 191#define RXDMA_CFG_RINGSZ 0x0000001e /* RX descriptor ring size */ 192#define RXDMA_CFG_RINGSZ_32 0x00000000 /* - 32 entries */ 193#define RXDMA_CFG_RINGSZ_64 0x00000002 /* - 64 entries */ 194#define RXDMA_CFG_RINGSZ_128 0x00000004 /* - 128 entries */ 195#define RXDMA_CFG_RINGSZ_256 0x00000006 /* - 256 entries */ 196#define RXDMA_CFG_RINGSZ_512 0x00000008 /* - 512 entries */ 197#define RXDMA_CFG_RINGSZ_1K 0x0000000a /* - 1024 entries */ 198#define RXDMA_CFG_RINGSZ_2K 0x0000000c /* - 2048 entries */ 199#define RXDMA_CFG_RINGSZ_4K 0x0000000e /* - 4096 entries */ 200#define RXDMA_CFG_RINGSZ_8K 0x00000010 /* - 8192 entries */ 201#define RXDMA_CFG_RINGSZ_BDISAB 0x00000020 /* Disable RX desc batching */ 202#define RXDMA_CFG_FBOFF 0x00001c00 /* Offset of first data byte */ 203#define RXDMA_CFG_CSUMOFF 0x000fe000 /* Skip bytes before csum calc */ 204#define RXDMA_CFG_FTHRESH 0x07000000 /* RX FIFO dma start threshold */ 205#define RXDMA_CFG_FTHRESH_64 0x00000000 /* - 64 bytes */ 206#define RXDMA_CFG_FTHRESH_128 0x01000000 /* - 128 bytes */ 207#define RXDMA_CFG_FTHRESH_256 0x02000000 /* - 256 bytes */ 208#define RXDMA_CFG_FTHRESH_512 0x03000000 /* - 512 bytes */ 209#define RXDMA_CFG_FTHRESH_1K 0x04000000 /* - 1024 bytes */ 210#define RXDMA_CFG_FTHRESH_2K 0x05000000 /* - 2048 bytes */ 211 212/* RX Descriptor Base Low/High. 213 * 214 * These two registers store the 53 most significant bits of the base address 215 * of the RX descriptor table. The 11 least significant bits are always 216 * zero. As a result, the RX descriptor table must be 2K aligned. 217 */ 218 219/* RX PAUSE Thresholds. 220 * 221 * These values determine when XOFF and XON PAUSE frames are emitted by 222 * GEM. The thresholds measure RX FIFO occupancy in units of 64 bytes. 223 */ 224#define RXDMA_PTHRESH_OFF 0x000001ff /* XOFF emitted w/FIFO > this */ 225#define RXDMA_PTHRESH_ON 0x001ff000 /* XON emitted w/FIFO < this */ 226 227/* RX Kick Register. 228 * 229 * This 13-bit register is written by the host CPU and holds the last 230 * valid RX descriptor number plus one. This is, if 'N' is written to 231 * this register, it means that all RX descriptors up to but excluding 232 * 'N' are valid. 233 * 234 * The hardware requires that RX descriptors are posted in increments 235 * of 4. This means 'N' must be a multiple of four. For the best 236 * performance, the first new descriptor being posted should be (PCI) 237 * cache line aligned. 238 */ 239 240/* RX Completion Register. 241 * 242 * This 13-bit register is updated by GEM to indicate which RX descriptors 243 * have already been used for receive frames. All descriptors up to but 244 * excluding the value in this register are ready to be processed. GEM 245 * updates this register value after the RX FIFO empties completely into 246 * the RX descriptor's buffer, but before the RX_DONE bit is set in the 247 * interrupt status register. 248 */ 249 250/* RX Blanking Register. */ 251#define RXDMA_BLANK_IPKTS 0x000001ff /* RX_DONE asserted after this 252 * many packets received since 253 * previous RX_DONE. 254 */ 255#define RXDMA_BLANK_ITIME 0x000ff000 /* RX_DONE asserted after this 256 * many clocks (measured in 2048 257 * PCI clocks) were counted since 258 * the previous RX_DONE. 259 */ 260 261/* RX FIFO Size. 262 * 263 * This 11-bit read-only register indicates how large, in units of 64-bytes, 264 * the RX FIFO is. The driver uses this to properly configure the RX PAUSE 265 * thresholds. 266 */ 267 268/* The rest of the RXDMA_* registers are for diagnostics and debug, I will document 269 * them later. -DaveM 270 */ 271 272/* MAC Registers */ 273#define MAC_TXRST 0x6000UL /* TX MAC Software Reset Command*/ 274#define MAC_RXRST 0x6004UL /* RX MAC Software Reset Command*/ 275#define MAC_SNDPAUSE 0x6008UL /* Send Pause Command Register */ 276#define MAC_TXSTAT 0x6010UL /* TX MAC Status Register */ 277#define MAC_RXSTAT 0x6014UL /* RX MAC Status Register */ 278#define MAC_CSTAT 0x6018UL /* MAC Control Status Register */ 279#define MAC_TXMASK 0x6020UL /* TX MAC Mask Register */ 280#define MAC_RXMASK 0x6024UL /* RX MAC Mask Register */ 281#define MAC_MCMASK 0x6028UL /* MAC Control Mask Register */ 282#define MAC_TXCFG 0x6030UL /* TX MAC Configuration Register*/ 283#define MAC_RXCFG 0x6034UL /* RX MAC Configuration Register*/ 284#define MAC_MCCFG 0x6038UL /* MAC Control Config Register */ 285#define MAC_XIFCFG 0x603CUL /* XIF Configuration Register */ 286#define MAC_IPG0 0x6040UL /* InterPacketGap0 Register */ 287#define MAC_IPG1 0x6044UL /* InterPacketGap1 Register */ 288#define MAC_IPG2 0x6048UL /* InterPacketGap2 Register */ 289#define MAC_STIME 0x604CUL /* SlotTime Register */ 290#define MAC_MINFSZ 0x6050UL /* MinFrameSize Register */ 291#define MAC_MAXFSZ 0x6054UL /* MaxFrameSize Register */ 292#define MAC_PASIZE 0x6058UL /* PA Size Register */ 293#define MAC_JAMSIZE 0x605CUL /* JamSize Register */ 294#define MAC_ATTLIM 0x6060UL /* Attempt Limit Register */ 295#define MAC_MCTYPE 0x6064UL /* MAC Control Type Register */ 296#define MAC_ADDR0 0x6080UL /* MAC Address 0 Register */ 297#define MAC_ADDR1 0x6084UL /* MAC Address 1 Register */ 298#define MAC_ADDR2 0x6088UL /* MAC Address 2 Register */ 299#define MAC_ADDR3 0x608CUL /* MAC Address 3 Register */ 300#define MAC_ADDR4 0x6090UL /* MAC Address 4 Register */ 301#define MAC_ADDR5 0x6094UL /* MAC Address 5 Register */ 302#define MAC_ADDR6 0x6098UL /* MAC Address 6 Register */ 303#define MAC_ADDR7 0x609CUL /* MAC Address 7 Register */ 304#define MAC_ADDR8 0x60A0UL /* MAC Address 8 Register */ 305#define MAC_AFILT0 0x60A4UL /* Address Filter 0 Register */ 306#define MAC_AFILT1 0x60A8UL /* Address Filter 1 Register */ 307#define MAC_AFILT2 0x60ACUL /* Address Filter 2 Register */ 308#define MAC_AF21MSK 0x60B0UL /* Address Filter 2&1 Mask Reg */ 309#define MAC_AF0MSK 0x60B4UL /* Address Filter 0 Mask Reg */ 310#define MAC_HASH0 0x60C0UL /* Hash Table 0 Register */ 311#define MAC_HASH1 0x60C4UL /* Hash Table 1 Register */ 312#define MAC_HASH2 0x60C8UL /* Hash Table 2 Register */ 313#define MAC_HASH3 0x60CCUL /* Hash Table 3 Register */ 314#define MAC_HASH4 0x60D0UL /* Hash Table 4 Register */ 315#define MAC_HASH5 0x60D4UL /* Hash Table 5 Register */ 316#define MAC_HASH6 0x60D8UL /* Hash Table 6 Register */ 317#define MAC_HASH7 0x60DCUL /* Hash Table 7 Register */ 318#define MAC_HASH8 0x60E0UL /* Hash Table 8 Register */ 319#define MAC_HASH9 0x60E4UL /* Hash Table 9 Register */ 320#define MAC_HASH10 0x60E8UL /* Hash Table 10 Register */ 321#define MAC_HASH11 0x60ECUL /* Hash Table 11 Register */ 322#define MAC_HASH12 0x60F0UL /* Hash Table 12 Register */ 323#define MAC_HASH13 0x60F4UL /* Hash Table 13 Register */ 324#define MAC_HASH14 0x60F8UL /* Hash Table 14 Register */ 325#define MAC_HASH15 0x60FCUL /* Hash Table 15 Register */ 326#define MAC_NCOLL 0x6100UL /* Normal Collision Counter */ 327#define MAC_FASUCC 0x6104UL /* First Attmpt. Succ Coll Ctr. */ 328#define MAC_ECOLL 0x6108UL /* Excessive Collision Counter */ 329#define MAC_LCOLL 0x610CUL /* Late Collision Counter */ 330#define MAC_DTIMER 0x6110UL /* Defer Timer */ 331#define MAC_PATMPS 0x6114UL /* Peak Attempts Register */ 332#define MAC_RFCTR 0x6118UL /* Receive Frame Counter */ 333#define MAC_LERR 0x611CUL /* Length Error Counter */ 334#define MAC_AERR 0x6120UL /* Alignment Error Counter */ 335#define MAC_FCSERR 0x6124UL /* FCS Error Counter */ 336#define MAC_RXCVERR 0x6128UL /* RX code Violation Error Ctr */ 337#define MAC_RANDSEED 0x6130UL /* Random Number Seed Register */ 338#define MAC_SMACHINE 0x6134UL /* State Machine Register */ 339 340/* TX MAC Software Reset Command. */ 341#define MAC_TXRST_CMD 0x00000001 /* Start sw reset, self-clears */ 342 343/* RX MAC Software Reset Command. */ 344#define MAC_RXRST_CMD 0x00000001 /* Start sw reset, self-clears */ 345 346/* Send Pause Command. */ 347#define MAC_SNDPAUSE_TS 0x0000ffff /* The pause_time operand used in 348 * Send_Pause and flow-control 349 * handshakes. 350 */ 351#define MAC_SNDPAUSE_SP 0x00010000 /* Setting this bit instructs the MAC 352 * to send a Pause Flow Control 353 * frame onto the network. 354 */ 355 356/* TX MAC Status Register. */ 357#define MAC_TXSTAT_XMIT 0x00000001 /* Frame Transmitted */ 358#define MAC_TXSTAT_URUN 0x00000002 /* TX Underrun */ 359#define MAC_TXSTAT_MPE 0x00000004 /* Max Packet Size Error */ 360#define MAC_TXSTAT_NCE 0x00000008 /* Normal Collision Cntr Expire */ 361#define MAC_TXSTAT_ECE 0x00000010 /* Excess Collision Cntr Expire */ 362#define MAC_TXSTAT_LCE 0x00000020 /* Late Collision Cntr Expire */ 363#define MAC_TXSTAT_FCE 0x00000040 /* First Collision Cntr Expire */ 364#define MAC_TXSTAT_DTE 0x00000080 /* Defer Timer Expire */ 365#define MAC_TXSTAT_PCE 0x00000100 /* Peak Attempts Cntr Expire */ 366 367/* RX MAC Status Register. */ 368#define MAC_RXSTAT_RCV 0x00000001 /* Frame Received */ 369#define MAC_RXSTAT_OFLW 0x00000002 /* Receive Overflow */ 370#define MAC_RXSTAT_FCE 0x00000004 /* Frame Cntr Expire */ 371#define MAC_RXSTAT_ACE 0x00000008 /* Align Error Cntr Expire */ 372#define MAC_RXSTAT_CCE 0x00000010 /* CRC Error Cntr Expire */ 373#define MAC_RXSTAT_LCE 0x00000020 /* Length Error Cntr Expire */ 374#define MAC_RXSTAT_VCE 0x00000040 /* Code Violation Cntr Expire */ 375 376/* MAC Control Status Register. */ 377#define MAC_CSTAT_PRCV 0x00000001 /* Pause Received */ 378#define MAC_CSTAT_PS 0x00000002 /* Paused State */ 379#define MAC_CSTAT_NPS 0x00000004 /* Not Paused State */ 380#define MAC_CSTAT_PTR 0xffff0000 /* Pause Time Received */ 381 382/* The layout of the MAC_{TX,RX,C}MASK registers is identical to that 383 * of MAC_{TX,RX,C}STAT. Bits set in MAC_{TX,RX,C}MASK will prevent 384 * that interrupt type from being signalled to front end of GEM. For 385 * the interrupt to actually get sent to the cpu, it is necessary to 386 * properly set the appropriate GREG_IMASK_{TX,RX,}MAC bits as well. 387 */ 388 389/* TX MAC Configuration Register. 390 * 391 * NOTE: The TX MAC Enable bit must be cleared and polled until 392 * zero before any other bits in this register are changed. 393 * 394 * Also, enabling the Carrier Extension feature of GEM is 395 * a 3 step process 1) Set TX Carrier Extension 2) Set 396 * RX Carrier Extension 3) Set Slot Time to 0x200. This 397 * mode must be enabled when in half-duplex at 1Gbps, else 398 * it must be disabled. 399 */ 400#define MAC_TXCFG_ENAB 0x00000001 /* TX MAC Enable */ 401#define MAC_TXCFG_ICS 0x00000002 /* Ignore Carrier Sense */ 402#define MAC_TXCFG_ICOLL 0x00000004 /* Ignore Collisions */ 403#define MAC_TXCFG_EIPG0 0x00000008 /* Enable IPG0 */ 404#define MAC_TXCFG_NGU 0x00000010 /* Never Give Up */ 405#define MAC_TXCFG_NGUL 0x00000020 /* Never Give Up Limit */ 406#define MAC_TXCFG_NBO 0x00000040 /* No Backoff */ 407#define MAC_TXCFG_SD 0x00000080 /* Slow Down */ 408#define MAC_TXCFG_NFCS 0x00000100 /* No FCS */ 409#define MAC_TXCFG_TCE 0x00000200 /* TX Carrier Extension */ 410 411/* RX MAC Configuration Register. 412 * 413 * NOTE: The RX MAC Enable bit must be cleared and polled until 414 * zero before any other bits in this register are changed. 415 * 416 * Similar rules apply to the Hash Filter Enable bit when 417 * programming the hash table registers, and the Address Filter 418 * Enable bit when programming the address filter registers. 419 */ 420#define MAC_RXCFG_ENAB 0x00000001 /* RX MAC Enable */ 421#define MAC_RXCFG_SPAD 0x00000002 /* Strip Pad */ 422#define MAC_RXCFG_SFCS 0x00000004 /* Strip FCS */ 423#define MAC_RXCFG_PROM 0x00000008 /* Promiscuous Mode */ 424#define MAC_RXCFG_PGRP 0x00000010 /* Promiscuous Group */ 425#define MAC_RXCFG_HFE 0x00000020 /* Hash Filter Enable */ 426#define MAC_RXCFG_AFE 0x00000040 /* Address Filter Enable */ 427#define MAC_RXCFG_DDE 0x00000080 /* Disable Discard on Error */ 428#define MAC_RXCFG_RCE 0x00000100 /* RX Carrier Extension */ 429 430/* MAC Control Config Register. */ 431#define MAC_MCCFG_SPE 0x00000001 /* Send Pause Enable */ 432#define MAC_MCCFG_RPE 0x00000002 /* Receive Pause Enable */ 433#define MAC_MCCFG_PMC 0x00000004 /* Pass MAC Control */ 434 435/* XIF Configuration Register. 436 * 437 * NOTE: When leaving or entering loopback mode, a global hardware 438 * init of GEM should be performed. 439 */ 440#define MAC_XIFCFG_OE 0x00000001 /* MII TX Output Driver Enable */ 441#define MAC_XIFCFG_LBCK 0x00000002 /* Loopback TX to RX */ 442#define MAC_XIFCFG_DISE 0x00000004 /* Disable RX path during TX */ 443#define MAC_XIFCFG_GMII 0x00000008 /* Use GMII clocks + datapath */ 444#define MAC_XIFCFG_MBOE 0x00000010 /* Controls MII_BUF_EN pin */ 445#define MAC_XIFCFG_LLED 0x00000020 /* Force LINKLED# active (low) */ 446#define MAC_XIFCFG_FLED 0x00000040 /* Force FDPLXLED# active (low) */ 447 448/* InterPacketGap0 Register. This 8-bit value is used as an extension 449 * to the InterPacketGap1 Register. Specifically it contributes to the 450 * timing of the RX-to-TX IPG. This value is ignored and presumed to 451 * be zero for TX-to-TX IPG calculations and/or when the Enable IPG0 bit 452 * is cleared in the TX MAC Configuration Register. 453 * 454 * This value in this register in terms of media byte time. 455 * 456 * Recommended value: 0x00 457 */ 458 459/* InterPacketGap1 Register. This 8-bit value defines the first 2/3 460 * portion of the Inter Packet Gap. 461 * 462 * This value in this register in terms of media byte time. 463 * 464 * Recommended value: 0x08 465 */ 466 467/* InterPacketGap2 Register. This 8-bit value defines the second 1/3 468 * portion of the Inter Packet Gap. 469 * 470 * This value in this register in terms of media byte time. 471 * 472 * Recommended value: 0x04 473 */ 474 475/* Slot Time Register. This 10-bit value specifies the slot time 476 * parameter in units of media byte time. It determines the physical 477 * span of the network. 478 * 479 * Recommended value: 0x40 480 */ 481 482/* Minimum Frame Size Register. This 10-bit register specifies the 483 * smallest sized frame the TXMAC will send onto the medium, and the 484 * RXMAC will receive from the medium. 485 * 486 * Recommended value: 0x40 487 */ 488 489/* Maximum Frame and Burst Size Register. 490 * 491 * This register specifies two things. First it specifies the maximum 492 * sized frame the TXMAC will send and the RXMAC will recognize as 493 * valid. Second, it specifies the maximum run length of a burst of 494 * packets sent in half-duplex gigabit modes. 495 * 496 * Recommended value: 0x200005ee 497 */ 498#define MAC_MAXFSZ_MFS 0x00007fff /* Max Frame Size */ 499#define MAC_MAXFSZ_MBS 0x7fff0000 /* Max Burst Size */ 500 501/* PA Size Register. This 10-bit register specifies the number of preamble 502 * bytes which will be transmitted at the beginning of each frame. A 503 * value of two or greater should be programmed here. 504 * 505 * Recommended value: 0x07 506 */ 507 508/* Jam Size Register. This 4-bit register specifies the duration of 509 * the jam in units of media byte time. 510 * 511 * Recommended value: 0x04 512 */ 513 514/* Attempts Limit Register. This 8-bit register specifies the number 515 * of attempts that the TXMAC will make to transmit a frame, before it 516 * resets its Attempts Counter. After reaching the Attempts Limit the 517 * TXMAC may or may not drop the frame, as determined by the NGU 518 * (Never Give Up) and NGUL (Never Give Up Limit) bits in the TXMAC 519 * Configuration Register. 520 * 521 * Recommended value: 0x10 522 */ 523 524/* MAX Control Type Register. This 16-bit register specifies the 525 * "type" field of a MAC Control frame. The TXMAC uses this field to 526 * encapsulate the MAC Control frame for transmission, and the RXMAC 527 * uses it for decoding valid MAC Control frames received from the 528 * network. 529 * 530 * Recommended value: 0x8808 531 */ 532 533/* MAC Address Registers. Each of these registers specify the 534 * ethernet MAC of the interface, 16-bits at a time. Register 535 * 0 specifies bits [47:32], register 1 bits [31:16], and register 536 * 2 bits [15:0]. 537 * 538 * Registers 3 through and including 5 specify an alternate 539 * MAC address for the interface. 540 * 541 * Registers 6 through and including 8 specify the MAC Control 542 * Address, which must be the reserved multicast address for MAC 543 * Control frames. 544 * 545 * Example: To program primary station address a:b:c:d:e:f into 546 * the chip. 547 * MAC_Address_2 = (a << 8) | b 548 * MAC_Address_1 = (c << 8) | d 549 * MAC_Address_0 = (e << 8) | f 550 */ 551 552/* Address Filter Registers. Registers 0 through 2 specify bit 553 * fields [47:32] through [15:0], respectively, of the address 554 * filter. The Address Filter 2&1 Mask Register denotes the 8-bit 555 * nibble mask for Address Filter Registers 2 and 1. The Address 556 * Filter 0 Mask Register denotes the 16-bit mask for the Address 557 * Filter Register 0. 558 */ 559 560/* Hash Table Registers. Registers 0 through 15 specify bit fields 561 * [255:240] through [15:0], respectively, of the hash table. 562 */ 563 564/* Statistics Registers. All of these registers are 16-bits and 565 * track occurances of a specific event. GEM can be configured 566 * to interrupt the host cpu when any of these counters overflow. 567 * They should all be explicitly initialized to zero when the interface 568 * is brought up. 569 */ 570 571/* Random Number Seed Register. This 10-bit value is used as the 572 * RNG seed inside GEM for the CSMA/CD backoff algorithm. It is 573 * recommended to program this register to the 10 LSB of the 574 * interfaces MAC address. 575 */ 576 577/* Pause Timer, read-only. This 16-bit timer is used to time the pause 578 * interval as indicated by a received pause flow control frame. 579 * A non-zero value in this timer indicates that the MAC is currently in 580 * the paused state. 581 */ 582 583/* MIF Registers */ 584#define MIF_BBCLK 0x6200UL /* MIF Bit-Bang Clock */ 585#define MIF_BBDATA 0x6204UL /* MIF Bit-Band Data */ 586#define MIF_BBOENAB 0x6208UL /* MIF Bit-Bang Output Enable */ 587#define MIF_FRAME 0x620CUL /* MIF Frame/Output Register */ 588#define MIF_CFG 0x6210UL /* MIF Configuration Register */ 589#define MIF_MASK 0x6214UL /* MIF Mask Register */ 590#define MIF_STATUS 0x6218UL /* MIF Status Register */ 591#define MIF_SMACHINE 0x621CUL /* MIF State Machine Register */ 592 593/* MIF Bit-Bang Clock. This 1-bit register is used to generate the 594 * MDC clock waveform on the MII Management Interface when the MIF is 595 * programmed in the "Bit-Bang" mode. Writing a '1' after a '0' into 596 * this register will create a rising edge on the MDC, while writing 597 * a '0' after a '1' will create a falling edge. For every bit that 598 * is transferred on the management interface, both edges have to be 599 * generated. 600 */ 601 602/* MIF Bit-Bang Data. This 1-bit register is used to generate the 603 * outgoing data (MDO) on the MII Management Interface when the MIF 604 * is programmed in the "Bit-Bang" mode. The daa will be steered to the 605 * appropriate MDIO based on the state of the PHY_Select bit in the MIF 606 * Configuration Register. 607 */ 608 609/* MIF Big-Band Output Enable. THis 1-bit register is used to enable 610 * ('1') or disable ('0') the I-directional driver on the MII when the 611 * MIF is programmed in the "Bit-Bang" mode. The MDIO should be enabled 612 * when data bits are transferred from the MIF to the transceiver, and it 613 * should be disabled when the interface is idle or when data bits are 614 * transferred from the transceiver to the MIF (data portion of a read 615 * instruction). Only one MDIO will be enabled at a given time, depending 616 * on the state of the PHY_Select bit in the MIF Configuration Register. 617 */ 618 619/* MIF Configuration Register. This 15-bit register controls the operation 620 * of the MIF. 621 */ 622#define MIF_CFG_PSELECT 0x00000001 /* Xcvr slct: 0=mdio0 1=mdio1 */ 623#define MIF_CFG_POLL 0x00000002 /* Enable polling mechanism */ 624#define MIF_CFG_BBMODE 0x00000004 /* 1=bit-bang 0=frame mode */ 625#define MIF_CFG_PRADDR 0x000000f8 /* Xcvr poll register address */ 626#define MIF_CFG_MDI0 0x00000100 /* MDIO_0 present or read-bit */ 627#define MIF_CFG_MDI1 0x00000200 /* MDIO_1 present or read-bit */ 628#define MIF_CFG_PPADDR 0x00007c00 /* Xcvr poll PHY address */ 629 630/* MIF Frame/Output Register. This 32-bit register allows the host to 631 * communicate with a transceiver in frame mode (as opposed to big-bang 632 * mode). Writes by the host specify an instrution. After being issued 633 * the host must poll this register for completion. Also, after 634 * completion this register holds the data returned by the transceiver 635 * if applicable. 636 */ 637#define MIF_FRAME_ST 0xc0000000 /* STart of frame */ 638#define MIF_FRAME_OP 0x30000000 /* OPcode */ 639#define MIF_FRAME_PHYAD 0x0f800000 /* PHY ADdress */ 640#define MIF_FRAME_REGAD 0x007c0000 /* REGister ADdress */ 641#define MIF_FRAME_TAMSB 0x00020000 /* Turn Around MSB */ 642#define MIF_FRAME_TALSB 0x00010000 /* Turn Around LSB */ 643#define MIF_FRAME_DATA 0x0000ffff /* Instruction Payload */ 644 645/* MIF Status Register. This register reports status when the MIF is 646 * operating in the poll mode. The poll status field is auto-clearing 647 * on read. 648 */ 649#define MIF_STATUS_DATA 0xffff0000 /* Live image of XCVR reg */ 650#define MIF_STATUS_STAT 0x0000ffff /* Which bits have changed */ 651 652/* MIF Mask Register. This 16-bit register is used when in poll mode 653 * to say which bits of the polled register will cause an interrupt 654 * when changed. 655 */ 656 657/* PCS/Serialink Registers */ 658#define PCS_MIICTRL 0x9000UL /* PCS MII Control Register */ 659#define PCS_MIISTAT 0x9004UL /* PCS MII Status Register */ 660#define PCS_MIIADV 0x9008UL /* PCS MII Advertisement Reg */ 661#define PCS_MIILP 0x900CUL /* PCS MII Link Partner Ability */ 662#define PCS_CFG 0x9010UL /* PCS Configuration Register */ 663#define PCS_SMACHINE 0x9014UL /* PCS State Machine Register */ 664#define PCS_ISTAT 0x9018UL /* PCS Interrupt Status Reg */ 665#define PCS_DMODE 0x9050UL /* Datapath Mode Register */ 666#define PCS_SCTRL 0x9054UL /* Serialink Control Register */ 667#define PCS_SOS 0x9058UL /* Shared Output Select Reg */ 668#define PCS_SSTATE 0x905CUL /* Serialink State Register */ 669 670/* PCD MII Control Register. */ 671#define PCS_MIICTRL_SPD 0x00000040 /* Read as one, writes ignored */ 672#define PCS_MIICTRL_CT 0x00000080 /* Force COL signal active */ 673#define PCS_MIICTRL_DM 0x00000100 /* Duplex mode, forced low */ 674#define PCS_MIICTRL_RAN 0x00000200 /* Restart auto-neg, self clear */ 675#define PCS_MIICTRL_ISO 0x00000400 /* Read as zero, writes ignored */ 676#define PCS_MIICTRL_PD 0x00000800 /* Read as zero, writes ignored */ 677#define PCS_MIICTRL_ANE 0x00001000 /* Auto-neg enable */ 678#define PCS_MIICTRL_SS 0x00002000 /* Read as zero, writes ignored */ 679#define PCS_MIICTRL_WB 0x00004000 /* Wrapback, loopback at 10-bit 680 * input side of Serialink 681 */ 682#define PCS_MIICTRL_RST 0x00008000 /* Resets PCS, self clearing */ 683 684/* PCS MII Status Register. */ 685#define PCS_MIISTAT_EC 0x00000001 /* Ext Capability: Read as zero */ 686#define PCS_MIISTAT_JD 0x00000002 /* Jabber Detect: Read as zero */ 687#define PCS_MIISTAT_LS 0x00000004 /* Link Status: 1=up 0=down */ 688#define PCS_MIISTAT_ANA 0x00000008 /* Auto-neg Ability, always 1 */ 689#define PCS_MIISTAT_RF 0x00000010 /* Remote Fault */ 690#define PCS_MIISTAT_ANC 0x00000020 /* Auto-neg complete */ 691#define PCS_MIISTAT_ES 0x00000100 /* Extended Status, always 1 */ 692 693/* PCS MII Advertisement Register. */ 694#define PCS_MIIADV_FD 0x00000020 /* Advertise Full Duplex */ 695#define PCS_MIIADV_HD 0x00000040 /* Advertise Half Duplex */ 696#define PCS_MIIADV_SP 0x00000080 /* Advertise Symmetric Pause */ 697#define PCS_MIIADV_AP 0x00000100 /* Advertise Asymmetric Pause */ 698#define PCS_MIIADV_RF 0x00003000 /* Remote Fault */ 699#define PCS_MIIADV_ACK 0x00004000 /* Read-only */ 700#define PCS_MIIADV_NP 0x00008000 /* Next-page, forced low */ 701 702/* PCS MII Link Partner Ability Register. This register is equivalent 703 * to the Link Partnet Ability Register of the standard MII register set. 704 * It's layout corresponds to the PCS MII Advertisement Register. 705 */ 706 707/* PCS Configuration Register. */ 708#define PCS_CFG_ENABLE 0x00000001 /* Must be zero while changing 709 * PCS MII advertisement reg. 710 */ 711#define PCS_CFG_SDO 0x00000002 /* Signal detect override */ 712#define PCS_CFG_SDL 0x00000004 /* Signal detect active low */ 713#define PCS_CFG_JS 0x00000018 /* Jitter-study: 714 * 0 = normal operation 715 * 1 = high-frequency test pattern 716 * 2 = low-frequency test pattern 717 * 3 = reserved 718 */ 719#define PCS_CFG_TO 0x00000020 /* 10ms auto-neg timer override */ 720 721/* PCS Interrupt Status Register. This register is self-clearing 722 * when read. 723 */ 724#define PCS_ISTAT_LSC 0x00000004 /* Link Status Change */ 725 726/* Datapath Mode Register. */ 727#define PCS_DMODE_SM 0x00000001 /* 1 = use internal Serialink */ 728#define PCS_DMODE_ESM 0x00000002 /* External SERDES mode */ 729#define PCS_DMODE_MGM 0x00000004 /* MII/GMII mode */ 730#define PCS_DMODE_GMOE 0x00000008 /* GMII Output Enable */ 731 732/* Serialink Control Register. 733 * 734 * NOTE: When in SERDES mode, the loopback bit has inverse logic. 735 */ 736#define PCS_SCTRL_LOOP 0x00000001 /* Loopback enable */ 737#define PCS_SCTRL_ESCD 0x00000002 /* Enable sync char detection */ 738#define PCS_SCTRL_LOCK 0x00000004 /* Lock to reference clock */ 739#define PCS_SCTRL_EMP 0x00000018 /* Output driver emphasis */ 740#define PCS_SCTRL_STEST 0x000001c0 /* Self test patterns */ 741#define PCS_SCTRL_PDWN 0x00000200 /* Software power-down */ 742#define PCS_SCTRL_RXZ 0x00000c00 /* PLL input to Serialink */ 743#define PCS_SCTRL_RXP 0x00003000 /* PLL input to Serialink */ 744#define PCS_SCTRL_TXZ 0x0000c000 /* PLL input to Serialink */ 745#define PCS_SCTRL_TXP 0x00030000 /* PLL input to Serialink */ 746 747/* Shared Output Select Register. For test and debug, allows multiplexing 748 * test outputs into the PROM address pins. Set to zero for normal 749 * operation. 750 */ 751#define PCS_SOS_PADDR 0x00000003 /* PROM Address */ 752 753/* PROM Image Space */ 754#define PROM_START 0x100000UL /* Expansion ROM run time access*/ 755#define PROM_SIZE 0x0fffffUL /* Size of ROM */ 756#define PROM_END 0x200000UL /* End of ROM */ 757 758/* MII definitions missing from mii.h */ 759 760#define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */ 761#define LPA_PAUSE 0x0400 762 763/* More PHY registers (specific to Broadcom models) */ 764 765/* MII BCM5201 MULTIPHY interrupt register */ 766#define MII_BCM5201_INTERRUPT 0x1A 767#define MII_BCM5201_INTERRUPT_INTENABLE 0x4000 768 769#define MII_BCM5201_AUXMODE2 0x1B 770#define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008 771 772#define MII_BCM5201_MULTIPHY 0x1E 773 774/* MII BCM5201 MULTIPHY register bits */ 775#define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002 776#define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008 777 778/* MII BCM5400 1000-BASET Control register */ 779#define MII_BCM5400_GB_CONTROL 0x09 780#define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200 781 782/* MII BCM5400 AUXCONTROL register */ 783#define MII_BCM5400_AUXCONTROL 0x18 784#define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004 785 786/* MII BCM5400 AUXSTATUS register */ 787#define MII_BCM5400_AUXSTATUS 0x19 788#define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700 789#define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8 790 791/* When it can, GEM internally caches 4 aligned TX descriptors 792 * at a time, so that it can use full cacheline DMA reads. 793 * 794 * Note that unlike HME, there is no ownership bit in the descriptor 795 * control word. The same functionality is obtained via the TX-Kick 796 * and TX-Complete registers. As a result, GEM need not write back 797 * updated values to the TX descriptor ring, it only performs reads. 798 * 799 * Since TX descriptors are never modified by GEM, the driver can 800 * use the buffer DMA address as a place to keep track of allocated 801 * DMA mappings for a transmitted packet. 802 */ 803struct gem_txd { 804 u64 control_word; 805 u64 buffer; 806}; 807 808#define TXDCTRL_BUFSZ 0x0000000000007fff /* Buffer Size */ 809#define TXDCTRL_CSTART 0x00000000001f8000 /* CSUM Start Offset */ 810#define TXDCTRL_COFF 0x000000001fe00000 /* CSUM Stuff Offset */ 811#define TXDCTRL_CENAB 0x0000000020000000 /* CSUM Enable */ 812#define TXDCTRL_EOF 0x0000000040000000 /* End of Frame */ 813#define TXDCTRL_SOF 0x0000000080000000 /* Start of Frame */ 814#define TXDCTRL_INTME 0x0000000100000000 /* "Interrupt Me" */ 815#define TXDCTRL_NOCRC 0x0000000200000000 /* No CRC Present */ 816 817/* GEM requires that RX descriptors are provided four at a time, 818 * aligned. Also, the RX ring may not wrap around. This means that 819 * there will be at least 4 unused desciptor entries in the middle 820 * of the RX ring at all times. 821 * 822 * Similar to HME, GEM assumes that it can write garbage bytes before 823 * the beginning of the buffer and right after the end in order to DMA 824 * whole cachelines. 825 * 826 * Unlike for TX, GEM does update the status word in the RX descriptors 827 * when packets arrive. Therefore an ownership bit does exist in the 828 * RX descriptors. It is advisory, GEM clears it but does not check 829 * it in any way. So when buffers are posted to the RX ring (via the 830 * RX Kick register) by the driver it must make sure the buffers are 831 * truly ready and that the ownership bits are set properly. 832 * 833 * Even though GEM modifies the RX descriptors, it guarentees that the 834 * buffer DMA address field will stay the same when it performs these 835 * updates. Therefore it can be used to keep track of DMA mappings 836 * by the host driver just as in the TX descriptor case above. 837 */ 838struct gem_rxd { 839 u64 status_word; 840 u64 buffer; 841}; 842 843#define RXDCTRL_TCPCSUM 0x000000000000ffff /* TCP Pseudo-CSUM */ 844#define RXDCTRL_BUFSZ 0x000000007fff0000 /* Buffer Size */ 845#define RXDCTRL_OWN 0x0000000080000000 /* GEM owns this entry */ 846#define RXDCTRL_HASHVAL 0x0ffff00000000000 /* Hash Value */ 847#define RXDCTRL_HPASS 0x1000000000000000 /* Passed Hash Filter */ 848#define RXDCTRL_ALTMAC 0x2000000000000000 /* Matched ALT MAC */ 849#define RXDCTRL_BAD 0x4000000000000000 /* Frame has bad CRC */ 850 851#define RXDCTRL_FRESH(gp) \ 852 ((((RX_BUF_ALLOC_SIZE(gp) - RX_OFFSET) << 16) & RXDCTRL_BUFSZ) | \ 853 RXDCTRL_OWN) 854 855#define TX_RING_SIZE 128 856#define RX_RING_SIZE 128 857 858#if TX_RING_SIZE == 32 859#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_32 860#elif TX_RING_SIZE == 64 861#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_64 862#elif TX_RING_SIZE == 128 863#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_128 864#elif TX_RING_SIZE == 256 865#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_256 866#elif TX_RING_SIZE == 512 867#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_512 868#elif TX_RING_SIZE == 1024 869#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_1K 870#elif TX_RING_SIZE == 2048 871#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_2K 872#elif TX_RING_SIZE == 4096 873#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_4K 874#elif TX_RING_SIZE == 8192 875#define TXDMA_CFG_BASE TXDMA_CFG_RINGSZ_8K 876#else 877#error TX_RING_SIZE value is illegal... 878#endif 879 880#if RX_RING_SIZE == 32 881#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_32 882#elif RX_RING_SIZE == 64 883#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_64 884#elif RX_RING_SIZE == 128 885#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_128 886#elif RX_RING_SIZE == 256 887#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_256 888#elif RX_RING_SIZE == 512 889#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_512 890#elif RX_RING_SIZE == 1024 891#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_1K 892#elif RX_RING_SIZE == 2048 893#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_2K 894#elif RX_RING_SIZE == 4096 895#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_4K 896#elif RX_RING_SIZE == 8192 897#define RXDMA_CFG_BASE RXDMA_CFG_RINGSZ_8K 898#else 899#error RX_RING_SIZE is illegal... 900#endif 901 902#define NEXT_TX(N) (((N) + 1) & (TX_RING_SIZE - 1)) 903#define NEXT_RX(N) (((N) + 1) & (RX_RING_SIZE - 1)) 904 905#define TX_BUFFS_AVAIL(GP) \ 906 (((GP)->tx_old <= (GP)->tx_new) ? \ 907 (GP)->tx_old + (TX_RING_SIZE - 1) - (GP)->tx_new : \ 908 (GP)->tx_old - (GP)->tx_new - 1) 909 910#define RX_OFFSET 2 911#define RX_BUF_ALLOC_SIZE(gp) ((gp)->dev->mtu + 46 + RX_OFFSET + 64) 912 913#define RX_COPY_THRESHOLD 256 914 915#if TX_RING_SIZE < 128 916#define INIT_BLOCK_TX_RING_SIZE 128 917#else 918#define INIT_BLOCK_TX_RING_SIZE TX_RING_SIZE 919#endif 920 921#if RX_RING_SIZE < 128 922#define INIT_BLOCK_RX_RING_SIZE 128 923#else 924#define INIT_BLOCK_RX_RING_SIZE RX_RING_SIZE 925#endif 926 927struct gem_init_block { 928 struct gem_txd txd[INIT_BLOCK_TX_RING_SIZE]; 929 struct gem_rxd rxd[INIT_BLOCK_RX_RING_SIZE]; 930}; 931 932enum gem_phy_type { 933 phy_mii_mdio0, 934 phy_mii_mdio1, 935 phy_serialink, 936 phy_serdes, 937}; 938 939enum gem_phy_model { 940 phymod_generic, 941 phymod_bcm5201, 942 phymod_bcm5221, 943 phymod_bcm5400, 944 phymod_bcm5401, 945 phymod_bcm5411, 946 phymod_m1011, 947}; 948 949enum link_state { 950 link_down = 0, /* No link, will retry */ 951 link_aneg, /* Autoneg in progress */ 952 link_force_try, /* Try Forced link speed */ 953 link_force_ret, /* Forced mode worked, retrying autoneg */ 954 link_force_ok, /* Stay in forced mode */ 955 link_up /* Link is up */ 956}; 957 958struct gem { 959 spinlock_t lock; 960 unsigned long regs; 961 int rx_new, rx_old; 962 int tx_new, tx_old; 963 964 /* Set when chip is actually in operational state 965 * (ie. not power managed) 966 */ 967 int hw_running; 968 int opened; 969 struct semaphore pm_sem; 970 struct tq_struct pm_task; 971 struct timer_list pm_timer; 972 973 struct gem_init_block *init_block; 974 975 struct sk_buff *rx_skbs[RX_RING_SIZE]; 976 struct sk_buff *tx_skbs[RX_RING_SIZE]; 977 978 u32 msg_enable; 979 980 struct net_device_stats net_stats; 981 982 enum gem_phy_type phy_type; 983 enum gem_phy_model phy_mod; 984 int tx_fifo_sz; 985 int rx_fifo_sz; 986 int rx_pause_off; 987 int rx_pause_on; 988 int mii_phy_addr; 989 int gigabit_capable; 990 991 u32 mac_rx_cfg; 992 u32 swrst_base; 993 994 /* Autoneg & PHY control */ 995 int link_cntl; 996 int link_advertise; 997 int link_fcntl; 998 enum link_state lstate; 999 struct timer_list link_timer; 1000 int timer_ticks; 1001 int wake_on_lan; 1002 struct tq_struct reset_task; 1003 volatile int reset_task_pending; 1004 1005 /* Diagnostic counters and state. */ 1006 u64 pause_entered; 1007 u16 pause_last_time_recvd; 1008 1009 dma_addr_t gblock_dvma; 1010 struct pci_dev *pdev; 1011 struct net_device *dev; 1012#ifdef CONFIG_ALL_PPC 1013 struct device_node *of_node; 1014#endif 1015}; 1016 1017#define ALIGNED_RX_SKB_ADDR(addr) \ 1018 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr)) 1019static __inline__ struct sk_buff *gem_alloc_skb(int size, int gfp_flags) 1020{ 1021 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags); 1022 1023 if (skb) { 1024 int offset = (int) ALIGNED_RX_SKB_ADDR(skb->data); 1025 if (offset) 1026 skb_reserve(skb, offset); 1027 } 1028 1029 return skb; 1030} 1031 1032#endif /* _SUNGEM_H */ 1033