1/****************************************************************************** 2 * 3 * Name: skgeinit.c 4 * Project: GEnesis, PCI Gigabit Ethernet Adapter 5 * Version: $Revision: 1.1.1.1 $ 6 * Date: $Date: 2008/10/15 03:26:44 $ 7 * Purpose: Contains functions to initialize the GE HW 8 * 9 ******************************************************************************/ 10 11/****************************************************************************** 12 * 13 * (C)Copyright 1998-2001 SysKonnect GmbH. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * The information in this file is provided "AS IS" without warranty. 21 * 22 ******************************************************************************/ 23 24 25#include "h/skdrv1st.h" 26#include "h/xmac_ii.h" 27#include "h/skdrv2nd.h" 28 29/* defines ********************************************************************/ 30 31/* defines for SkGeXmitLed() */ 32#define XMIT_LED_INI 0 33#define XMIT_LED_CNT (RX_LED_VAL - RX_LED_INI) 34#define XMIT_LED_CTRL (RX_LED_CTRL- RX_LED_INI) 35#define XMIT_LED_TST (RX_LED_TST - RX_LED_INI) 36 37/* Queue Size units */ 38#define QZ_UNITS 0x7 39 40/* Types of RAM Buffer Queues */ 41#define SK_RX_SRAM_Q 1 /* small receive queue */ 42#define SK_RX_BRAM_Q 2 /* big receive queue */ 43#define SK_TX_RAM_Q 3 /* small or big transmit queue */ 44 45/* typedefs *******************************************************************/ 46/* global variables ***********************************************************/ 47 48/* local variables ************************************************************/ 49 50static const char SysKonnectFileId[] = 51 "@(#)$Id: skgeinit.c,v 1.1.1.1 2008/10/15 03:26:44 james26_jang Exp $ (C) SK "; 52 53struct s_QOffTab { 54 int RxQOff; /* Receive Queue Address Offset */ 55 int XsQOff; /* Sync Tx Queue Address Offset */ 56 int XaQOff; /* Async Tx Queue Address Offset */ 57}; 58static struct s_QOffTab QOffTab[] = { 59 {Q_R1, Q_XS1, Q_XA1}, {Q_R2, Q_XS2, Q_XA2} 60}; 61 62 63/****************************************************************************** 64 * 65 * SkGePollRxD() - Enable/Disable Descriptor Polling of RxD Ring 66 * 67 * Description: 68 * Enable or disable the descriptor polling the receive descriptor 69 * ring (RxD) of port 'port'. 70 * The new configuration is *not* saved over any SkGeStopPort() and 71 * SkGeInitPort() calls. 72 * 73 * Returns: 74 * nothing 75 */ 76void SkGePollRxD( 77SK_AC *pAC, /* adapter context */ 78SK_IOC IoC, /* IO context */ 79int Port, /* Port Index (MAC_1 + n) */ 80SK_BOOL PollRxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ 81{ 82 SK_GEPORT *pPrt; 83 84 pPrt = &pAC->GIni.GP[Port]; 85 86 if (PollRxD) { 87 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_ENA_POL); 88 } 89 else { 90 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_DIS_POL); 91 } 92} /* SkGePollRxD */ 93 94 95/****************************************************************************** 96 * 97 * SkGePollTxD() - Enable/Disable Descriptor Polling of TxD Rings 98 * 99 * Description: 100 * Enable or disable the descriptor polling the transmit descriptor 101 * ring(s) (RxD) of port 'port'. 102 * The new configuration is *not* saved over any SkGeStopPort() and 103 * SkGeInitPort() calls. 104 * 105 * Returns: 106 * nothing 107 */ 108void SkGePollTxD( 109SK_AC *pAC, /* adapter context */ 110SK_IOC IoC, /* IO context */ 111int Port, /* Port Index (MAC_1 + n) */ 112SK_BOOL PollTxD) /* SK_TRUE (enable pol.), SK_FALSE (disable pol.) */ 113{ 114 SK_GEPORT *pPrt; 115 SK_U32 DWord; 116 117 pPrt = &pAC->GIni.GP[Port]; 118 119 if (PollTxD) { 120 DWord = CSR_ENA_POL; 121 } 122 else { 123 DWord = CSR_DIS_POL; 124 } 125 126 if (pPrt->PXSQSize != 0) { 127 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord); 128 } 129 if (pPrt->PXAQSize != 0) { 130 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord); 131 } 132} /* SkGePollTxD */ 133 134 135/****************************************************************************** 136 * 137 * SkGeYellowLED() - Switch the yellow LED on or off. 138 * 139 * Description: 140 * Switch the yellow LED on or off. 141 * 142 * Note: 143 * This function may be called any time after SkGeInit(Level 1). 144 * 145 * Returns: 146 * nothing 147 */ 148void SkGeYellowLED( 149SK_AC *pAC, /* adapter context */ 150SK_IOC IoC, /* IO context */ 151int State) /* yellow LED state, 0 = OFF, 0 != ON */ 152{ 153 if (State == 0) { 154 /* Switch yellow LED OFF */ 155 SK_OUT8(IoC, B0_LED, LED_STAT_OFF); 156 } 157 else { 158 /* Switch yellow LED ON */ 159 SK_OUT8(IoC, B0_LED, LED_STAT_ON); 160 } 161} /* SkGeYellowLED */ 162 163 164/****************************************************************************** 165 * 166 * SkGeXmitLED() - Modify the Operational Mode of a transmission LED. 167 * 168 * Description: 169 * The Rx or Tx LED which is specified by 'Led' will be 170 * enabled, disabled or switched on in test mode. 171 * 172 * Note: 173 * 'Led' must contain the address offset of the LEDs INI register. 174 * 175 * Usage: 176 * SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); 177 * 178 * Returns: 179 * nothing 180 */ 181void SkGeXmitLED( 182SK_AC *pAC, /* adapter context */ 183SK_IOC IoC, /* IO context */ 184int Led, /* offset to the LED Init Value register */ 185int Mode) /* Mode may be SK_LED_DIS, SK_LED_ENA, SK_LED_TST */ 186{ 187 SK_U32 LedIni; 188 189 switch (Mode) { 190 case SK_LED_ENA: 191 LedIni = SK_XMIT_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; 192 SK_OUT32(IoC, Led + XMIT_LED_INI, LedIni); 193 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START); 194 break; 195 case SK_LED_TST: 196 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_ON); 197 SK_OUT32(IoC, Led + XMIT_LED_CNT, 100); 198 SK_OUT8(IoC, Led + XMIT_LED_CTRL, LED_START); 199 break; 200 case SK_LED_DIS: 201 default: 202 /* 203 * Do NOT stop the LED Timer here. The LED might be 204 * in on state. But it needs to go off. 205 */ 206 SK_OUT32(IoC, Led + XMIT_LED_CNT, 0); 207 SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF); 208 break; 209 } 210 211} /* SkGeXmitLED */ 212 213 214/****************************************************************************** 215 * 216 * DoCalcAddr() - Calculates the start and the end address of a queue. 217 * 218 * Description: 219 * This function calculates the start- end the end address 220 * of a queue. Afterwards the 'StartVal' is incremented to the 221 * next start position. 222 * If the port is already initialized the calculated values 223 * will be checked against the configured values and an 224 * error will be returned, if they are not equal. 225 * If the port is not initialized the values will be written to 226 * *StartAdr and *EndAddr. 227 * 228 * Returns: 229 * 0: success 230 * 1: configuration error 231 */ 232static int DoCalcAddr( 233SK_AC *pAC, /* adapter context */ 234SK_GEPORT *pPrt, /* port index */ 235int QuSize, /* size of the queue to configure in kB */ 236SK_U32 *StartVal, /* start value for address calculation */ 237SK_U32 *QuStartAddr, /* start addr to calculate */ 238SK_U32 *QuEndAddr) /* end address to calculate */ 239{ 240 SK_U32 EndVal; 241 SK_U32 NextStart; 242 int Rtv; 243 244 Rtv = 0; 245 if (QuSize == 0) { 246 EndVal = *StartVal; 247 NextStart = EndVal; 248 } 249 else { 250 EndVal = *StartVal + ((SK_U32)QuSize * 1024) - 1; 251 NextStart = EndVal + 1; 252 } 253 254 if (pPrt->PState >= SK_PRT_INIT) { 255 if (*StartVal != *QuStartAddr || EndVal != *QuEndAddr) { 256 Rtv = 1; 257 } 258 } 259 else { 260 *QuStartAddr = *StartVal; 261 *QuEndAddr = EndVal; 262 } 263 264 *StartVal = NextStart; 265 return (Rtv); 266} /* DoCalcAddr */ 267 268 269/****************************************************************************** 270 * 271 * SkGeCheckQSize() - Checks the Adapters Queue Size Configuration 272 * 273 * Description: 274 * This function verifies the Queue Size Configuration specified 275 * in the variabels PRxQSize, PXSQSize, and PXAQSize of all 276 * used ports. 277 * This requirements must be fullfilled to have a valid configuration: 278 * - The size of all queues must not exceed GIRamSize. 279 * - The queue sizes must be specified in units of 8 kB. 280 * - The size of rx queues of available ports must not be 281 * smaller than 16kB. 282 * - The RAM start and end addresses must not be changed 283 * for ports which are already initialized. 284 * Furthermore SkGeCheckQSize() defines the Start and End 285 * Addresses of all ports and stores them into the HWAC port 286 * structure. 287 * 288 * Returns: 289 * 0: Queue Size Configuration valid 290 * 1: Queue Size Configuration invalid 291 */ 292static int SkGeCheckQSize( 293SK_AC *pAC, /* adapter context */ 294int Port) /* port index */ 295{ 296 SK_GEPORT *pPrt; 297 int UsedMem; 298 int i; 299 int Rtv; 300 int Rtv2; 301 SK_U32 StartAddr; 302 303 UsedMem = 0; 304 Rtv = 0; 305 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 306 pPrt = &pAC->GIni.GP[i]; 307 308 if (( pPrt->PRxQSize & QZ_UNITS) || 309 (pPrt->PXSQSize & QZ_UNITS) || 310 (pPrt->PXAQSize & QZ_UNITS)) { 311 312 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); 313 Rtv = 1; 314 goto CheckQSizeEnd; 315 } 316 317 UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize; 318 319 if (i == Port && pPrt->PRxQSize < SK_MIN_RXQ_SIZE) { 320 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG); 321 Rtv = 1; 322 goto CheckQSizeEnd; 323 } 324 } 325 if (UsedMem > pAC->GIni.GIRamSize) { 326 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG); 327 Rtv = 1; 328 goto CheckQSizeEnd; 329 } 330 331 /* Now start address calculation */ 332 StartAddr = pAC->GIni.GIRamOffs; 333 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 334 pPrt = &pAC->GIni.GP[i]; 335 336 /* Calculate/Check values for the receive queue */ 337 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PRxQSize, &StartAddr, 338 &pPrt->PRxQRamStart, &pPrt->PRxQRamEnd); 339 Rtv |= Rtv2; 340 341 /* Calculate/Check values for the synchronous tx queue */ 342 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXSQSize, &StartAddr, 343 &pPrt->PXsQRamStart, &pPrt->PXsQRamEnd); 344 Rtv |= Rtv2; 345 346 /* Calculate/Check values for the asynchronous tx queue */ 347 Rtv2 = DoCalcAddr(pAC, pPrt, pPrt->PXAQSize, &StartAddr, 348 &pPrt->PXaQRamStart, &pPrt->PXaQRamEnd); 349 Rtv |= Rtv2; 350 351 if (Rtv) { 352 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E013, SKERR_HWI_E013MSG); 353 break; 354 } 355 } 356 357CheckQSizeEnd: 358 return (Rtv); 359} /* SkGeCheckQSize */ 360 361 362/****************************************************************************** 363 * 364 * SkGeInitMacArb() - Initialize the MAC Arbiter 365 * 366 * Description: 367 * This function initializes the MAC Arbiter. 368 * It must not be called if there is still an 369 * initilaized or active port. 370 * 371 * Returns: 372 * nothing: 373 */ 374static void SkGeInitMacArb( 375SK_AC *pAC, /* adapter context */ 376SK_IOC IoC) /* IO context */ 377{ 378 /* release local reset */ 379 SK_OUT16(IoC, B3_MA_TO_CTRL, MA_RST_CLR); 380 381 /* configure timeout values */ 382 SK_OUT8(IoC, B3_MA_TOINI_RX1, SK_MAC_TO_53); 383 SK_OUT8(IoC, B3_MA_TOINI_RX2, SK_MAC_TO_53); 384 SK_OUT8(IoC, B3_MA_TOINI_TX1, SK_MAC_TO_53); 385 SK_OUT8(IoC, B3_MA_TOINI_TX2, SK_MAC_TO_53); 386 387 SK_OUT8(IoC, B3_MA_RCINI_RX1, 0); 388 SK_OUT8(IoC, B3_MA_RCINI_RX2, 0); 389 SK_OUT8(IoC, B3_MA_RCINI_TX1, 0); 390 SK_OUT8(IoC, B3_MA_RCINI_TX2, 0); 391 392 /* recovery values are needed for XMAC II Rev. B2 only */ 393 /* Fast Output Enable Mode was intended to use with Rev. B2, but now? */ 394 395 /* 396 * There is not start or enable buttom to push, therefore 397 * the MAC arbiter is configured and enabled now. 398 */ 399} /* SkGeInitMacArb */ 400 401 402/****************************************************************************** 403 * 404 * SkGeInitPktArb() - Initialize the Packet Arbiter 405 * 406 * Description: 407 * This function initializes the Packet Arbiter. 408 * It must not be called if there is still an 409 * initilaized or active port. 410 * 411 * Returns: 412 * nothing: 413 */ 414static void SkGeInitPktArb( 415SK_AC *pAC, /* adapter context */ 416SK_IOC IoC) /* IO context */ 417{ 418 /* release local reset */ 419 SK_OUT16(IoC, B3_PA_CTRL, PA_RST_CLR); 420 421 /* configure timeout values */ 422 SK_OUT16(IoC, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); 423 SK_OUT16(IoC, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); 424 SK_OUT16(IoC, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); 425 SK_OUT16(IoC, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); 426 427 if (pAC->GIni.GIPortUsage != SK_JUMBO_LINK) { 428 if (pAC->GIni.GIMacsFound == 1) { 429 SK_OUT16(IoC, B3_PA_CTRL, PA_ENA_TO_TX1); 430 } 431 else { 432 SK_OUT16(IoC, B3_PA_CTRL,(PA_ENA_TO_TX1 | PA_ENA_TO_TX2)); 433 } 434 } 435} /* SkGeInitPktArb */ 436 437 438/****************************************************************************** 439 * 440 * SkGeInitMacFifo() - Initialize the MAC FIFOs 441 * 442 * Description: 443 * Initialize all MAC FIFOs of the specified port 444 * 445 * Returns: 446 * nothing 447 */ 448static void SkGeInitMacFifo( 449SK_AC *pAC, /* adapter context */ 450SK_IOC IoC, /* IO context */ 451int Port) /* Port Index (MAC_1 + n) */ 452{ 453 /* 454 * For each FIFO: 455 * - release local reset 456 * - use default value for MAC FIFO size 457 * - setup defaults for the control register 458 * - enable the FIFO 459 */ 460 /* Configure RX MAC FIFO */ 461 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR); 462 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF); 463 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD); 464 465 /* Configure TX MAC FIFO */ 466 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR); 467 SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); 468 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD); 469 470 /* Enable frame flushing if jumbo frames used */ 471 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { 472 SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH); 473 } 474} /* SkGeInitMacFifo */ 475 476 477/****************************************************************************** 478 * 479 * SkGeLoadLnkSyncCnt() - Load the Link Sync Counter and starts counting 480 * 481 * Description: 482 * This function starts the Link Sync Counter of the specified 483 * port and enables the generation of an Link Sync IRQ. 484 * The Link Sync Counter may be used to detect an active link, 485 * if autonegotiation is not used. 486 * 487 * Note: 488 * o To ensure receiving the Link Sync Event the LinkSyncCounter 489 * should be initialized BEFORE clearing the XMACs reset! 490 * o Enable IS_LNK_SYNC_M1 and IS_LNK_SYNC_M2 after calling this 491 * function. 492 * 493 * Retruns: 494 * nothing 495 */ 496void SkGeLoadLnkSyncCnt( 497SK_AC *pAC, /* adapter context */ 498SK_IOC IoC, /* IO context */ 499int Port, /* Port Index (MAC_1 + n) */ 500SK_U32 CntVal) /* Counter value */ 501{ 502 SK_U32 OrgIMsk; 503 SK_U32 NewIMsk; 504 SK_U32 ISrc; 505 SK_BOOL IrqPend; 506 507 /* stop counter */ 508 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_STOP); 509 510 IrqPend = SK_FALSE; 511 SK_IN32(IoC, B0_ISRC, &ISrc); 512 SK_IN32(IoC, B0_IMSK, &OrgIMsk); 513 if (Port == MAC_1) { 514 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M1; 515 if (ISrc & IS_LNK_SYNC_M1) { 516 IrqPend = SK_TRUE; 517 } 518 } 519 else { 520 NewIMsk = OrgIMsk & ~IS_LNK_SYNC_M2; 521 if (ISrc & IS_LNK_SYNC_M2) { 522 IrqPend = SK_TRUE; 523 } 524 } 525 if (!IrqPend) { 526 SK_OUT32(IoC, B0_IMSK, NewIMsk); 527 } 528 529 /* load counter */ 530 SK_OUT32(IoC, MR_ADDR(Port, LNK_SYNC_INI), CntVal); 531 532 /* start counter */ 533 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_START); 534 535 if (!IrqPend) { 536 /* clear the unexpected IRQ, and restore the interrupt mask */ 537 SK_OUT8(IoC, MR_ADDR(Port, LNK_SYNC_CTRL), LED_CLR_IRQ); 538 SK_OUT32(IoC, B0_IMSK, OrgIMsk); 539 } 540} /* SkGeLoadLnkSyncCnt*/ 541 542 543/****************************************************************************** 544 * 545 * SkGeCfgSync() - Configure synchronous bandwidth for this port. 546 * 547 * Description: 548 * This function may be used to configure synchronous bandwidth 549 * to the specified port. This may be done any time after 550 * initializing the port. The configuration values are NOT saved 551 * in the HWAC port structure and will be overwritten any 552 * time when stopping and starting the port. 553 * Any values for the synchronous configuration will be ignored 554 * if the size of the synchronous queue is zero! 555 * 556 * The default configuration for the synchronous service is 557 * TXA_ENA_FSYNC. This means if the size of 558 * the synchronous queue is unequal zero but no specific 559 * synchronous bandwidth is configured, the synchronous queue 560 * will always have the 'unlimitted' transmit priority! 561 * 562 * This mode will be restored if the synchronous bandwidth is 563 * deallocated ('IntTime' = 0 and 'LimCount' = 0). 564 * 565 * Returns: 566 * 0: success 567 * 1: paramter configuration error 568 * 2: try to configure quality of service although no 569 * synchronous queue is configured 570 */ 571int SkGeCfgSync( 572SK_AC *pAC, /* adapter context */ 573SK_IOC IoC, /* IO context */ 574int Port, /* Port Index (MAC_1 + n) */ 575SK_U32 IntTime, /* Interval Timer Value in units of 8ns */ 576SK_U32 LimCount, /* Number of bytes to transfer during IntTime */ 577int SyncMode) /* Sync Mode: TXA_ENA_ALLOC | TXA_DIS_ALLOC | 0 */ 578{ 579 int Rtv; 580 581 Rtv = 0; 582 583 /* check the parameters */ 584 if (LimCount > IntTime || 585 (LimCount == 0 && IntTime != 0) || 586 (LimCount !=0 && IntTime == 0)) { 587 588 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); 589 Rtv = 1; 590 goto CfgSyncEnd; 591 } 592 if (pAC->GIni.GP[Port].PXSQSize != 0) { 593 /* calculate register values */ 594 IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100; 595 LimCount = LimCount / 8; 596 if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) { 597 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG); 598 Rtv = 1; 599 goto CfgSyncEnd; 600 } 601 602 /* 603 * - Enable 'Force Sync' to ensure the synchronous queue 604 * has the priority while configuring the new values. 605 * - Also 'disable alloc' to ensure the settings complies 606 * to the SyncMode parameter. 607 * - Disable 'Rate Control' to configure the new values. 608 * - write IntTime and Limcount 609 * - start 'Rate Control' and disable 'Force Sync' 610 * if Interval Timer or Limit Counter not zero. 611 */ 612 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), 613 TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 614 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime); 615 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount); 616 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), 617 (SyncMode & (TXA_ENA_ALLOC|TXA_DIS_ALLOC))); 618 if (IntTime != 0 || LimCount != 0) { 619 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), 620 TXA_DIS_FSYNC|TXA_START_RC); 621 } 622 } 623 else { 624 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG); 625 Rtv = 2; 626 } 627 628CfgSyncEnd: 629 return (Rtv); 630} /* SkGeCfgSync */ 631 632 633/****************************************************************************** 634 * 635 * DoInitRamQueue() - Initilaize the RAM Buffer Address of a single Queue 636 * 637 * Desccription: 638 * If the queue is used, enable and initilaize it. 639 * Make sure the queue is still reset, if it is not used. 640 * 641 * Returns: 642 * nothing 643 */ 644static void DoInitRamQueue( 645SK_AC *pAC, /* adapter context */ 646SK_IOC IoC, /* IO context */ 647int QuIoOffs, /* Queue IO Address Offset */ 648SK_U32 QuStartAddr, /* Queue Start Address */ 649SK_U32 QuEndAddr, /* Queue End Address */ 650int QuType) /* Queue Type (SK_RX_SRAM_Q|SK_RX_BRAM_Q|SK_TX_RAM_Q) */ 651{ 652 SK_U32 RxUpThresVal; 653 SK_U32 RxLoThresVal; 654 655 if (QuStartAddr != QuEndAddr) { 656 /* calculate thresholds, assume we have a big Rx queue */ 657 RxUpThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_ULPP) / 8; 658 RxLoThresVal = (QuEndAddr + 1 - QuStartAddr - SK_RB_LLPP_B)/8; 659 660 /* build HW address format */ 661 QuStartAddr = QuStartAddr / 8; 662 QuEndAddr = QuEndAddr / 8; 663 664 /* release local reset */ 665 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_CLR); 666 667 /* configure addresses */ 668 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_START), QuStartAddr); 669 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_END), QuEndAddr); 670 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_WP), QuStartAddr); 671 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RP), QuStartAddr); 672 673 switch (QuType) { 674 case SK_RX_SRAM_Q: 675 /* configure threshold for small Rx Queue */ 676 RxLoThresVal += (SK_RB_LLPP_B - SK_RB_LLPP_S) / 8; 677 678 /* continue with SK_RX_BRAM_Q */ 679 case SK_RX_BRAM_Q: 680 /* write threshold for Rx Queue */ 681 682 SK_OUT32(IoC, RB_ADDR(QuIoOffs, RB_RX_UTPP), RxUpThresVal); 683 SK_OUT32(IoC, RB_ADDR(QuIoOffs,RB_RX_LTPP), RxLoThresVal); 684 685 /* the high priority threshold not used */ 686 break; 687 case SK_TX_RAM_Q: 688 /* 689 * Do NOT use Store and forward under normal 690 * operation due to performance optimization. 691 * But if Jumbo frames are configured we NEED 692 * the store and forward of the RAM buffer. 693 */ 694 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { 695 /* 696 * enable Store & Forward Mode for the 697 * Tx Side 698 */ 699 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_STFWD); 700 } 701 break; 702 } 703 704 /* set queue operational */ 705 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_ENA_OP_MD); 706 } 707 else { 708 /* ensure the queue is still disabled */ 709 SK_OUT8(IoC, RB_ADDR(QuIoOffs, RB_CTRL), RB_RST_SET); 710 } 711} /* DoInitRamQueue*/ 712 713 714/****************************************************************************** 715 * 716 * SkGeInitRamBufs() - Initialize the RAM Buffer Queues 717 * 718 * Description: 719 * Initialize all RAM Buffer Queues of the specified port 720 * 721 * Returns: 722 * nothing 723 */ 724static void SkGeInitRamBufs( 725SK_AC *pAC, /* adapter context */ 726SK_IOC IoC, /* IO context */ 727int Port) /* Port Index (MAC_1 + n) */ 728{ 729 SK_GEPORT *pPrt; 730 int RxQType; 731 732 pPrt = &pAC->GIni.GP[Port]; 733 734 if (pPrt->PRxQSize == SK_MIN_RXQ_SIZE) { 735 RxQType = SK_RX_SRAM_Q; /* small Rx Queue */ 736 } 737 else { 738 RxQType = SK_RX_BRAM_Q; /* big Rx Queue */ 739 } 740 741 DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart, 742 pPrt->PRxQRamEnd, RxQType); 743 DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart, 744 pPrt->PXsQRamEnd, SK_TX_RAM_Q); 745 DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart, 746 pPrt->PXaQRamEnd, SK_TX_RAM_Q); 747} /* SkGeInitRamBufs */ 748 749 750/****************************************************************************** 751 * 752 * SkGeInitRamIface() - Initialize the RAM Interface 753 * 754 * Description: 755 * This function initializes the Adapbers RAM Interface. 756 * 757 * Note: 758 * This function is used in the diagnostics. 759 * 760 * Returns: 761 * nothing 762 */ 763void SkGeInitRamIface( 764SK_AC *pAC, /* adapter context */ 765SK_IOC IoC) /* IO context */ 766{ 767 /* release local reset */ 768 SK_OUT16(IoC, B3_RI_CTRL, RI_RST_CLR); 769 770 /* configure timeout values */ 771 SK_OUT8(IoC, B3_RI_WTO_R1, SK_RI_TO_53); 772 SK_OUT8(IoC, B3_RI_WTO_XA1, SK_RI_TO_53); 773 SK_OUT8(IoC, B3_RI_WTO_XS1, SK_RI_TO_53); 774 SK_OUT8(IoC, B3_RI_RTO_R1, SK_RI_TO_53); 775 SK_OUT8(IoC, B3_RI_RTO_XA1, SK_RI_TO_53); 776 SK_OUT8(IoC, B3_RI_RTO_XS1, SK_RI_TO_53); 777 SK_OUT8(IoC, B3_RI_WTO_R2, SK_RI_TO_53); 778 SK_OUT8(IoC, B3_RI_WTO_XA2, SK_RI_TO_53); 779 SK_OUT8(IoC, B3_RI_WTO_XS2, SK_RI_TO_53); 780 SK_OUT8(IoC, B3_RI_RTO_R2, SK_RI_TO_53); 781 SK_OUT8(IoC, B3_RI_RTO_XA2, SK_RI_TO_53); 782 SK_OUT8(IoC, B3_RI_RTO_XS2, SK_RI_TO_53); 783} /* SkGeInitRamIface */ 784 785 786/****************************************************************************** 787 * 788 * SkGeInitBmu() - Initialize the BMU state machines 789 * 790 * Description: 791 * Initialize all BMU state machines of the specified port 792 * 793 * Returns: 794 * nothing 795 */ 796static void SkGeInitBmu( 797SK_AC *pAC, /* adapter context */ 798SK_IOC IoC, /* IO context */ 799int Port) /* Port Index (MAC_1 + n) */ 800{ 801 SK_GEPORT *pPrt; 802 803 pPrt = &pAC->GIni.GP[Port]; 804 805 /* Rx Queue: Release all local resets and set the watermark */ 806 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_CLR_RESET); 807 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_F), SK_BMU_RX_WM); 808 809 /* 810 * Tx Queue: Release all local resets if the queue is used! 811 * set watermark 812 */ 813 if (pPrt->PXSQSize != 0) { 814 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET); 815 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), SK_BMU_TX_WM); 816 } 817 if (pPrt->PXAQSize != 0) { 818 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET); 819 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), SK_BMU_TX_WM); 820 } 821 /* 822 * Do NOT enable the descriptor poll timers here, because 823 * the descriptor addresses are not specified yet. 824 */ 825} /* SkGeInitBmu */ 826 827 828/****************************************************************************** 829 * 830 * TestStopBit() - Test the stop bit of the queue 831 * 832 * Description: 833 * Stopping a queue is not as simple as it seems to be. 834 * If descriptor polling is enabled, it may happen 835 * that RX/TX stop is done and SV idle is NOT set. 836 * In this case we have to issue another stop command. 837 * 838 * Retruns: 839 * The queues control status register 840 */ 841static SK_U32 TestStopBit( 842SK_AC *pAC, /* Adapter Context */ 843SK_IOC IoC, /* IO Context */ 844int QuIoOffs) /* Queue IO Address Offset */ 845{ 846 SK_U32 QuCsr; /* CSR contents */ 847 848 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); 849 if ((QuCsr & (CSR_STOP|CSR_SV_IDLE)) == 0) { 850 SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP); 851 SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr); 852 } 853 return (QuCsr); 854} /* TestStopBit*/ 855 856 857void SkGeStopPort( 858SK_AC *pAC, /* adapter context */ 859SK_IOC IoC, /* I/O context */ 860int Port, /* port to stop (MAC_1 + n) */ 861int Dir, /* Direction to Stop (SK_STOP_RX, SK_STOP_TX, SK_STOP_ALL) */ 862int RstMode)/* Reset Mode (SK_SOFT_RST, SK_HARD_RST) */ 863{ 864#ifndef SK_DIAG 865 SK_EVPARA Para; 866#endif /* !SK_DIAG */ 867 SK_GEPORT *pPrt; 868 SK_U32 DWord; 869 SK_U16 Word; 870 SK_U32 XsCsr; 871 SK_U32 XaCsr; 872 int i; 873 SK_BOOL AllPortsDis; 874 SK_U64 ToutStart; 875 int ToutCnt; 876 877 pPrt = &pAC->GIni.GP[Port]; 878 879 if (Dir & SK_STOP_TX) { 880 /* disable the XMACs receiver and transmitter */ 881 XM_IN16(IoC, Port, XM_MMU_CMD, &Word); 882 XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); 883 884 /* dummy read to ensure writing */ 885 XM_IN16(IoC, Port, XM_MMU_CMD, &Word); 886 887 /* stop both transmit queues */ 888 /* 889 * If the BMU is in the reset state CSR_STOP will terminate 890 * immediately. 891 */ 892 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_STOP); 893 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_STOP); 894 895 ToutStart = SkOsGetTime(pAC); 896 ToutCnt = 0; 897 do { 898 /* 899 * Clear packet arbiter timeout to make sure 900 * this loop will terminate. 901 */ 902 if (Port == MAC_1) { 903 Word = PA_CLR_TO_TX1; 904 } 905 else { 906 Word = PA_CLR_TO_TX2; 907 } 908 SK_OUT16(IoC, B3_PA_CTRL, Word); 909 910 /* 911 * If the transfer stucks at the XMAC the STOP command will not 912 * terminate if we don't flush the XMAC's transmit FIFO! 913 */ 914 XM_IN32(IoC, Port, XM_MODE, &DWord); 915 DWord |= XM_MD_FTF; 916 XM_OUT32(IoC, Port, XM_MODE, DWord); 917 918 XsCsr = TestStopBit(pAC, IoC, pPrt->PXsQOff); 919 XaCsr = TestStopBit(pAC, IoC, pPrt->PXaQOff); 920 921 if (SkOsGetTime(pAC) - ToutStart > (SK_TICKS_PER_SEC / 18)) { 922 /* 923 * Timeout of 1/18 second reached. 924 * This needs to be checked at 1/18 sec only. 925 */ 926 ToutCnt++; 927 switch (ToutCnt) { 928 case 1: 929 ToutStart = SkOsGetTime(pAC); 930 if (XsCsr & CSR_STOP) { 931 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_START); 932 } 933 if (XaCsr & CSR_STOP) { 934 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_START); 935 } 936 break; 937 case 2: 938 default: 939 940 /* Fatal Error, Loop aborted */ 941 /* Create an Error Log Entry */ 942 SK_ERR_LOG( 943 pAC, 944 SK_ERRCL_HW, 945 SKERR_HWI_E018, 946 SKERR_HWI_E018MSG); 947#ifndef SK_DIAG 948 Para.Para64 = Port; 949 SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_FAIL, Para); 950#endif /* !SK_DIAG */ 951 return; 952 } 953 } 954 955 /* 956 * Because of the ASIC problem report entry from 21.08.1998 it is 957 * required to wait until CSR_STOP is reset and CSR_SV_IDLE is set. 958 */ 959 } while ((XsCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE || 960 (XaCsr & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE); 961 962 /* reset the XMAC depending on the RstMode */ 963 if (RstMode == SK_SOFT_RST) { 964 SkXmSoftRst(pAC, IoC, Port); 965 } 966 else { 967 SkXmHardRst(pAC, IoC, Port); 968 } 969 970 /* 971 * Stop Interval Timer and Limit Counter of Tx Arbiter, 972 * also disable Force Sync bit and Enable Alloc bit. 973 */ 974 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), 975 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 976 SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0x00000000L); 977 SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0x00000000L); 978 979 /* 980 * perform a local reset of the port's tx path 981 * - reset the PCI FIFO of the async tx queue 982 * - reset the PCI FIFO of the sync tx queue 983 * - reset the RAM Buffer async tx queue 984 * - reset the RAM Butter sync tx queue 985 * - reset the MAC Tx FIFO 986 */ 987 SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_SET_RESET); 988 SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_SET_RESET); 989 SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET); 990 SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET); 991 /* Note: MFF_RST_SET does NOT reset the XMAC! */ 992 SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_SET); 993 994 /* switch Link and Tx LED off, stop the LED counters */ 995 /* Link LED is switched off by the RLMT and the Diag itself */ 996 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_DIS); 997 } 998 999 if (Dir & SK_STOP_RX) { 1000 /* 1001 * The RX Stop Command will not terminate if no buffers 1002 * are queued in the RxD ring. But it will always reach 1003 * the Idle state. Therefore we can use this feature to 1004 * stop the transfer of received packets. 1005 */ 1006 /* stop the port's receive queue */ 1007 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP); 1008 i = 100; 1009 do { 1010 /* 1011 * Clear packet arbiter timeout to make sure 1012 * this loop will terminate 1013 */ 1014 if (Port == MAC_1) { 1015 Word = PA_CLR_TO_RX1; 1016 } 1017 else { 1018 Word = PA_CLR_TO_RX2; 1019 } 1020 SK_OUT16(IoC, B3_PA_CTRL, Word); 1021 1022 DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff); 1023 if (i != 0) { 1024 i--; 1025 } 1026 1027 /* finish if CSR_STOP is done or CSR_SV_IDLE is true and i==0 */ 1028 /* 1029 * because of the ASIC problem report entry from 21.08.98 1030 * it is required to wait until CSR_STOP is reset and 1031 * CSR_SV_IDLE is set. 1032 */ 1033 } while ((DWord & (CSR_STOP | CSR_SV_IDLE)) != CSR_SV_IDLE && 1034 ((DWord & CSR_SV_IDLE) == 0 || i != 0)); 1035 1036 /* The path data transfer activity is fully stopped now. */ 1037 1038 /* 1039 * perform a local reset of the port's rx path 1040 * - reset the PCI FIFO of the rx queue 1041 * - reset the RAM Buffer receive queue 1042 * - reset the MAC Rx FIFO 1043 */ 1044 SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_SET_RESET); 1045 SK_OUT8(IoC, RB_ADDR(pPrt->PRxQOff, RB_CTRL), RB_RST_SET); 1046 SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET); 1047 1048 /* switch Rx LED off, stop the LED counter */ 1049 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_DIS); 1050 1051 } 1052 1053 /* 1054 * If all ports are stopped reset the RAM Interface. 1055 */ 1056 for (i = 0, AllPortsDis = SK_TRUE; i < pAC->GIni.GIMacsFound; i++) { 1057 if (pAC->GIni.GP[i].PState != SK_PRT_RESET && 1058 pAC->GIni.GP[i].PState != SK_PRT_STOP) { 1059 1060 AllPortsDis = SK_FALSE; 1061 break; 1062 } 1063 } 1064 if (AllPortsDis) { 1065 pAC->GIni.GIAnyPortAct = SK_FALSE; 1066 } 1067} /* SkGeStopPort */ 1068 1069 1070/****************************************************************************** 1071 * 1072 * SkGeInit0() - Level 0 Initialization 1073 * 1074 * Description: 1075 * - Initialize the BMU address offsets 1076 * 1077 * Returns: 1078 * nothing 1079 */ 1080static void SkGeInit0( 1081SK_AC *pAC, /* adapter context */ 1082SK_IOC IoC) /* IO context */ 1083{ 1084 int i; 1085 SK_GEPORT *pPrt; 1086 1087 for (i = 0; i < SK_MAX_MACS; i++) { 1088 pPrt = &pAC->GIni.GP[i]; 1089 pPrt->PState = SK_PRT_RESET; 1090 pPrt->PRxQOff = QOffTab[i].RxQOff; 1091 pPrt->PXsQOff = QOffTab[i].XsQOff; 1092 pPrt->PXaQOff = QOffTab[i].XaQOff; 1093 pPrt->PCheckPar = SK_FALSE; 1094 pPrt->PRxCmd = XM_RX_STRIP_FCS | XM_RX_LENERR_OK; 1095 pPrt->PIsave = 0; 1096 pPrt->PPrevShorts = 0; 1097 pPrt->PLinkResCt = 0; 1098 pPrt->PAutoNegTOCt = 0; 1099 pPrt->PPrevRx = 0; 1100 pPrt->PPrevFcs = 0; 1101 pPrt->PRxLim = SK_DEF_RX_WA_LIM; 1102 pPrt->PLinkMode = SK_LMODE_AUTOFULL; 1103 pPrt->PLinkModeConf = SK_LMODE_AUTOSENSE; 1104 pPrt->PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM; 1105 pPrt->PLinkBroken = SK_TRUE; /* See WA code */ 1106 pPrt->PLinkCap = (SK_LMODE_CAP_HALF | SK_LMODE_CAP_FULL | 1107 SK_LMODE_CAP_AUTOHALF | SK_LMODE_CAP_AUTOFULL); 1108 pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN; 1109 pPrt->PFlowCtrlCap = SK_FLOW_MODE_SYM_OR_REM; 1110 pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE; 1111 pPrt->PMSCap = (SK_MS_CAP_AUTO | SK_MS_CAP_MASTER | 1112 SK_MS_CAP_SLAVE); 1113 pPrt->PMSMode = SK_MS_MODE_AUTO; 1114 pPrt->PMSStatus = SK_MS_STAT_UNSET; 1115 pPrt->PAutoNegFail = SK_FALSE; 1116 pPrt->PLipaAutoNeg = SK_LIPA_UNKNOWN; 1117 pPrt->PHWLinkUp = SK_FALSE; 1118 } 1119 1120 pAC->GIni.GIPortUsage = SK_RED_LINK; 1121 pAC->GIni.GIAnyPortAct = SK_FALSE; 1122} /* SkGeInit0*/ 1123 1124#ifdef SK_PCI_RESET 1125 1126/****************************************************************************** 1127 * 1128 * SkGePciReset() - Reset PCI interface 1129 * 1130 * Description: 1131 * o Read PCI configuration. 1132 * o Change power state to 3. 1133 * o Change power state to 0. 1134 * o Restore PCI configuration. 1135 * 1136 * Returns: 1137 * 0: Success. 1138 * 1: Power state could not be changed to 3. 1139 */ 1140static int SkGePciReset( 1141SK_AC *pAC, /* adapter context */ 1142SK_IOC IoC) /* IO context */ 1143{ 1144 int i; 1145 SK_U16 PmCtlSts; 1146 SK_U32 Bp1; 1147 SK_U32 Bp2; 1148 SK_U16 PciCmd; 1149 SK_U8 Cls; 1150 SK_U8 Lat; 1151 SK_U8 ConfigSpace[PCI_CFG_SIZE]; 1152 1153 /* 1154 * Note: Switching to D3 state is like a software reset. 1155 * Switching from D3 to D0 is a hardware reset. 1156 * We have to save and restore the configuration space. 1157 */ 1158 for (i = 0; i < PCI_CFG_SIZE; i++) { 1159 SkPciReadCfgDWord(pAC, i*4, &ConfigSpace[i]); 1160 } 1161 1162 /* We know the RAM Interface Arbiter is enabled. */ 1163 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3); 1164 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts); 1165 if ((PmCtlSts & PCI_PM_STATE) != PCI_PM_STATE_D3) { 1166 return (1); 1167 } 1168 1169 /* 1170 * Return to D0 state. 1171 */ 1172 SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D0); 1173 1174 /* Check for D0 state. */ 1175 SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts); 1176 if ((PmCtlSts & PCI_PM_STATE) != PCI_PM_STATE_D0) { 1177 return (1); 1178 } 1179 1180 /* 1181 * Check PCI Config Registers. 1182 */ 1183 SkPciReadCfgWord(pAC, PCI_COMMAND, &PciCmd); 1184 SkPciReadCfgByte(pAC, PCI_CACHE_LSZ, &Cls); 1185 SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1); 1186 SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2); 1187 SkPciReadCfgByte(pAC, PCI_LAT_TIM, &lat); 1188 if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 || 1189 Lat != 0 ) { 1190 return (0); 1191 } 1192 1193 /* 1194 * Restore Config Space. 1195 */ 1196 for (i = 0; i < PCI_CFG_SIZE; i++) { 1197 SkPciWriteCfgDWord(pAC, i*4, ConfigSpace[i]); 1198 } 1199 1200 return (0); 1201} /* SkGePciReset */ 1202 1203#endif /* SK_PCI_RESET */ 1204 1205/****************************************************************************** 1206 * 1207 * SkGeInit1() - Level 1 Initialization 1208 * 1209 * Description: 1210 * o Do a software reset. 1211 * o Clear all reset bits. 1212 * o Verify that the detected hardware is present. 1213 * Return an error if not. 1214 * o Get the hardware configuration 1215 * + Read the number of MACs/Ports. 1216 * + Read the RAM size. 1217 * + Read the PCI Revision ID. 1218 * + Find out the adapters host clock speed 1219 * + Read and check the PHY type 1220 * 1221 * Returns: 1222 * 0: success 1223 * 5: Unexpected PHY type detected 1224 */ 1225static int SkGeInit1( 1226SK_AC *pAC, /* adapter context */ 1227SK_IOC IoC) /* IO context */ 1228{ 1229 SK_U8 Byte; 1230 SK_U16 Word; 1231 int RetVal; 1232 int i; 1233 1234 RetVal = 0; 1235 1236#ifdef SK_PCI_RESET 1237 (void)SkGePciReset(pAC, IoC); 1238#endif /* SK_PCI_RESET */ 1239 1240 /* Do the reset */ 1241 SK_OUT8(IoC, B0_CTST, CS_RST_SET); 1242 1243 /* Release the reset */ 1244 SK_OUT8(IoC, B0_CTST, CS_RST_CLR); 1245 1246 /* Reset all error bits in the PCI STATUS register */ 1247 /* 1248 * Note: Cfg cycles cannot be used, because they are not 1249 * available on some platforms after 'boot time'. 1250 */ 1251 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1252 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); 1253 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); 1254 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1255 1256 /* Release Master_Reset */ 1257 SK_OUT8(IoC, B0_CTST, CS_MRST_CLR); 1258 1259 /* Read number of MACs */ 1260 SK_IN8(IoC, B2_MAC_CFG, &Byte); 1261 if (Byte & CFG_SNG_MAC) { 1262 pAC->GIni.GIMacsFound = 1; 1263 } 1264 else { 1265 pAC->GIni.GIMacsFound = 2; 1266 } 1267 SK_IN8(IoC, PCI_C(PCI_REV_ID), &Byte); 1268 pAC->GIni.GIPciHwRev = (int) Byte; 1269 1270 /* Read the adapters RAM size */ 1271 SK_IN8(IoC, B2_E_0, &Byte); 1272 if (Byte == 3) { 1273 pAC->GIni.GIRamSize = (int)(Byte-1) * 512; 1274 pAC->GIni.GIRamOffs = (SK_U32)512 * 1024; 1275 } 1276 else { 1277 pAC->GIni.GIRamSize = (int)Byte * 512; 1278 pAC->GIni.GIRamOffs = 0; 1279 } 1280 1281 /* All known GE Adapters works with 53.125 MHz host clock */ 1282 pAC->GIni.GIHstClkFact = SK_FACT_53; 1283 pAC->GIni.GIPollTimerVal = 1284 SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100; 1285 1286 /* Read the PHY type */ 1287 SK_IN8(IoC, B2_E_1, &Byte); 1288 Byte &= 0x0f; /* the PHY type is stored in the lower nibble */ 1289 for (i=0; i<pAC->GIni.GIMacsFound; i++) { 1290 pAC->GIni.GP[i].PhyType = Byte; 1291 switch (Byte) { 1292 case SK_PHY_XMAC: 1293 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_XMAC; 1294 break; 1295 case SK_PHY_BCOM: 1296 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_BCOM; 1297 break; 1298 case SK_PHY_LONE: 1299 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_LONE; 1300 break; 1301 case SK_PHY_NAT: 1302 pAC->GIni.GP[i].PhyAddr = PHY_ADDR_NAT; 1303 break; 1304 default: 1305 /* ERROR: unexpected PHY typ detected */ 1306 RetVal = 5; 1307 break; 1308 } 1309 } 1310 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, 1311 ("PHY type: %d PHY addr: %x\n", pAC->GIni.GP[i].PhyType, 1312 pAC->GIni.GP[i].PhyAddr)); 1313 1314 return (RetVal); 1315} /* SkGeInit1*/ 1316 1317 1318/****************************************************************************** 1319 * 1320 * SkGeInit2() - Level 2 Initialization 1321 * 1322 * Description: 1323 * - start the Blink Source Counter 1324 * - start the Descriptor Poll Timer 1325 * - configure the MAC-Arbiter 1326 * - configure the Packet-Arbiter 1327 * - enable the Tx Arbiters 1328 * - enable the RAM Interface Arbiter 1329 * 1330 * Returns: 1331 * nothing 1332 */ 1333static void SkGeInit2( 1334SK_AC *pAC, /* adapter context */ 1335SK_IOC IoC) /* IO context */ 1336{ 1337 SK_GEPORT *pPrt; 1338 SK_U32 DWord; 1339 int i; 1340 1341 /* start the Blink Source Counter */ 1342 DWord = SK_BLK_DUR * (SK_U32)pAC->GIni.GIHstClkFact / 100; 1343 SK_OUT32(IoC, B2_BSC_INI, DWord); 1344 SK_OUT8(IoC, B2_BSC_CTRL, BSC_START); 1345 1346 /* start the Descriptor Poll Timer */ 1347 if (pAC->GIni.GIPollTimerVal != 0) { 1348 if (pAC->GIni.GIPollTimerVal > SK_DPOLL_MAX) { 1349 pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; 1350 1351 /* Create an Error Log Entry */ 1352 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E017, SKERR_HWI_E017MSG); 1353 } 1354 SK_OUT32(IoC, B28_DPT_INI, pAC->GIni.GIPollTimerVal); 1355 SK_OUT8(IoC, B28_DPT_CTRL, DPT_START); 1356 } 1357 1358 /* 1359 * Configure 1360 * - the MAC-Arbiter and 1361 * - the Paket Arbiter 1362 * 1363 * The MAC and the packet arbiter will be started once 1364 * and never be stopped. 1365 */ 1366 SkGeInitMacArb(pAC, IoC); 1367 SkGeInitPktArb(pAC, IoC); 1368 1369 /* enable the Tx Arbiters */ 1370 SK_OUT8(IoC, MR_ADDR(MAC_1, TXA_CTRL), TXA_ENA_ARB); 1371 if (pAC->GIni.GIMacsFound > 1) { 1372 SK_OUT8(IoC, MR_ADDR(MAC_2, TXA_CTRL), TXA_ENA_ARB); 1373 } 1374 1375 /* enable the RAM Interface Arbiter */ 1376 SkGeInitRamIface(pAC, IoC); 1377 1378 for (i = 0; i < SK_MAX_MACS; i++) { 1379 pPrt = &pAC->GIni.GP[i]; 1380 if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) { 1381 pPrt->PRxCmd |= XM_RX_BIG_PK_OK; 1382 } 1383 1384 if (pPrt->PLinkModeConf == SK_LMODE_HALF) { 1385 /* 1386 * If in manual half duplex mode 1387 * the other side might be in full duplex mode 1388 * so ignore if a carrier extension is not seen on 1389 * frames received 1390 */ 1391 pPrt->PRxCmd |= XM_RX_DIS_CEXT; 1392 } 1393 1394 } 1395} /* SkGeInit2 */ 1396 1397/****************************************************************************** 1398 * 1399 * SkGeInit() - Initialize the GE Adapter with the specified level. 1400 * 1401 * Description: 1402 * Level 0: Initialize the Module structures. 1403 * Level 1: Generic Hardware Initialization. The 1404 * IOP/MemBase pointer has to be set before 1405 * calling this level. 1406 * 1407 * o Do a software reset. 1408 * o Clear all reset bits. 1409 * o Verify that the detected hardware is present. 1410 * Return an error if not. 1411 * o Get the hardware configuration 1412 * + Set GIMacsFound with the number of MACs. 1413 * + Store the RAM size in GIRamSize. 1414 * + Save the PCI Revision ID in GIPciHwRev. 1415 * o return an error 1416 * if Number of MACs > SK_MAX_MACS 1417 * 1418 * After returning from Level 0 the adapter 1419 * may be accessed with IO operations. 1420 * 1421 * Level 2: start the Blink Source Counter 1422 * 1423 * Returns: 1424 * 0: success 1425 * 1: Number of MACs exceeds SK_MAX_MACS ( after level 1) 1426 * 2: Adapter not present or not accessable 1427 * 3: Illegal initialization level 1428 * 4: Initialization Level 1 Call missing 1429 * 5: Unexpected PHY type detected 1430 */ 1431int SkGeInit( 1432SK_AC *pAC, /* adapter context */ 1433SK_IOC IoC, /* IO context */ 1434int Level) /* initialization level */ 1435{ 1436 int RetVal; /* return value */ 1437 SK_U32 DWord; 1438 1439 RetVal = 0; 1440 SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT, 1441 ("SkGeInit(Level %d)\n", Level)); 1442 1443 switch (Level) { 1444 case SK_INIT_DATA: 1445 /* Initialization Level 0 */ 1446 SkGeInit0(pAC, IoC); 1447 pAC->GIni.GILevel = SK_INIT_DATA; 1448 break; 1449 case SK_INIT_IO: 1450 /* Initialization Level 1 */ 1451 RetVal = SkGeInit1(pAC, IoC); 1452 1453 /* Check if the adapter seems to be accessable */ 1454 SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L); 1455 SK_IN32(IoC, B2_IRQM_INI, &DWord); 1456 SK_OUT32(IoC, B2_IRQM_INI, 0x00000000L); 1457 if (DWord != 0x11335577L) { 1458 RetVal = 2; 1459 break; 1460 } 1461 1462 /* Check if the number of GIMacsFound matches SK_MAX_MACS */ 1463 if (pAC->GIni.GIMacsFound > SK_MAX_MACS) { 1464 RetVal = 1; 1465 break; 1466 } 1467 1468 /* Level 1 successfully passed */ 1469 pAC->GIni.GILevel = SK_INIT_IO; 1470 break; 1471 case SK_INIT_RUN: 1472 /* Initialization Level 2 */ 1473 if (pAC->GIni.GILevel != SK_INIT_IO) { 1474#ifndef SK_DIAG 1475 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E002, SKERR_HWI_E002MSG); 1476#endif 1477 RetVal = 4; 1478 break; 1479 } 1480 SkGeInit2(pAC, IoC); 1481 1482 /* Level 2 successfully passed */ 1483 pAC->GIni.GILevel = SK_INIT_RUN; 1484 break; 1485 default: 1486 /* Create an Error Log Entry */ 1487 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG); 1488 RetVal = 3; 1489 break; 1490 } 1491 1492 return (RetVal); 1493} /* SkGeInit*/ 1494 1495 1496/****************************************************************************** 1497 * 1498 * SkGeDeInit() - Deinitialize the adapter. 1499 * 1500 * Description: 1501 * All ports of the adapter will be stopped if not already done. 1502 * Do a software reset and switch off all LEDs. 1503 * 1504 * Returns: 1505 * nothing 1506 */ 1507void SkGeDeInit( 1508SK_AC *pAC, /* adapter context */ 1509SK_IOC IoC) /* IO context */ 1510{ 1511 int i; 1512 SK_U16 Word; 1513 1514 /* Ensure I2C is ready. */ 1515 SkI2cWaitIrq(pAC, IoC); 1516 1517 /* Stop all current transfer activity */ 1518 for (i = 0; i < pAC->GIni.GIMacsFound; i++) { 1519 if (pAC->GIni.GP[i].PState != SK_PRT_STOP && 1520 pAC->GIni.GP[i].PState != SK_PRT_RESET) { 1521 1522 SkGeStopPort(pAC, IoC, i, SK_STOP_ALL, SK_HARD_RST); 1523 } 1524 } 1525 1526 /* Reset all bits in the PCI STATUS register */ 1527 /* 1528 * Note: Cfg cycles cannot be used, because they are not 1529 * available on some platforms after 'boot time'. 1530 */ 1531 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1532 SK_IN16(IoC, PCI_C(PCI_STATUS), &Word); 1533 SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS); 1534 SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1535 1536 /* Do the reset, all LEDs are switched off now */ 1537 SK_OUT8(IoC, B0_CTST, CS_RST_SET); 1538} /* SkGeDeInit*/ 1539 1540 1541/****************************************************************************** 1542 * 1543 * SkGeInitPort() Initialize the specified prot. 1544 * 1545 * Description: 1546 * PRxQSize, PXSQSize, and PXAQSize has to be 1547 * configured for the specified port before calling this 1548 * function. The descriptor rings has to be initialized, too. 1549 * 1550 * o (Re)configure queues of the specified port. 1551 * o configure the XMAC of the specified port. 1552 * o put ASIC and XMAC(s) in operational mode. 1553 * o initialize Rx/Tx and Sync LED 1554 * o initialize RAM Buffers and MAC FIFOs 1555 * 1556 * The port is ready to connect when returning. 1557 * 1558 * Note: 1559 * The XMACs Rx and Tx state machine is still disabled when 1560 * returning. 1561 * 1562 * Returns: 1563 * 0: success 1564 * 1: Queue size initialization error. The configured values 1565 * for PRxQSize, PXSQSize, or PXAQSize are invalid for one 1566 * or more queues. The specified port was NOT initialized. 1567 * An error log entry was generated. 1568 * 2: The port has to be stopped before it can be initialized again. 1569 */ 1570int SkGeInitPort( 1571SK_AC *pAC, /* adapter context */ 1572SK_IOC IoC, /* IO context */ 1573int Port) /* Port to configure */ 1574{ 1575 SK_GEPORT *pPrt; 1576 1577 pPrt = &pAC->GIni.GP[Port]; 1578 1579 if (SkGeCheckQSize(pAC, Port) != 0) { 1580 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG); 1581 return (1); 1582 } 1583 if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) { 1584 SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG); 1585 return (2); 1586 } 1587 1588 /* Configuration ok, initialize the Port now */ 1589 1590 /* Initialize Rx, Tx and Link LED */ 1591 /* 1592 * If 1000BT Phy needs LED initialization than swap 1593 * LED and XMAC initialization order 1594 */ 1595 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA); 1596 SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA); 1597 /* The Link LED is initialized by RLMT or Diagnostics itself */ 1598 1599 /* Do NOT initialize the Link Sync Counter */ 1600 1601 /* 1602 * Configure 1603 * - XMAC 1604 * - MAC FIFOs 1605 * - RAM Buffers 1606 * - enable Force Sync bit if synchronous queue available 1607 * - BMUs 1608 */ 1609 SkXmInitMac(pAC, IoC, Port); 1610 SkGeInitMacFifo(pAC, IoC, Port); 1611 SkGeInitRamBufs(pAC, IoC, Port); 1612 if (pPrt->PXSQSize != 0) { 1613 SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC); 1614 } 1615 SkGeInitBmu(pAC, IoC, Port); 1616 1617 /* Mark port as initialized. */ 1618 pPrt->PState = SK_PRT_INIT; 1619 pAC->GIni.GIAnyPortAct = SK_TRUE; 1620 1621 return (0); 1622} /* SkGeInitPort */ 1623