1#define _VERSION "0.20" 2/* ns83820.c by Benjamin LaHaise with contributions. 3 * 4 * Questions/comments/discussion to linux-ns83820@kvack.org. 5 * 6 * $Revision: 1.1.1.1 $ 7 * 8 * Copyright 2001 Benjamin LaHaise. 9 * Copyright 2001, 2002 Red Hat. 10 * 11 * Mmmm, chocolate vanilla mocha... 12 * 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 27 * 28 * 29 * ChangeLog 30 * ========= 31 * 20010414 0.1 - created 32 * 20010622 0.2 - basic rx and tx. 33 * 20010711 0.3 - added duplex and link state detection support. 34 * 20010713 0.4 - zero copy, no hangs. 35 * 0.5 - 64 bit dma support (davem will hate me for this) 36 * - disable jumbo frames to avoid tx hangs 37 * - work around tx deadlocks on my 1.02 card via 38 * fiddling with TXCFG 39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64 40 * 20010816 0.7 - misc cleanups 41 * 20010826 0.8 - fix critical zero copy bugs 42 * 0.9 - internal experiment 43 * 20010827 0.10 - fix ia64 unaligned access. 44 * 20010906 0.11 - accept all packets with checksum errors as 45 * otherwise fragments get lost 46 * - fix >> 32 bugs 47 * 0.12 - add statistics counters 48 * - add allmulti/promisc support 49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups 50 * 20011204 0.13a - optical transceiver support added 51 * by Michael Clark <michael@metaparadigm.com> 52 * 20011205 0.13b - call register_netdev earlier in initialization 53 * suppress duplicate link status messages 54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik 55 * 20011204 0.15 get ppc (big endian) working 56 * 20011218 0.16 various cleanups 57 * 20020310 0.17 speedups 58 * 20020610 0.18 - actually use the pci dma api for highmem 59 * - remove pci latency register fiddling 60 * 0.19 - better bist support 61 * - add ihr and reset_phy parameters 62 * - gmii bus probing 63 * - fix missed txok introduced during performance 64 * tuning 65 * 0.20 - fix stupid RFEN thinko. i am such a smurf. 66 * 67 * Driver Overview 68 * =============== 69 * 70 * This driver was originally written for the National Semiconductor 71 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully 72 * this code will turn out to be a) clean, b) correct, and c) fast. 73 * With that in mind, I'm aiming to split the code up as much as 74 * reasonably possible. At present there are X major sections that 75 * break down into a) packet receive, b) packet transmit, c) link 76 * management, d) initialization and configuration. Where possible, 77 * these code paths are designed to run in parallel. 78 * 79 * This driver has been tested and found to work with the following 80 * cards (in no particular order): 81 * 82 * Cameo SOHO-GA2000T SOHO-GA2500T 83 * D-Link DGE-500T 84 * PureData PDP8023Z-TG 85 * SMC SMC9452TX SMC9462TX 86 * Netgear GA621 87 * 88 * Special thanks to SMC for providing hardware to test this driver on. 89 * 90 * Reports of success or failure would be greatly appreciated. 91 */ 92//#define dprintk printk 93#define dprintk(x...) do { } while (0) 94 95#include <linux/module.h> 96#include <linux/types.h> 97#include <linux/pci.h> 98#include <linux/netdevice.h> 99#include <linux/etherdevice.h> 100#include <linux/delay.h> 101#include <linux/smp_lock.h> 102#include <linux/tqueue.h> 103#include <linux/init.h> 104#include <linux/ip.h> /* for iph */ 105#include <linux/in.h> /* for IPPROTO_... */ 106#include <linux/eeprom.h> 107#include <linux/compiler.h> 108#include <linux/prefetch.h> 109#include <linux/ethtool.h> 110#include <linux/timer.h> 111 112#include <asm/io.h> 113#include <asm/uaccess.h> 114 115/* Global parameters. See MODULE_PARM near the bottom. */ 116static int ihr = 2; 117static int reset_phy = 0; 118static int lnksts = 0; /* CFG_LNKSTS bit polarity */ 119 120/* Dprintk is used for more interesting debug events */ 121#undef Dprintk 122#define Dprintk dprintk 123 124#if defined(CONFIG_HIGHMEM64G) || defined(__ia64__) 125#define USE_64BIT_ADDR "+" 126#endif 127 128#if defined(USE_64BIT_ADDR) 129#define VERSION _VERSION USE_64BIT_ADDR 130#define TRY_DAC 1 131#else 132#define VERSION _VERSION 133#define TRY_DAC 0 134#endif 135 136/* tunables */ 137#define RX_BUF_SIZE 1500 /* 8192 */ 138 139/* Must not exceed ~65000. */ 140#define NR_RX_DESC 64 141#define NR_TX_DESC 128 142 143/* not tunable */ 144#define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */ 145 146#define MIN_TX_DESC_FREE 8 147 148/* register defines */ 149#define CFGCS 0x04 150 151#define CR_TXE 0x00000001 152#define CR_TXD 0x00000002 153/* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE 154 * The Receive engine skips one descriptor and moves 155 * onto the next one!! */ 156#define CR_RXE 0x00000004 157#define CR_RXD 0x00000008 158#define CR_TXR 0x00000010 159#define CR_RXR 0x00000020 160#define CR_SWI 0x00000080 161#define CR_RST 0x00000100 162 163#define PTSCR_EEBIST_FAIL 0x00000001 164#define PTSCR_EEBIST_EN 0x00000002 165#define PTSCR_EELOAD_EN 0x00000004 166#define PTSCR_RBIST_FAIL 0x000001b8 167#define PTSCR_RBIST_DONE 0x00000200 168#define PTSCR_RBIST_EN 0x00000400 169#define PTSCR_RBIST_RST 0x00002000 170 171#define MEAR_EEDI 0x00000001 172#define MEAR_EEDO 0x00000002 173#define MEAR_EECLK 0x00000004 174#define MEAR_EESEL 0x00000008 175#define MEAR_MDIO 0x00000010 176#define MEAR_MDDIR 0x00000020 177#define MEAR_MDC 0x00000040 178 179#define ISR_TXDESC3 0x40000000 180#define ISR_TXDESC2 0x20000000 181#define ISR_TXDESC1 0x10000000 182#define ISR_TXDESC0 0x08000000 183#define ISR_RXDESC3 0x04000000 184#define ISR_RXDESC2 0x02000000 185#define ISR_RXDESC1 0x01000000 186#define ISR_RXDESC0 0x00800000 187#define ISR_TXRCMP 0x00400000 188#define ISR_RXRCMP 0x00200000 189#define ISR_DPERR 0x00100000 190#define ISR_SSERR 0x00080000 191#define ISR_RMABT 0x00040000 192#define ISR_RTABT 0x00020000 193#define ISR_RXSOVR 0x00010000 194#define ISR_HIBINT 0x00008000 195#define ISR_PHY 0x00004000 196#define ISR_PME 0x00002000 197#define ISR_SWI 0x00001000 198#define ISR_MIB 0x00000800 199#define ISR_TXURN 0x00000400 200#define ISR_TXIDLE 0x00000200 201#define ISR_TXERR 0x00000100 202#define ISR_TXDESC 0x00000080 203#define ISR_TXOK 0x00000040 204#define ISR_RXORN 0x00000020 205#define ISR_RXIDLE 0x00000010 206#define ISR_RXEARLY 0x00000008 207#define ISR_RXERR 0x00000004 208#define ISR_RXDESC 0x00000002 209#define ISR_RXOK 0x00000001 210 211#define TXCFG_CSI 0x80000000 212#define TXCFG_HBI 0x40000000 213#define TXCFG_MLB 0x20000000 214#define TXCFG_ATP 0x10000000 215#define TXCFG_ECRETRY 0x00800000 216#define TXCFG_BRST_DIS 0x00080000 217#define TXCFG_MXDMA1024 0x00000000 218#define TXCFG_MXDMA512 0x00700000 219#define TXCFG_MXDMA256 0x00600000 220#define TXCFG_MXDMA128 0x00500000 221#define TXCFG_MXDMA64 0x00400000 222#define TXCFG_MXDMA32 0x00300000 223#define TXCFG_MXDMA16 0x00200000 224#define TXCFG_MXDMA8 0x00100000 225 226#define CFG_LNKSTS 0x80000000 227#define CFG_SPDSTS 0x60000000 228#define CFG_SPDSTS1 0x40000000 229#define CFG_SPDSTS0 0x20000000 230#define CFG_DUPSTS 0x10000000 231#define CFG_TBI_EN 0x01000000 232#define CFG_MODE_1000 0x00400000 233/* Ramit : Dont' ever use AUTO_1000, it never works and is buggy. 234 * Read the Phy response and then configure the MAC accordingly */ 235#define CFG_AUTO_1000 0x00200000 236#define CFG_PINT_CTL 0x001c0000 237#define CFG_PINT_DUPSTS 0x00100000 238#define CFG_PINT_LNKSTS 0x00080000 239#define CFG_PINT_SPDSTS 0x00040000 240#define CFG_TMRTEST 0x00020000 241#define CFG_MRM_DIS 0x00010000 242#define CFG_MWI_DIS 0x00008000 243#define CFG_T64ADDR 0x00004000 244#define CFG_PCI64_DET 0x00002000 245#define CFG_DATA64_EN 0x00001000 246#define CFG_M64ADDR 0x00000800 247#define CFG_PHY_RST 0x00000400 248#define CFG_PHY_DIS 0x00000200 249#define CFG_EXTSTS_EN 0x00000100 250#define CFG_REQALG 0x00000080 251#define CFG_SB 0x00000040 252#define CFG_POW 0x00000020 253#define CFG_EXD 0x00000010 254#define CFG_PESEL 0x00000008 255#define CFG_BROM_DIS 0x00000004 256#define CFG_EXT_125 0x00000002 257#define CFG_BEM 0x00000001 258 259#define EXTSTS_UDPPKT 0x00200000 260#define EXTSTS_TCPPKT 0x00080000 261#define EXTSTS_IPPKT 0x00020000 262 263#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) 264 265#define MIBC_MIBS 0x00000008 266#define MIBC_ACLR 0x00000004 267#define MIBC_FRZ 0x00000002 268#define MIBC_WRN 0x00000001 269 270#define PCR_PSEN (1 << 31) 271#define PCR_PS_MCAST (1 << 30) 272#define PCR_PS_DA (1 << 29) 273#define PCR_STHI_8 (3 << 23) 274#define PCR_STLO_4 (1 << 23) 275#define PCR_FFHI_8K (3 << 21) 276#define PCR_FFLO_4K (1 << 21) 277#define PCR_PAUSE_CNT 0xFFFE 278 279#define RXCFG_AEP 0x80000000 280#define RXCFG_ARP 0x40000000 281#define RXCFG_STRIPCRC 0x20000000 282#define RXCFG_RX_FD 0x10000000 283#define RXCFG_ALP 0x08000000 284#define RXCFG_AIRL 0x04000000 285#define RXCFG_MXDMA512 0x00700000 286#define RXCFG_DRTH 0x0000003e 287#define RXCFG_DRTH0 0x00000002 288 289#define RFCR_RFEN 0x80000000 290#define RFCR_AAB 0x40000000 291#define RFCR_AAM 0x20000000 292#define RFCR_AAU 0x10000000 293#define RFCR_APM 0x08000000 294#define RFCR_APAT 0x07800000 295#define RFCR_APAT3 0x04000000 296#define RFCR_APAT2 0x02000000 297#define RFCR_APAT1 0x01000000 298#define RFCR_APAT0 0x00800000 299#define RFCR_AARP 0x00400000 300#define RFCR_MHEN 0x00200000 301#define RFCR_UHEN 0x00100000 302#define RFCR_ULM 0x00080000 303 304#define VRCR_RUDPE 0x00000080 305#define VRCR_RTCPE 0x00000040 306#define VRCR_RIPE 0x00000020 307#define VRCR_IPEN 0x00000010 308#define VRCR_DUTF 0x00000008 309#define VRCR_DVTF 0x00000004 310#define VRCR_VTREN 0x00000002 311#define VRCR_VTDEN 0x00000001 312 313#define VTCR_PPCHK 0x00000008 314#define VTCR_GCHK 0x00000004 315#define VTCR_VPPTI 0x00000002 316#define VTCR_VGTI 0x00000001 317 318#define CR 0x00 319#define CFG 0x04 320#define MEAR 0x08 321#define PTSCR 0x0c 322#define ISR 0x10 323#define IMR 0x14 324#define IER 0x18 325#define IHR 0x1c 326#define TXDP 0x20 327#define TXDP_HI 0x24 328#define TXCFG 0x28 329#define GPIOR 0x2c 330#define RXDP 0x30 331#define RXDP_HI 0x34 332#define RXCFG 0x38 333#define PQCR 0x3c 334#define WCSR 0x40 335#define PCR 0x44 336#define RFCR 0x48 337#define RFDR 0x4c 338 339#define SRR 0x58 340 341#define VRCR 0xbc 342#define VTCR 0xc0 343#define VDR 0xc4 344#define CCSR 0xcc 345 346#define TBICR 0xe0 347#define TBISR 0xe4 348#define TANAR 0xe8 349#define TANLPAR 0xec 350#define TANER 0xf0 351#define TESR 0xf4 352 353#define TBICR_MR_AN_ENABLE 0x00001000 354#define TBICR_MR_RESTART_AN 0x00000200 355 356#define TBISR_MR_LINK_STATUS 0x00000020 357#define TBISR_MR_AN_COMPLETE 0x00000004 358 359#define TANAR_PS2 0x00000100 360#define TANAR_PS1 0x00000080 361#define TANAR_HALF_DUP 0x00000040 362#define TANAR_FULL_DUP 0x00000020 363 364#define GPIOR_GP5_OE 0x00000200 365#define GPIOR_GP4_OE 0x00000100 366#define GPIOR_GP3_OE 0x00000080 367#define GPIOR_GP2_OE 0x00000040 368#define GPIOR_GP1_OE 0x00000020 369#define GPIOR_GP3_OUT 0x00000004 370#define GPIOR_GP1_OUT 0x00000001 371 372#define LINK_AUTONEGOTIATE 0x01 373#define LINK_DOWN 0x02 374#define LINK_UP 0x04 375 376#define __kick_rx(dev) writel(CR_RXE, dev->base + CR) 377 378#define kick_rx(dev) do { \ 379 dprintk("kick_rx: maybe kicking\n"); \ 380 if (test_and_clear_bit(0, &dev->rx_info.idle)) { \ 381 dprintk("actually kicking\n"); \ 382 writel(dev->rx_info.phy_descs + (4 * DESC_SIZE * dev->rx_info.next_rx), dev->base + RXDP); \ 383 if (dev->rx_info.next_rx == dev->rx_info.next_empty) \ 384 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n", dev->net_dev.name);\ 385 __kick_rx(dev); \ 386 } \ 387} while(0) 388 389#ifdef USE_64BIT_ADDR 390#define HW_ADDR_LEN 8 391#define desc_addr_set(desc, addr) \ 392 do { \ 393 u64 __addr = (addr); \ 394 (desc)[0] = cpu_to_le32(__addr); \ 395 (desc)[1] = cpu_to_le32(__addr >> 32); \ 396 } while(0) 397#define desc_addr_get(desc) \ 398 (((u64)le32_to_cpu((desc)[1]) << 32) \ 399 | le32_to_cpu((desc)[0])) 400#else 401#define HW_ADDR_LEN 4 402#define desc_addr_set(desc, addr) ((desc)[0] = cpu_to_le32(addr)) 403#define desc_addr_get(desc) (le32_to_cpu((desc)[0])) 404#endif 405 406#define DESC_LINK 0 407#define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4) 408#define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4) 409#define DESC_EXTSTS (DESC_CMDSTS + 4/4) 410 411#define CMDSTS_OWN 0x80000000 412#define CMDSTS_MORE 0x40000000 413#define CMDSTS_INTR 0x20000000 414#define CMDSTS_ERR 0x10000000 415#define CMDSTS_OK 0x08000000 416#define CMDSTS_LEN_MASK 0x0000ffff 417 418#define CMDSTS_DEST_MASK 0x01800000 419#define CMDSTS_DEST_SELF 0x00800000 420#define CMDSTS_DEST_MULTI 0x01000000 421 422#define DESC_SIZE 8 /* Should be cache line sized */ 423 424struct rx_info { 425 spinlock_t lock; 426 int up; 427 long idle; 428 429 struct sk_buff *skbs[NR_RX_DESC]; 430 431 u32 *next_rx_desc; 432 u16 next_rx, next_empty; 433 434 u32 *descs; 435 dma_addr_t phy_descs; 436}; 437 438 439struct ns83820 { 440 struct net_device net_dev; 441 struct net_device_stats stats; 442 u8 *base; 443 444 struct pci_dev *pci_dev; 445 446 struct rx_info rx_info; 447 struct tasklet_struct rx_tasklet; 448 449 unsigned ihr; 450 struct tq_struct tq_refill; 451 452 /* protects everything below. irqsave when using. */ 453 spinlock_t misc_lock; 454 455 u32 CFG_cache; 456 457 u32 MEAR_cache; 458 u32 IMR_cache; 459 struct eeprom ee; 460 461 unsigned linkstate; 462 463 spinlock_t tx_lock; 464 465 u16 tx_done_idx; 466 u16 tx_idx; 467 volatile u16 tx_free_idx; /* idx of free desc chain */ 468 u16 tx_intr_idx; 469 470 atomic_t nr_tx_skbs; 471 struct sk_buff *tx_skbs[NR_TX_DESC]; 472 473 char pad[16] __attribute__((aligned(16))); 474 u32 *tx_descs; 475 dma_addr_t tx_phy_descs; 476 477 struct timer_list tx_watchdog; 478}; 479 480//free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC 481#define start_tx_okay(dev) \ 482 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE) 483 484 485/* Packet Receiver 486 * 487 * The hardware supports linked lists of receive descriptors for 488 * which ownership is transfered back and forth by means of an 489 * ownership bit. While the hardware does support the use of a 490 * ring for receive descriptors, we only make use of a chain in 491 * an attempt to reduce bus traffic under heavy load scenarios. 492 * This will also make bugs a bit more obvious. The current code 493 * only makes use of a single rx chain; I hope to implement 494 * priority based rx for version 1.0. Goal: even under overload 495 * conditions, still route realtime traffic with as low jitter as 496 * possible. 497 */ 498static inline void build_rx_desc(struct ns83820 *dev, u32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts) 499{ 500 desc_addr_set(desc + DESC_LINK, link); 501 desc_addr_set(desc + DESC_BUFPTR, buf); 502 desc[DESC_EXTSTS] = extsts; 503 mb(); 504 desc[DESC_CMDSTS] = cmdsts; 505} 506 507#define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC) 508static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb) 509{ 510 unsigned next_empty; 511 u32 cmdsts; 512 u32 *sg; 513 dma_addr_t buf; 514 515 next_empty = dev->rx_info.next_empty; 516 517 /* don't overrun last rx marker */ 518 if (unlikely(nr_rx_empty(dev) <= 2)) { 519 kfree_skb(skb); 520 return 1; 521 } 522 523 524 sg = dev->rx_info.descs + (next_empty * DESC_SIZE); 525 if (unlikely(NULL != dev->rx_info.skbs[next_empty])) 526 BUG(); 527 dev->rx_info.skbs[next_empty] = skb; 528 529 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC; 530 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR; 531 buf = pci_map_single(dev->pci_dev, skb->tail, 532 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); 533 build_rx_desc(dev, sg, 0, buf, cmdsts, 0); 534 /* update link of previous rx */ 535 if (likely(next_empty != dev->rx_info.next_rx)) 536 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4)); 537 538 return 0; 539} 540 541static inline int rx_refill(struct ns83820 *dev, int gfp) 542{ 543 unsigned i; 544 long flags = 0; 545 546 if (unlikely(nr_rx_empty(dev) <= 2)) 547 return 0; 548 549 dprintk("rx_refill(%p)\n", dev); 550 if (gfp == GFP_ATOMIC) 551 spin_lock_irqsave(&dev->rx_info.lock, flags); 552 for (i=0; i<NR_RX_DESC; i++) { 553 struct sk_buff *skb; 554 long res; 555 /* extra 16 bytes for alignment */ 556 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp); 557 if (unlikely(!skb)) 558 break; 559 560 res = (long)skb->tail & 0xf; 561 res = 0x10 - res; 562 res &= 0xf; 563 skb_reserve(skb, res); 564 565 skb->dev = &dev->net_dev; 566 if (gfp != GFP_ATOMIC) 567 spin_lock_irqsave(&dev->rx_info.lock, flags); 568 res = ns83820_add_rx_skb(dev, skb); 569 if (gfp != GFP_ATOMIC) 570 spin_unlock_irqrestore(&dev->rx_info.lock, flags); 571 if (res) { 572 i = 1; 573 break; 574 } 575 } 576 if (gfp == GFP_ATOMIC) 577 spin_unlock_irqrestore(&dev->rx_info.lock, flags); 578 579 return i ? 0 : -ENOMEM; 580} 581 582static void FASTCALL(rx_refill_atomic(struct ns83820 *dev)); 583static void rx_refill_atomic(struct ns83820 *dev) 584{ 585 rx_refill(dev, GFP_ATOMIC); 586} 587 588/* REFILL */ 589static inline void queue_refill(void *_dev) 590{ 591 struct ns83820 *dev = _dev; 592 593 rx_refill(dev, GFP_KERNEL); 594 if (dev->rx_info.up) 595 kick_rx(dev); 596} 597 598static inline void clear_rx_desc(struct ns83820 *dev, unsigned i) 599{ 600 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0); 601} 602 603static void FASTCALL(phy_intr(struct ns83820 *dev)); 604static void phy_intr(struct ns83820 *dev) 605{ 606 static char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" }; 607 u32 cfg, new_cfg; 608 u32 tbisr, tanar, tanlpar; 609 int speed, fullduplex, newlinkstate; 610 611 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 612 613 if (dev->CFG_cache & CFG_TBI_EN) { 614 /* we have an optical transceiver */ 615 tbisr = readl(dev->base + TBISR); 616 tanar = readl(dev->base + TANAR); 617 tanlpar = readl(dev->base + TANLPAR); 618 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n", 619 tbisr, tanar, tanlpar); 620 621 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) 622 && (tanar & TANAR_FULL_DUP)) ) { 623 624 /* both of us are full duplex */ 625 writel(readl(dev->base + TXCFG) 626 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, 627 dev->base + TXCFG); 628 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, 629 dev->base + RXCFG); 630 /* Light up full duplex LED */ 631 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, 632 dev->base + GPIOR); 633 634 } else if(((tanlpar & TANAR_HALF_DUP) 635 && (tanar & TANAR_HALF_DUP)) 636 || ((tanlpar & TANAR_FULL_DUP) 637 && (tanar & TANAR_HALF_DUP)) 638 || ((tanlpar & TANAR_HALF_DUP) 639 && (tanar & TANAR_FULL_DUP))) { 640 641 /* one or both of us are half duplex */ 642 writel((readl(dev->base + TXCFG) 643 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP, 644 dev->base + TXCFG); 645 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, 646 dev->base + RXCFG); 647 /* Turn off full duplex LED */ 648 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, 649 dev->base + GPIOR); 650 } 651 652 speed = 4; /* 1000F */ 653 654 } else { 655 /* we have a copper transceiver */ 656 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS); 657 658 if (cfg & CFG_SPDSTS1) 659 new_cfg |= CFG_MODE_1000; 660 else 661 new_cfg &= ~CFG_MODE_1000; 662 663 speed = ((cfg / CFG_SPDSTS0) & 3); 664 fullduplex = (cfg & CFG_DUPSTS); 665 666 if (fullduplex) 667 new_cfg |= CFG_SB; 668 669 if ((cfg & CFG_LNKSTS) && 670 ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) { 671 writel(new_cfg, dev->base + CFG); 672 dev->CFG_cache = new_cfg; 673 } 674 675 dev->CFG_cache &= ~CFG_SPDSTS; 676 dev->CFG_cache |= cfg & CFG_SPDSTS; 677 } 678 679 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN; 680 681 if (newlinkstate & LINK_UP 682 && dev->linkstate != newlinkstate) { 683 netif_start_queue(&dev->net_dev); 684 netif_wake_queue(&dev->net_dev); 685 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n", 686 dev->net_dev.name, 687 speeds[speed], 688 fullduplex ? "full" : "half"); 689 } else if (newlinkstate & LINK_DOWN 690 && dev->linkstate != newlinkstate) { 691 netif_stop_queue(&dev->net_dev); 692 printk(KERN_INFO "%s: link now down.\n", dev->net_dev.name); 693 } 694 695 dev->linkstate = newlinkstate; 696} 697 698static int ns83820_setup_rx(struct ns83820 *dev) 699{ 700 unsigned i; 701 int ret; 702 703 dprintk("ns83820_setup_rx(%p)\n", dev); 704 705 dev->rx_info.idle = 1; 706 dev->rx_info.next_rx = 0; 707 dev->rx_info.next_rx_desc = dev->rx_info.descs; 708 dev->rx_info.next_empty = 0; 709 710 for (i=0; i<NR_RX_DESC; i++) 711 clear_rx_desc(dev, i); 712 713 writel(0, dev->base + RXDP_HI); 714 writel(dev->rx_info.phy_descs, dev->base + RXDP); 715 716 ret = rx_refill(dev, GFP_KERNEL); 717 if (!ret) { 718 dprintk("starting receiver\n"); 719 /* prevent the interrupt handler from stomping on us */ 720 spin_lock_irq(&dev->rx_info.lock); 721 722 writel(0x0001, dev->base + CCSR); 723 writel(0, dev->base + RFCR); 724 writel(0x7fc00000, dev->base + RFCR); 725 writel(0xffc00000, dev->base + RFCR); 726 727 dev->rx_info.up = 1; 728 729 phy_intr(dev); 730 731 /* Okay, let it rip */ 732 spin_lock_irq(&dev->misc_lock); 733 dev->IMR_cache |= ISR_PHY; 734 dev->IMR_cache |= ISR_RXRCMP; 735 //dev->IMR_cache |= ISR_RXERR; 736 //dev->IMR_cache |= ISR_RXOK; 737 dev->IMR_cache |= ISR_RXORN; 738 dev->IMR_cache |= ISR_RXSOVR; 739 dev->IMR_cache |= ISR_RXDESC; 740 dev->IMR_cache |= ISR_RXIDLE; 741 dev->IMR_cache |= ISR_TXDESC; 742 dev->IMR_cache |= ISR_TXIDLE; 743 744 writel(dev->IMR_cache, dev->base + IMR); 745 writel(1, dev->base + IER); 746 spin_unlock_irq(&dev->misc_lock); 747 748 kick_rx(dev); 749 750 spin_unlock_irq(&dev->rx_info.lock); 751 } 752 return ret; 753} 754 755static void ns83820_cleanup_rx(struct ns83820 *dev) 756{ 757 unsigned i; 758 long flags; 759 760 dprintk("ns83820_cleanup_rx(%p)\n", dev); 761 762 /* disable receive interrupts */ 763 spin_lock_irqsave(&dev->misc_lock, flags); 764 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE); 765 writel(dev->IMR_cache, dev->base + IMR); 766 spin_unlock_irqrestore(&dev->misc_lock, flags); 767 768 /* synchronize with the interrupt handler and kill it */ 769 dev->rx_info.up = 0; 770 synchronize_irq(); 771 772 /* touch the pci bus... */ 773 readl(dev->base + IMR); 774 775 /* assumes the transmitter is already disabled and reset */ 776 writel(0, dev->base + RXDP_HI); 777 writel(0, dev->base + RXDP); 778 779 for (i=0; i<NR_RX_DESC; i++) { 780 struct sk_buff *skb = dev->rx_info.skbs[i]; 781 dev->rx_info.skbs[i] = NULL; 782 clear_rx_desc(dev, i); 783 if (skb) 784 kfree_skb(skb); 785 } 786} 787 788static void FASTCALL(ns83820_rx_kick(struct ns83820 *dev)); 789static void ns83820_rx_kick(struct ns83820 *dev) 790{ 791 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ { 792 if (dev->rx_info.up) { 793 rx_refill_atomic(dev); 794 kick_rx(dev); 795 } 796 } 797 798 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4) 799 schedule_task(&dev->tq_refill); 800 else 801 kick_rx(dev); 802 if (dev->rx_info.idle) 803 printk(KERN_DEBUG "%s: BAD\n", dev->net_dev.name); 804} 805 806/* rx_irq 807 * 808 */ 809static void FASTCALL(rx_irq(struct ns83820 *dev)); 810static void rx_irq(struct ns83820 *dev) 811{ 812 struct rx_info *info = &dev->rx_info; 813 unsigned next_rx; 814 u32 cmdsts, *desc; 815 long flags; 816 int nr = 0; 817 818 dprintk("rx_irq(%p)\n", dev); 819 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n", 820 readl(dev->base + RXDP), 821 (long)(dev->rx_info.phy_descs), 822 (int)dev->rx_info.next_rx, 823 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)), 824 (int)dev->rx_info.next_empty, 825 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty)) 826 ); 827 828 spin_lock_irqsave(&info->lock, flags); 829 if (!info->up) 830 goto out; 831 832 dprintk("walking descs\n"); 833 next_rx = info->next_rx; 834 desc = info->next_rx_desc; 835 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) && 836 (cmdsts != CMDSTS_OWN)) { 837 struct sk_buff *skb; 838 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]); 839 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR); 840 841 dprintk("cmdsts: %08x\n", cmdsts); 842 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK])); 843 dprintk("extsts: %08x\n", extsts); 844 845 skb = info->skbs[next_rx]; 846 info->skbs[next_rx] = NULL; 847 info->next_rx = (next_rx + 1) % NR_RX_DESC; 848 849 mb(); 850 clear_rx_desc(dev, next_rx); 851 852 pci_unmap_single(dev->pci_dev, bufptr, 853 RX_BUF_SIZE, PCI_DMA_FROMDEVICE); 854 if (likely(CMDSTS_OK & cmdsts)) { 855 int len = cmdsts & 0xffff; 856 skb_put(skb, len); 857 if (unlikely(!skb)) 858 goto netdev_mangle_me_harder_failed; 859 if (cmdsts & CMDSTS_DEST_MULTI) 860 dev->stats.multicast ++; 861 dev->stats.rx_packets ++; 862 dev->stats.rx_bytes += len; 863 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) { 864 skb->ip_summed = CHECKSUM_UNNECESSARY; 865 } else { 866 skb->ip_summed = CHECKSUM_NONE; 867 } 868 skb->protocol = eth_type_trans(skb, &dev->net_dev); 869 if (NET_RX_DROP == netif_rx(skb)) { 870netdev_mangle_me_harder_failed: 871 dev->stats.rx_dropped ++; 872 } 873 } else { 874 kfree_skb(skb); 875 } 876 877 nr++; 878 next_rx = info->next_rx; 879 desc = info->descs + (DESC_SIZE * next_rx); 880 } 881 info->next_rx = next_rx; 882 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx); 883 884out: 885 if (0 && !nr) { 886 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts); 887 } 888 889 spin_unlock_irqrestore(&info->lock, flags); 890} 891 892static void rx_action(unsigned long _dev) 893{ 894 struct ns83820 *dev = (void *)_dev; 895 rx_irq(dev); 896 writel(ihr, dev->base + IHR); 897 898 spin_lock_irq(&dev->misc_lock); 899 dev->IMR_cache |= ISR_RXDESC; 900 writel(dev->IMR_cache, dev->base + IMR); 901 spin_unlock_irq(&dev->misc_lock); 902 903 rx_irq(dev); 904 ns83820_rx_kick(dev); 905} 906 907/* Packet Transmit code 908 */ 909static inline void kick_tx(struct ns83820 *dev) 910{ 911 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n", 912 dev, dev->tx_idx, dev->tx_free_idx); 913 writel(CR_TXE, dev->base + CR); 914} 915 916/* No spinlock needed on the transmit irq path as the interrupt handler is 917 * serialized. 918 */ 919static void do_tx_done(struct ns83820 *dev) 920{ 921 u32 cmdsts, tx_done_idx, *desc; 922 923 spin_lock_irq(&dev->tx_lock); 924 925 dprintk("do_tx_done(%p)\n", dev); 926 tx_done_idx = dev->tx_done_idx; 927 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 928 929 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 930 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 931 while ((tx_done_idx != dev->tx_free_idx) && 932 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) { 933 struct sk_buff *skb; 934 unsigned len; 935 dma_addr_t addr; 936 937 if (cmdsts & CMDSTS_ERR) 938 dev->stats.tx_errors ++; 939 if (cmdsts & CMDSTS_OK) 940 dev->stats.tx_packets ++; 941 if (cmdsts & CMDSTS_OK) 942 dev->stats.tx_bytes += cmdsts & 0xffff; 943 944 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 945 tx_done_idx, dev->tx_free_idx, cmdsts); 946 skb = dev->tx_skbs[tx_done_idx]; 947 dev->tx_skbs[tx_done_idx] = NULL; 948 dprintk("done(%p)\n", skb); 949 950 len = cmdsts & CMDSTS_LEN_MASK; 951 addr = desc_addr_get(desc + DESC_BUFPTR); 952 if (skb) { 953 pci_unmap_single(dev->pci_dev, 954 addr, 955 len, 956 PCI_DMA_TODEVICE); 957 dev_kfree_skb_irq(skb); 958 atomic_dec(&dev->nr_tx_skbs); 959 } else 960 pci_unmap_page(dev->pci_dev, 961 addr, 962 len, 963 PCI_DMA_TODEVICE); 964 965 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC; 966 dev->tx_done_idx = tx_done_idx; 967 desc[DESC_CMDSTS] = cpu_to_le32(0); 968 mb(); 969 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 970 } 971 972 /* Allow network stack to resume queueing packets after we've 973 * finished transmitting at least 1/4 of the packets in the queue. 974 */ 975 if (netif_queue_stopped(&dev->net_dev) && start_tx_okay(dev)) { 976 dprintk("start_queue(%p)\n", dev); 977 netif_start_queue(&dev->net_dev); 978 netif_wake_queue(&dev->net_dev); 979 } 980 spin_unlock_irq(&dev->tx_lock); 981} 982 983static void ns83820_cleanup_tx(struct ns83820 *dev) 984{ 985 unsigned i; 986 987 for (i=0; i<NR_TX_DESC; i++) { 988 struct sk_buff *skb = dev->tx_skbs[i]; 989 dev->tx_skbs[i] = NULL; 990 if (skb) { 991 u32 *desc = dev->tx_descs + (i * DESC_SIZE); 992 pci_unmap_single(dev->pci_dev, 993 desc_addr_get(desc + DESC_BUFPTR), 994 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK, 995 PCI_DMA_TODEVICE); 996 dev_kfree_skb_irq(skb); 997 atomic_dec(&dev->nr_tx_skbs); 998 } 999 } 1000 1001 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4); 1002} 1003 1004/* transmit routine. This code relies on the network layer serializing 1005 * its calls in, but will run happily in parallel with the interrupt 1006 * handler. This code currently has provisions for fragmenting tx buffers 1007 * while trying to track down a bug in either the zero copy code or 1008 * the tx fifo (hence the MAX_FRAG_LEN). 1009 */ 1010static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *_dev) 1011{ 1012 struct ns83820 *dev = (struct ns83820 *)_dev; 1013 u32 free_idx, cmdsts, extsts; 1014 int nr_free, nr_frags; 1015 unsigned tx_done_idx, last_idx; 1016 dma_addr_t buf; 1017 unsigned len; 1018 skb_frag_t *frag; 1019 int stopped = 0; 1020 int do_intr = 0; 1021 volatile u32 *first_desc; 1022 1023 dprintk("ns83820_hard_start_xmit\n"); 1024 1025 nr_frags = skb_shinfo(skb)->nr_frags; 1026again: 1027 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) { 1028 netif_stop_queue(&dev->net_dev); 1029 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) 1030 return 1; 1031 netif_start_queue(&dev->net_dev); 1032 } 1033 1034 last_idx = free_idx = dev->tx_free_idx; 1035 tx_done_idx = dev->tx_done_idx; 1036 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC; 1037 nr_free -= 1; 1038 if (nr_free <= nr_frags) { 1039 dprintk("stop_queue - not enough(%p)\n", dev); 1040 netif_stop_queue(&dev->net_dev); 1041 1042 /* Check again: we may have raced with a tx done irq */ 1043 if (dev->tx_done_idx != tx_done_idx) { 1044 dprintk("restart queue(%p)\n", dev); 1045 netif_start_queue(&dev->net_dev); 1046 goto again; 1047 } 1048 return 1; 1049 } 1050 1051 if (free_idx == dev->tx_intr_idx) { 1052 do_intr = 1; 1053 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC; 1054 } 1055 1056 nr_free -= nr_frags; 1057 if (nr_free < MIN_TX_DESC_FREE) { 1058 dprintk("stop_queue - last entry(%p)\n", dev); 1059 netif_stop_queue(&dev->net_dev); 1060 stopped = 1; 1061 } 1062 1063 frag = skb_shinfo(skb)->frags; 1064 if (!nr_frags) 1065 frag = 0; 1066 extsts = 0; 1067 if (skb->ip_summed == CHECKSUM_HW) { 1068 extsts |= EXTSTS_IPPKT; 1069 if (IPPROTO_TCP == skb->nh.iph->protocol) 1070 extsts |= EXTSTS_TCPPKT; 1071 else if (IPPROTO_UDP == skb->nh.iph->protocol) 1072 extsts |= EXTSTS_UDPPKT; 1073 } 1074 1075 len = skb->len; 1076 if (nr_frags) 1077 len -= skb->data_len; 1078 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE); 1079 1080 first_desc = dev->tx_descs + (free_idx * DESC_SIZE); 1081 1082 for (;;) { 1083 volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE); 1084 u32 residue = 0; 1085 1086 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len, 1087 (unsigned long long)buf); 1088 last_idx = free_idx; 1089 free_idx = (free_idx + 1) % NR_TX_DESC; 1090 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4)); 1091 desc_addr_set(desc + DESC_BUFPTR, buf); 1092 desc[DESC_EXTSTS] = cpu_to_le32(extsts); 1093 1094 cmdsts = ((nr_frags|residue) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0); 1095 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN; 1096 cmdsts |= len; 1097 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); 1098 1099 if (residue) { 1100 buf += len; 1101 len = residue; 1102 continue; 1103 } 1104 1105 if (!nr_frags) 1106 break; 1107 1108 buf = pci_map_page(dev->pci_dev, frag->page, 1109 frag->page_offset, 1110 frag->size, PCI_DMA_TODEVICE); 1111 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n", 1112 (long long)buf, (long)(frag->page - mem_map), 1113 frag->page_offset); 1114 len = frag->size; 1115 frag++; 1116 nr_frags--; 1117 } 1118 dprintk("done pkt\n"); 1119 1120 spin_lock_irq(&dev->tx_lock); 1121 dev->tx_skbs[last_idx] = skb; 1122 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN); 1123 dev->tx_free_idx = free_idx; 1124 atomic_inc(&dev->nr_tx_skbs); 1125 spin_unlock_irq(&dev->tx_lock); 1126 1127 kick_tx(dev); 1128 1129 /* Check again: we may have raced with a tx done irq */ 1130 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev)) 1131 netif_start_queue(&dev->net_dev); 1132 1133 /* set the transmit start time to catch transmit timeouts */ 1134 dev->net_dev.trans_start = jiffies; 1135 return 0; 1136} 1137 1138static void ns83820_update_stats(struct ns83820 *dev) 1139{ 1140 u8 *base = dev->base; 1141 1142 /* the DP83820 will freeze counters, so we need to read all of them */ 1143 dev->stats.rx_errors += readl(base + 0x60) & 0xffff; 1144 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff; 1145 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff; 1146 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff; 1147 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70); 1148 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff; 1149 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff; 1150 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c); 1151 /*dev->stats.rx_pause_count += */ readl(base + 0x80); 1152 /*dev->stats.tx_pause_count += */ readl(base + 0x84); 1153 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff; 1154} 1155 1156static struct net_device_stats *ns83820_get_stats(struct net_device *_dev) 1157{ 1158 struct ns83820 *dev = (void *)_dev; 1159 1160 /* somewhat overkill */ 1161 spin_lock_irq(&dev->misc_lock); 1162 ns83820_update_stats(dev); 1163 spin_unlock_irq(&dev->misc_lock); 1164 1165 return &dev->stats; 1166} 1167 1168static int ns83820_ethtool_ioctl (struct ns83820 *dev, void *useraddr) 1169{ 1170 u32 ethcmd; 1171 1172 if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd))) 1173 return -EFAULT; 1174 1175 switch (ethcmd) { 1176 case ETHTOOL_GDRVINFO: 1177 { 1178 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO }; 1179 strcpy(info.driver, "ns83820"); 1180 strcpy(info.version, VERSION); 1181 strcpy(info.bus_info, dev->pci_dev->slot_name); 1182 if (copy_to_user(useraddr, &info, sizeof (info))) 1183 return -EFAULT; 1184 return 0; 1185 } 1186 1187 /* get link status */ 1188 case ETHTOOL_GLINK: { 1189 struct ethtool_value edata = { ETHTOOL_GLINK }; 1190 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 1191 1192 if (cfg & CFG_LNKSTS) 1193 edata.data = 1; 1194 else 1195 edata.data = 0; 1196 if (copy_to_user(useraddr, &edata, sizeof(edata))) 1197 return -EFAULT; 1198 return 0; 1199 } 1200 1201 default: 1202 break; 1203 } 1204 1205 return -EOPNOTSUPP; 1206} 1207 1208static int ns83820_ioctl(struct net_device *_dev, struct ifreq *rq, int cmd) 1209{ 1210 struct ns83820 *dev = _dev->priv; 1211 1212 switch(cmd) { 1213 case SIOCETHTOOL: 1214 return ns83820_ethtool_ioctl(dev, (void *) rq->ifr_data); 1215 1216 default: 1217 return -EOPNOTSUPP; 1218 } 1219} 1220 1221static void ns83820_mib_isr(struct ns83820 *dev) 1222{ 1223 spin_lock(&dev->misc_lock); 1224 ns83820_update_stats(dev); 1225 spin_unlock(&dev->misc_lock); 1226} 1227 1228static void ns83820_do_isr(struct ns83820 *dev, u32 isr); 1229static void ns83820_irq(int foo, void *data, struct pt_regs *regs) 1230{ 1231 struct ns83820 *dev = data; 1232 u32 isr; 1233 dprintk("ns83820_irq(%p)\n", dev); 1234 1235 dev->ihr = 0; 1236 1237 isr = readl(dev->base + ISR); 1238 dprintk("irq: %08x\n", isr); 1239 ns83820_do_isr(dev, isr); 1240} 1241 1242static void ns83820_do_isr(struct ns83820 *dev, u32 isr) 1243{ 1244#ifdef DEBUG 1245 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC)) 1246 Dprintk("odd isr? 0x%08x\n", isr); 1247#endif 1248 1249 if (ISR_RXIDLE & isr) { 1250 dev->rx_info.idle = 1; 1251 Dprintk("oh dear, we are idle\n"); 1252 ns83820_rx_kick(dev); 1253 } 1254 1255 if ((ISR_RXDESC | ISR_RXOK) & isr) { 1256 prefetch(dev->rx_info.next_rx_desc); 1257 1258 spin_lock_irq(&dev->misc_lock); 1259 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK); 1260 writel(dev->IMR_cache, dev->base + IMR); 1261 spin_unlock_irq(&dev->misc_lock); 1262 1263 tasklet_schedule(&dev->rx_tasklet); 1264 //rx_irq(dev); 1265 //writel(4, dev->base + IHR); 1266 } 1267 1268 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr) 1269 ns83820_rx_kick(dev); 1270 1271 if (unlikely(ISR_RXSOVR & isr)) { 1272 //printk("overrun: rxsovr\n"); 1273 dev->stats.rx_fifo_errors ++; 1274 } 1275 1276 if (unlikely(ISR_RXORN & isr)) { 1277 //printk("overrun: rxorn\n"); 1278 dev->stats.rx_fifo_errors ++; 1279 } 1280 1281 if ((ISR_RXRCMP & isr) && dev->rx_info.up) 1282 writel(CR_RXE, dev->base + CR); 1283 1284 if (ISR_TXIDLE & isr) { 1285 u32 txdp; 1286 txdp = readl(dev->base + TXDP); 1287 dprintk("txdp: %08x\n", txdp); 1288 txdp -= dev->tx_phy_descs; 1289 dev->tx_idx = txdp / (DESC_SIZE * 4); 1290 if (dev->tx_idx >= NR_TX_DESC) { 1291 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", dev->net_dev.name); 1292 dev->tx_idx = 0; 1293 } 1294 /* The may have been a race between a pci originated read 1295 * and the descriptor update from the cpu. Just in case, 1296 * kick the transmitter if the hardware thinks it is on a 1297 * different descriptor than we are. 1298 */ 1299 if (dev->tx_idx != dev->tx_free_idx) 1300 kick_tx(dev); 1301 } 1302 1303 /* Defer tx ring processing until more than a minimum amount of 1304 * work has accumulated 1305 */ 1306 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) { 1307 do_tx_done(dev); 1308 1309 /* Disable TxOk if there are no outstanding tx packets. 1310 */ 1311 if ((dev->tx_done_idx == dev->tx_free_idx) && 1312 (dev->IMR_cache & ISR_TXOK)) { 1313 spin_lock_irq(&dev->misc_lock); 1314 dev->IMR_cache &= ~ISR_TXOK; 1315 writel(dev->IMR_cache, dev->base + IMR); 1316 spin_unlock_irq(&dev->misc_lock); 1317 } 1318 } 1319 1320 /* The TxIdle interrupt can come in before the transmit has 1321 * completed. Normally we reap packets off of the combination 1322 * of TxDesc and TxIdle and leave TxOk disabled (since it 1323 * occurs on every packet), but when no further irqs of this 1324 * nature are expected, we must enable TxOk. 1325 */ 1326 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) { 1327 spin_lock_irq(&dev->misc_lock); 1328 dev->IMR_cache |= ISR_TXOK; 1329 writel(dev->IMR_cache, dev->base + IMR); 1330 spin_unlock_irq(&dev->misc_lock); 1331 } 1332 1333 /* MIB interrupt: one of the statistics counters is about to overflow */ 1334 if (unlikely(ISR_MIB & isr)) 1335 ns83820_mib_isr(dev); 1336 1337 /* PHY: Link up/down/negotiation state change */ 1338 if (unlikely(ISR_PHY & isr)) 1339 phy_intr(dev); 1340 1341} 1342 1343static void ns83820_do_reset(struct ns83820 *dev, u32 which) 1344{ 1345 Dprintk("resetting chip...\n"); 1346 writel(which, dev->base + CR); 1347 do { 1348 schedule(); 1349 } while (readl(dev->base + CR) & which); 1350 Dprintk("okay!\n"); 1351} 1352 1353static int ns83820_stop(struct net_device *_dev) 1354{ 1355 struct ns83820 *dev = (struct ns83820 *)_dev; 1356 1357 del_timer_sync(&dev->tx_watchdog); 1358 1359 /* disable interrupts */ 1360 writel(0, dev->base + IMR); 1361 writel(0, dev->base + IER); 1362 readl(dev->base + IER); 1363 1364 dev->rx_info.up = 0; 1365 synchronize_irq(); 1366 1367 ns83820_do_reset(dev, CR_RST); 1368 1369 synchronize_irq(); 1370 1371 spin_lock_irq(&dev->misc_lock); 1372 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK); 1373 spin_unlock_irq(&dev->misc_lock); 1374 1375 ns83820_cleanup_rx(dev); 1376 ns83820_cleanup_tx(dev); 1377 1378 return 0; 1379} 1380 1381static void ns83820_do_isr(struct ns83820 *dev, u32 isr); 1382static void ns83820_tx_timeout(struct net_device *_dev) 1383{ 1384 struct ns83820 *dev = (struct ns83820 *)_dev; 1385 u32 tx_done_idx, *desc; 1386 long flags; 1387 1388 __save_flags(flags); 1389 __cli(); 1390 1391 tx_done_idx = dev->tx_done_idx; 1392 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1393 1394 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 1395 dev->net_dev.name, 1396 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 1397 1398#if defined(DEBUG) 1399 { 1400 u32 isr; 1401 isr = readl(dev->base + ISR); 1402 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache); 1403 ns83820_do_isr(dev, isr); 1404 } 1405#endif 1406 1407 do_tx_done(dev); 1408 1409 tx_done_idx = dev->tx_done_idx; 1410 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1411 1412 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 1413 dev->net_dev.name, 1414 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 1415 1416 __restore_flags(flags); 1417} 1418 1419static void ns83820_tx_watch(unsigned long data) 1420{ 1421 struct ns83820 *dev = (void *)data; 1422 1423#if defined(DEBUG) 1424 printk("ns83820_tx_watch: %u %u %d\n", 1425 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs) 1426 ); 1427#endif 1428 1429 if (time_after(jiffies, dev->net_dev.trans_start + 1*HZ) && 1430 dev->tx_done_idx != dev->tx_free_idx) { 1431 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n", 1432 dev->net_dev.name, 1433 dev->tx_done_idx, dev->tx_free_idx, 1434 atomic_read(&dev->nr_tx_skbs)); 1435 ns83820_tx_timeout(&dev->net_dev); 1436 } 1437 1438 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ); 1439} 1440 1441static int ns83820_open(struct net_device *_dev) 1442{ 1443 struct ns83820 *dev = (struct ns83820 *)_dev; 1444 unsigned i; 1445 u32 desc; 1446 int ret; 1447 1448 dprintk("ns83820_open\n"); 1449 1450 writel(0, dev->base + PQCR); 1451 1452 ret = ns83820_setup_rx(dev); 1453 if (ret) 1454 goto failed; 1455 1456 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE); 1457 for (i=0; i<NR_TX_DESC; i++) { 1458 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK] 1459 = cpu_to_le32( 1460 dev->tx_phy_descs 1461 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4); 1462 } 1463 1464 dev->tx_idx = 0; 1465 dev->tx_done_idx = 0; 1466 desc = dev->tx_phy_descs; 1467 writel(0, dev->base + TXDP_HI); 1468 writel(desc, dev->base + TXDP); 1469 1470 init_timer(&dev->tx_watchdog); 1471 dev->tx_watchdog.data = (unsigned long)dev; 1472 dev->tx_watchdog.function = ns83820_tx_watch; 1473 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ); 1474 1475 netif_start_queue(&dev->net_dev); 1476 1477 return 0; 1478 1479failed: 1480 ns83820_stop(_dev); 1481 return ret; 1482} 1483 1484static void ns83820_getmac(struct ns83820 *dev, u8 *mac) 1485{ 1486 unsigned i; 1487 for (i=0; i<3; i++) { 1488 u32 data; 1489 /* Read from the perfect match memory: this is loaded by 1490 * the chip from the EEPROM via the EELOAD self test. 1491 */ 1492 writel(i*2, dev->base + RFCR); 1493 data = readl(dev->base + RFDR); 1494 *mac++ = data; 1495 *mac++ = data >> 8; 1496 } 1497} 1498 1499static int ns83820_change_mtu(struct net_device *_dev, int new_mtu) 1500{ 1501 if (new_mtu > RX_BUF_SIZE) 1502 return -EINVAL; 1503 _dev->mtu = new_mtu; 1504 return 0; 1505} 1506 1507static void ns83820_set_multicast(struct net_device *_dev) 1508{ 1509 struct ns83820 *dev = (void *)_dev; 1510 u8 *rfcr = dev->base + RFCR; 1511 u32 and_mask = 0xffffffff; 1512 u32 or_mask = 0; 1513 u32 val; 1514 1515 if (dev->net_dev.flags & IFF_PROMISC) 1516 or_mask |= RFCR_AAU | RFCR_AAM; 1517 else 1518 and_mask &= ~(RFCR_AAU | RFCR_AAM); 1519 1520 if (dev->net_dev.flags & IFF_ALLMULTI) 1521 or_mask |= RFCR_AAM; 1522 else 1523 and_mask &= ~RFCR_AAM; 1524 1525 spin_lock_irq(&dev->misc_lock); 1526 val = (readl(rfcr) & and_mask) | or_mask; 1527 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */ 1528 writel(val & ~RFCR_RFEN, rfcr); 1529 writel(val, rfcr); 1530 spin_unlock_irq(&dev->misc_lock); 1531} 1532 1533static void ns83820_run_bist(struct ns83820 *dev, const char *name, u32 enable, u32 done, u32 fail) 1534{ 1535 int timed_out = 0; 1536 long start; 1537 u32 status; 1538 int loops = 0; 1539 1540 dprintk("%s: start %s\n", dev->net_dev.name, name); 1541 1542 start = jiffies; 1543 1544 writel(enable, dev->base + PTSCR); 1545 for (;;) { 1546 loops++; 1547 status = readl(dev->base + PTSCR); 1548 if (!(status & enable)) 1549 break; 1550 if (status & done) 1551 break; 1552 if (status & fail) 1553 break; 1554 if ((jiffies - start) >= HZ) { 1555 timed_out = 1; 1556 break; 1557 } 1558 set_current_state(TASK_UNINTERRUPTIBLE); 1559 schedule_timeout(1); 1560 } 1561 1562 if (status & fail) 1563 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n", 1564 dev->net_dev.name, name, status, fail); 1565 else if (timed_out) 1566 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n", 1567 dev->net_dev.name, name, status); 1568 1569 dprintk("%s: done %s in %d loops\n", dev->net_dev.name, name, loops); 1570} 1571 1572static void ns83820_mii_write_bit(struct ns83820 *dev, int bit) 1573{ 1574 /* drive MDC low */ 1575 dev->MEAR_cache &= ~MEAR_MDC; 1576 writel(dev->MEAR_cache, dev->base + MEAR); 1577 readl(dev->base + MEAR); 1578 1579 /* enable output, set bit */ 1580 dev->MEAR_cache |= MEAR_MDDIR; 1581 if (bit) 1582 dev->MEAR_cache |= MEAR_MDIO; 1583 else 1584 dev->MEAR_cache &= ~MEAR_MDIO; 1585 1586 /* set the output bit */ 1587 writel(dev->MEAR_cache, dev->base + MEAR); 1588 readl(dev->base + MEAR); 1589 1590 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */ 1591 udelay(1); 1592 1593 /* drive MDC high causing the data bit to be latched */ 1594 dev->MEAR_cache |= MEAR_MDC; 1595 writel(dev->MEAR_cache, dev->base + MEAR); 1596 readl(dev->base + MEAR); 1597 1598 /* Wait again... */ 1599 udelay(1); 1600} 1601 1602static int ns83820_mii_read_bit(struct ns83820 *dev) 1603{ 1604 int bit; 1605 1606 /* drive MDC low, disable output */ 1607 dev->MEAR_cache &= ~MEAR_MDC; 1608 dev->MEAR_cache &= ~MEAR_MDDIR; 1609 writel(dev->MEAR_cache, dev->base + MEAR); 1610 readl(dev->base + MEAR); 1611 1612 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */ 1613 udelay(1); 1614 1615 /* drive MDC high causing the data bit to be latched */ 1616 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0; 1617 dev->MEAR_cache |= MEAR_MDC; 1618 writel(dev->MEAR_cache, dev->base + MEAR); 1619 1620 /* Wait again... */ 1621 udelay(1); 1622 1623 return bit; 1624} 1625 1626static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg) 1627{ 1628 unsigned data = 0; 1629 int i; 1630 1631 /* read some garbage so that we eventually sync up */ 1632 for (i=0; i<64; i++) 1633 ns83820_mii_read_bit(dev); 1634 1635 ns83820_mii_write_bit(dev, 0); /* start */ 1636 ns83820_mii_write_bit(dev, 1); 1637 ns83820_mii_write_bit(dev, 1); /* opcode read */ 1638 ns83820_mii_write_bit(dev, 0); 1639 1640 /* write out the phy address: 5 bits, msb first */ 1641 for (i=0; i<5; i++) 1642 ns83820_mii_write_bit(dev, phy & (0x10 >> i)); 1643 1644 /* write out the register address, 5 bits, msb first */ 1645 for (i=0; i<5; i++) 1646 ns83820_mii_write_bit(dev, reg & (0x10 >> i)); 1647 1648 ns83820_mii_read_bit(dev); /* turn around cycles */ 1649 ns83820_mii_read_bit(dev); 1650 1651 /* read in the register data, 16 bits msb first */ 1652 for (i=0; i<16; i++) { 1653 data <<= 1; 1654 data |= ns83820_mii_read_bit(dev); 1655 } 1656 1657 return data; 1658} 1659 1660static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data) 1661{ 1662 int i; 1663 1664 /* read some garbage so that we eventually sync up */ 1665 for (i=0; i<64; i++) 1666 ns83820_mii_read_bit(dev); 1667 1668 ns83820_mii_write_bit(dev, 0); /* start */ 1669 ns83820_mii_write_bit(dev, 1); 1670 ns83820_mii_write_bit(dev, 0); /* opcode read */ 1671 ns83820_mii_write_bit(dev, 1); 1672 1673 /* write out the phy address: 5 bits, msb first */ 1674 for (i=0; i<5; i++) 1675 ns83820_mii_write_bit(dev, phy & (0x10 >> i)); 1676 1677 /* write out the register address, 5 bits, msb first */ 1678 for (i=0; i<5; i++) 1679 ns83820_mii_write_bit(dev, reg & (0x10 >> i)); 1680 1681 ns83820_mii_read_bit(dev); /* turn around cycles */ 1682 ns83820_mii_read_bit(dev); 1683 1684 /* read in the register data, 16 bits msb first */ 1685 for (i=0; i<16; i++) 1686 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1); 1687 1688 return data; 1689} 1690 1691static void ns83820_probe_phy(struct ns83820 *dev) 1692{ 1693 static int first; 1694 int i; 1695#define MII_PHYIDR1 0x02 1696#define MII_PHYIDR2 0x03 1697 1698 first = 1; 1699 1700 for (i=1; i<2; i++) { 1701 int j; 1702 unsigned a, b; 1703 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1); 1704 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2); 1705 1706 //printk("%s: phy %d: 0x%04x 0x%04x\n", 1707 // dev->net_dev.name, i, a, b); 1708 1709 for (j=0; j<0x16; j+=4) { 1710 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n", 1711 dev->net_dev.name, j, 1712 ns83820_mii_read_reg(dev, i, 0 + j), 1713 ns83820_mii_read_reg(dev, i, 1 + j), 1714 ns83820_mii_read_reg(dev, i, 2 + j), 1715 ns83820_mii_read_reg(dev, i, 3 + j) 1716 ); 1717 } 1718 } 1719 { 1720 unsigned a, b; 1721 /* read firmware version: memory addr is 0x8402 and 0x8403 */ 1722 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d); 1723 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e); 1724 a = ns83820_mii_read_reg(dev, 1, 0x1d); 1725 1726 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d); 1727 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e); 1728 b = ns83820_mii_read_reg(dev, 1, 0x1d); 1729 dprintk("version: 0x%04x 0x%04x\n", a, b); 1730 } 1731} 1732 1733static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id) 1734{ 1735 struct ns83820 *dev; 1736 long addr; 1737 int err; 1738 int using_dac = 0; 1739 1740 /* See if we can set the dma mask early on; failure is fatal. */ 1741 if (TRY_DAC && !pci_set_dma_mask(pci_dev, 0xffffffffffffffff)) { 1742 using_dac = 1; 1743 } else if (!pci_set_dma_mask(pci_dev, 0xffffffff)) { 1744 using_dac = 0; 1745 } else { 1746 printk(KERN_WARNING "ns83820.c: pci_set_dma_mask failed!\n"); 1747 return -ENODEV; 1748 } 1749 1750 dev = (struct ns83820 *)alloc_etherdev((sizeof *dev) - (sizeof dev->net_dev)); 1751 err = -ENOMEM; 1752 if (!dev) 1753 goto out; 1754 1755 spin_lock_init(&dev->rx_info.lock); 1756 spin_lock_init(&dev->tx_lock); 1757 spin_lock_init(&dev->misc_lock); 1758 dev->pci_dev = pci_dev; 1759 1760 dev->ee.cache = &dev->MEAR_cache; 1761 dev->ee.lock = &dev->misc_lock; 1762 dev->net_dev.owner = THIS_MODULE; 1763 1764 PREPARE_TQUEUE(&dev->tq_refill, queue_refill, dev); 1765 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)dev); 1766 1767 err = pci_enable_device(pci_dev); 1768 if (err) { 1769 printk(KERN_INFO "ns83820: pci_enable_dev failed: %d\n", err); 1770 goto out_free; 1771 } 1772 1773 pci_set_master(pci_dev); 1774 addr = pci_resource_start(pci_dev, 1); 1775 dev->base = ioremap_nocache(addr, PAGE_SIZE); 1776 dev->tx_descs = pci_alloc_consistent(pci_dev, 1777 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs); 1778 dev->rx_info.descs = pci_alloc_consistent(pci_dev, 1779 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs); 1780 err = -ENOMEM; 1781 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs) 1782 goto out_disable; 1783 1784 dprintk("%p: %08lx %p: %08lx\n", 1785 dev->tx_descs, (long)dev->tx_phy_descs, 1786 dev->rx_info.descs, (long)dev->rx_info.phy_descs); 1787 1788 /* disable interrupts */ 1789 writel(0, dev->base + IMR); 1790 writel(0, dev->base + IER); 1791 readl(dev->base + IER); 1792 1793 dev->IMR_cache = 0; 1794 1795 setup_ee_mem_bitbanger(&dev->ee, (long)dev->base + MEAR, 3, 2, 1, 0, 1796 0); 1797 1798 err = request_irq(pci_dev->irq, ns83820_irq, SA_SHIRQ, 1799 dev->net_dev.name, dev); 1800 if (err) { 1801 printk(KERN_INFO "ns83820: unable to register irq %d\n", 1802 pci_dev->irq); 1803 goto out_unmap; 1804 } 1805 1806 err = register_netdev(&dev->net_dev); 1807 if (err) { 1808 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err); 1809 goto out_unmap; 1810 } 1811 1812 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n", 1813 dev->net_dev.name, le32_to_cpu(readl(dev->base + 0x22c)), 1814 pci_dev->subsystem_vendor, pci_dev->subsystem_device); 1815 1816 dev->net_dev.open = ns83820_open; 1817 dev->net_dev.stop = ns83820_stop; 1818 dev->net_dev.hard_start_xmit = ns83820_hard_start_xmit; 1819 dev->net_dev.get_stats = ns83820_get_stats; 1820 dev->net_dev.change_mtu = ns83820_change_mtu; 1821 dev->net_dev.set_multicast_list = ns83820_set_multicast; 1822 dev->net_dev.do_ioctl = ns83820_ioctl; 1823 dev->net_dev.tx_timeout = ns83820_tx_timeout; 1824 dev->net_dev.watchdog_timeo = 5 * HZ; 1825 1826 pci_set_drvdata(pci_dev, dev); 1827 1828 ns83820_do_reset(dev, CR_RST); 1829 1830 /* Must reset the ram bist before running it */ 1831 writel(PTSCR_RBIST_RST, dev->base + PTSCR); 1832 ns83820_run_bist(dev, "sram bist", PTSCR_RBIST_EN, 1833 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL); 1834 ns83820_run_bist(dev, "eeprom bist", PTSCR_EEBIST_EN, 0, 1835 PTSCR_EEBIST_FAIL); 1836 ns83820_run_bist(dev, "eeprom load", PTSCR_EELOAD_EN, 0, 0); 1837 1838 /* I love config registers */ 1839 dev->CFG_cache = readl(dev->base + CFG); 1840 1841 if ((dev->CFG_cache & CFG_PCI64_DET)) { 1842 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n", 1843 dev->net_dev.name); 1844 /*dev->CFG_cache |= CFG_DATA64_EN;*/ 1845 if (!(dev->CFG_cache & CFG_DATA64_EN)) 1846 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n", 1847 dev->net_dev.name); 1848 } else 1849 dev->CFG_cache &= ~(CFG_DATA64_EN); 1850 1851 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS | 1852 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 | 1853 CFG_M64ADDR); 1854 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS | 1855 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL; 1856 dev->CFG_cache |= CFG_REQALG; 1857 dev->CFG_cache |= CFG_POW; 1858 dev->CFG_cache |= CFG_TMRTEST; 1859 1860 /* When compiled with 64 bit addressing, we must always enable 1861 * the 64 bit descriptor format. 1862 */ 1863#ifdef USE_64BIT_ADDR 1864 dev->CFG_cache |= CFG_M64ADDR; 1865#endif 1866 if (using_dac) 1867 dev->CFG_cache |= CFG_T64ADDR; 1868 1869 /* Big endian mode does not seem to do what the docs suggest */ 1870 dev->CFG_cache &= ~CFG_BEM; 1871 1872 /* setup optical transceiver if we have one */ 1873 if (dev->CFG_cache & CFG_TBI_EN) { 1874 printk(KERN_INFO "%s: enabling optical transceiver\n", 1875 dev->net_dev.name); 1876 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR); 1877 1878 /* setup auto negotiation feature advertisement */ 1879 writel(readl(dev->base + TANAR) 1880 | TANAR_HALF_DUP | TANAR_FULL_DUP, 1881 dev->base + TANAR); 1882 1883 /* start auto negotiation */ 1884 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, 1885 dev->base + TBICR); 1886 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); 1887 dev->linkstate = LINK_AUTONEGOTIATE; 1888 1889 dev->CFG_cache |= CFG_MODE_1000; 1890 } 1891 1892 writel(dev->CFG_cache, dev->base + CFG); 1893 dprintk("CFG: %08x\n", dev->CFG_cache); 1894 1895 if (reset_phy) { 1896 printk(KERN_INFO "%s: resetting phy\n", dev->net_dev.name); 1897 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG); 1898 set_current_state(TASK_UNINTERRUPTIBLE); 1899 schedule_timeout((HZ+99)/100); 1900 writel(dev->CFG_cache, dev->base + CFG); 1901 } 1902 1903 1904 /* Note! The DMA burst size interacts with packet 1905 * transmission, such that the largest packet that 1906 * can be transmitted is 8192 - FLTH - burst size. 1907 * If only the transmit fifo was larger... 1908 */ 1909 /* Ramit : 1024 DMA is not a good idea, it ends up banging 1910 * some DELL and COMPAQ SMP systems */ 1911 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512 1912 | ((1600 / 32) * 0x100), 1913 dev->base + TXCFG); 1914 1915 /* Flush the interrupt holdoff timer */ 1916 writel(0x000, dev->base + IHR); 1917 writel(0x100, dev->base + IHR); 1918 writel(0x000, dev->base + IHR); 1919 1920 /* Set Rx to full duplex, don't accept runt, errored, long or length 1921 * range errored packets. Use 512 byte DMA. 1922 */ 1923 /* Ramit : 1024 DMA is not a good idea, it ends up banging 1924 * some DELL and COMPAQ SMP systems 1925 * Turn on ALP, only we are accpeting Jumbo Packets */ 1926 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD 1927 | RXCFG_STRIPCRC 1928 //| RXCFG_ALP 1929 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG); 1930 1931 /* Disable priority queueing */ 1932 writel(0, dev->base + PQCR); 1933 1934 /* Enable IP checksum validation and detetion of VLAN headers. 1935 * Note: do not set the reject options as at least the 0x102 1936 * revision of the chip does not properly accept IP fragments 1937 * at least for UDP. 1938 */ 1939 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since 1940 * the MAC it calculates the packetsize AFTER stripping the VLAN 1941 * header, and if a VLAN Tagged packet of 64 bytes is received (like 1942 * a ping with a VLAN header) then the card, strips the 4 byte VLAN 1943 * tag and then checks the packet size, so if RXCFG_ARP is not enabled, 1944 * it discrards it!. These guys...... 1945 */ 1946 writel(VRCR_IPEN | VRCR_VTDEN, dev->base + VRCR); 1947 1948 /* Enable per-packet TCP/UDP/IP checksumming */ 1949 writel(VTCR_PPCHK, dev->base + VTCR); 1950 1951 /* Ramit : Enable async and sync pause frames */ 1952 /* writel(0, dev->base + PCR); */ 1953 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K | 1954 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT), 1955 dev->base + PCR); 1956 1957 /* Disable Wake On Lan */ 1958 writel(0, dev->base + WCSR); 1959 1960 ns83820_getmac(dev, dev->net_dev.dev_addr); 1961 1962 /* Yes, we support dumb IP checksum on transmit */ 1963 dev->net_dev.features |= NETIF_F_SG; 1964 dev->net_dev.features |= NETIF_F_IP_CSUM; 1965 1966 if (using_dac) { 1967 printk(KERN_INFO "%s: using 64 bit addressing.\n", 1968 dev->net_dev.name); 1969 dev->net_dev.features |= NETIF_F_HIGHDMA; 1970 } 1971 1972 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n", 1973 dev->net_dev.name, 1974 (unsigned)readl(dev->base + SRR) >> 8, 1975 (unsigned)readl(dev->base + SRR) & 0xff, 1976 dev->net_dev.dev_addr[0], dev->net_dev.dev_addr[1], 1977 dev->net_dev.dev_addr[2], dev->net_dev.dev_addr[3], 1978 dev->net_dev.dev_addr[4], dev->net_dev.dev_addr[5], 1979 addr, pci_dev->irq, 1980 (dev->net_dev.features & NETIF_F_HIGHDMA) ? "h,sg" : "sg" 1981 ); 1982 1983#ifdef PHY_CODE_IS_FINISHED 1984 ns83820_probe_phy(dev); 1985#endif 1986 1987 return 0; 1988 1989out_unmap: 1990 iounmap(dev->base); 1991out_disable: 1992 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs); 1993 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs); 1994 pci_disable_device(pci_dev); 1995out_free: 1996 kfree(dev); 1997 pci_set_drvdata(pci_dev, NULL); 1998out: 1999 return err; 2000} 2001 2002static void __devexit ns83820_remove_one(struct pci_dev *pci_dev) 2003{ 2004 struct ns83820 *dev = pci_get_drvdata(pci_dev); 2005 2006 if (!dev) /* paranoia */ 2007 return; 2008 2009 writel(0, dev->base + IMR); /* paranoia */ 2010 writel(0, dev->base + IER); 2011 readl(dev->base + IER); 2012 2013 unregister_netdev(&dev->net_dev); 2014 free_irq(dev->pci_dev->irq, dev); 2015 iounmap(dev->base); 2016 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC, 2017 dev->tx_descs, dev->tx_phy_descs); 2018 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC, 2019 dev->rx_info.descs, dev->rx_info.phy_descs); 2020 pci_disable_device(dev->pci_dev); 2021 kfree(dev); 2022 pci_set_drvdata(pci_dev, NULL); 2023} 2024 2025static struct pci_device_id ns83820_pci_tbl[] __devinitdata = { 2026 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, }, 2027 { 0, }, 2028}; 2029 2030static struct pci_driver driver = { 2031 name: "ns83820", 2032 id_table: ns83820_pci_tbl, 2033 probe: ns83820_init_one, 2034 remove: __devexit_p(ns83820_remove_one), 2035}; 2036 2037 2038static int __init ns83820_init(void) 2039{ 2040 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n"); 2041 return pci_module_init(&driver); 2042} 2043 2044static void __exit ns83820_exit(void) 2045{ 2046 pci_unregister_driver(&driver); 2047} 2048 2049MODULE_AUTHOR("Benjamin LaHaise <bcrl@redhat.com>"); 2050MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver"); 2051MODULE_LICENSE("GPL"); 2052 2053MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl); 2054 2055MODULE_PARM(lnksts, "i"); 2056MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit"); 2057 2058MODULE_PARM(ihr, "i"); 2059MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)"); 2060 2061MODULE_PARM(reset_phy, "i"); 2062MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup"); 2063 2064module_init(ns83820_init); 2065module_exit(ns83820_exit); 2066