1#include <linux/config.h>
2
3#define PCILYNX_DRIVER_NAME      "pcilynx"
4#define PCILYNX_MAJOR            177
5
6#define PCILYNX_MINOR_AUX_START  0
7#define PCILYNX_MINOR_ROM_START  16
8#define PCILYNX_MINOR_RAM_START  32
9
10#define PCILYNX_MAX_REGISTER     0xfff
11#define PCILYNX_MAX_MEMORY       0xffff
12
13#define PCI_DEVICE_ID_TI_PCILYNX 0x8000
14#define MAX_PCILYNX_CARDS        4
15#define LOCALRAM_SIZE            4096
16
17#define NUM_ISORCV_PCL           4
18#define MAX_ISORCV_SIZE          2048
19#define ISORCV_PER_PAGE          (PAGE_SIZE / MAX_ISORCV_SIZE)
20#define ISORCV_PAGES             (NUM_ISORCV_PCL / ISORCV_PER_PAGE)
21
22#define CHANNEL_LOCALBUS         0
23#define CHANNEL_ASYNC_RCV        1
24#define CHANNEL_ISO_RCV          2
25#define CHANNEL_ASYNC_SEND       3
26#define CHANNEL_ISO_SEND         4
27
28#define PCILYNX_CONFIG_ROM_LENGTH   1024
29
30typedef int pcl_t;
31
32struct ti_lynx {
33        int id; /* sequential card number */
34
35        spinlock_t lock;
36
37        struct pci_dev *dev;
38
39        struct {
40                unsigned reg_1394a:1;
41                u32 vendor;
42                u32 product;
43        } phyic;
44
45        enum { clear, have_intr, have_aux_buf, have_pcl_mem,
46               have_1394_buffers, have_iomappings, is_host } state;
47
48        /* remapped memory spaces */
49        void *registers;
50        void *local_rom;
51        void *local_ram;
52        void *aux_port;
53        quadlet_t config_rom[PCILYNX_CONFIG_ROM_LENGTH/4];
54
55#ifdef CONFIG_IEEE1394_PCILYNX_PORTS
56        atomic_t aux_intr_seen;
57        wait_queue_head_t aux_intr_wait;
58
59        void *mem_dma_buffer;
60        dma_addr_t mem_dma_buffer_dma;
61        struct semaphore mem_dma_mutex;
62        wait_queue_head_t mem_dma_intr_wait;
63#endif
64
65        /*
66         * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
67         * LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
68         * the following is an allocation bitmap
69         */
70        u8 pcl_bmap[LOCALRAM_SIZE / 1024];
71
72#ifndef CONFIG_IEEE1394_PCILYNX_LOCALRAM
73	/* point to PCLs memory area if needed */
74	void *pcl_mem;
75        dma_addr_t pcl_mem_dma;
76#endif
77
78        /* PCLs for local mem / aux transfers */
79        pcl_t dmem_pcl;
80
81        /* IEEE-1394 part follows */
82        struct hpsb_host *host;
83
84        int phyid, isroot;
85        int selfid_size;
86        int phy_reg0;
87
88        spinlock_t phy_reg_lock;
89
90        pcl_t rcv_pcl_start, rcv_pcl;
91        void *rcv_page;
92        dma_addr_t rcv_page_dma;
93        int rcv_active;
94
95        struct lynx_send_data {
96                pcl_t pcl_start, pcl;
97                struct list_head queue;
98                spinlock_t queue_lock;
99                dma_addr_t header_dma, data_dma;
100                int channel;
101        } async, iso_send;
102
103        struct {
104                pcl_t pcl[NUM_ISORCV_PCL];
105                u32 stat[NUM_ISORCV_PCL];
106                void *page[ISORCV_PAGES];
107                dma_addr_t page_dma[ISORCV_PAGES];
108                pcl_t pcl_start;
109                int chan_count;
110                int next, last, used, running;
111                struct tasklet_struct tq;
112                spinlock_t lock;
113        } iso_rcv;
114
115	u32 i2c_driven_state; /* the state we currently drive the Serial EEPROM Control register */
116};
117
118/* the per-file data structure for mem space access */
119struct memdata {
120        struct ti_lynx *lynx;
121        int cid;
122        atomic_t aux_intr_last_seen;
123	/* enum values are the same as LBUS_ADDR_SEL_* values below */
124        enum { rom = 0x10000, aux = 0x20000, ram = 0 } type;
125};
126
127
128
129/*
130 * Register read and write helper functions.
131 */
132static inline void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
133{
134        writel(data, lynx->registers + offset);
135}
136
137static inline u32 reg_read(const struct ti_lynx *lynx, int offset)
138{
139        return readl(lynx->registers + offset);
140}
141
142static inline void reg_set_bits(const struct ti_lynx *lynx, int offset,
143                                u32 mask)
144{
145        reg_write(lynx, offset, (reg_read(lynx, offset) | mask));
146}
147
148static inline void reg_clear_bits(const struct ti_lynx *lynx, int offset,
149                                  u32 mask)
150{
151        reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
152}
153
154
155
156/* chip register definitions follow */
157
158#define PCI_LATENCY_CACHELINE             0x0c
159
160#define MISC_CONTROL                      0x40
161#define MISC_CONTROL_SWRESET              (1<<0)
162
163#define SERIAL_EEPROM_CONTROL             0x44
164
165#define PCI_INT_STATUS                    0x48
166#define PCI_INT_ENABLE                    0x4c
167/* status and enable have identical bit numbers */
168#define PCI_INT_INT_PEND                  (1<<31)
169#define PCI_INT_FORCED_INT                (1<<30)
170#define PCI_INT_SLV_ADR_PERR              (1<<28)
171#define PCI_INT_SLV_DAT_PERR              (1<<27)
172#define PCI_INT_MST_DAT_PERR              (1<<26)
173#define PCI_INT_MST_DEV_TIMEOUT           (1<<25)
174#define PCI_INT_INTERNAL_SLV_TIMEOUT      (1<<23)
175#define PCI_INT_AUX_TIMEOUT               (1<<18)
176#define PCI_INT_AUX_INT                   (1<<17)
177#define PCI_INT_1394                      (1<<16)
178#define PCI_INT_DMA4_PCL                  (1<<9)
179#define PCI_INT_DMA4_HLT                  (1<<8)
180#define PCI_INT_DMA3_PCL                  (1<<7)
181#define PCI_INT_DMA3_HLT                  (1<<6)
182#define PCI_INT_DMA2_PCL                  (1<<5)
183#define PCI_INT_DMA2_HLT                  (1<<4)
184#define PCI_INT_DMA1_PCL                  (1<<3)
185#define PCI_INT_DMA1_HLT                  (1<<2)
186#define PCI_INT_DMA0_PCL                  (1<<1)
187#define PCI_INT_DMA0_HLT                  (1<<0)
188/* all DMA interrupts combined: */
189#define PCI_INT_DMA_ALL                   0x3ff
190
191#define PCI_INT_DMA_HLT(chan)             (1 << (chan * 2))
192#define PCI_INT_DMA_PCL(chan)             (1 << (chan * 2 + 1))
193
194#define LBUS_ADDR                         0xb4
195#define LBUS_ADDR_SEL_RAM                 (0x0<<16)
196#define LBUS_ADDR_SEL_ROM                 (0x1<<16)
197#define LBUS_ADDR_SEL_AUX                 (0x2<<16)
198#define LBUS_ADDR_SEL_ZV                  (0x3<<16)
199
200#define GPIO_CTRL_A                       0xb8
201#define GPIO_CTRL_B                       0xbc
202#define GPIO_DATA_BASE                    0xc0
203
204#define DMA_BREG(base, chan)              (base + chan * 0x20)
205#define DMA_SREG(base, chan)              (base + chan * 0x10)
206
207#define DMA0_PREV_PCL                     0x100
208#define DMA1_PREV_PCL                     0x120
209#define DMA2_PREV_PCL                     0x140
210#define DMA3_PREV_PCL                     0x160
211#define DMA4_PREV_PCL                     0x180
212#define DMA_PREV_PCL(chan)                (DMA_BREG(DMA0_PREV_PCL, chan))
213
214#define DMA0_CURRENT_PCL                  0x104
215#define DMA1_CURRENT_PCL                  0x124
216#define DMA2_CURRENT_PCL                  0x144
217#define DMA3_CURRENT_PCL                  0x164
218#define DMA4_CURRENT_PCL                  0x184
219#define DMA_CURRENT_PCL(chan)             (DMA_BREG(DMA0_CURRENT_PCL, chan))
220
221#define DMA0_CHAN_STAT                    0x10c
222#define DMA1_CHAN_STAT                    0x12c
223#define DMA2_CHAN_STAT                    0x14c
224#define DMA3_CHAN_STAT                    0x16c
225#define DMA4_CHAN_STAT                    0x18c
226#define DMA_CHAN_STAT(chan)               (DMA_BREG(DMA0_CHAN_STAT, chan))
227/* CHAN_STATUS registers share bits */
228#define DMA_CHAN_STAT_SELFID              (1<<31)
229#define DMA_CHAN_STAT_ISOPKT              (1<<30)
230#define DMA_CHAN_STAT_PCIERR              (1<<29)
231#define DMA_CHAN_STAT_PKTERR              (1<<28)
232#define DMA_CHAN_STAT_PKTCMPL             (1<<27)
233#define DMA_CHAN_STAT_SPECIALACK          (1<<14)
234
235
236#define DMA0_CHAN_CTRL                    0x110
237#define DMA1_CHAN_CTRL                    0x130
238#define DMA2_CHAN_CTRL                    0x150
239#define DMA3_CHAN_CTRL                    0x170
240#define DMA4_CHAN_CTRL                    0x190
241#define DMA_CHAN_CTRL(chan)               (DMA_BREG(DMA0_CHAN_CTRL, chan))
242/* CHAN_CTRL registers share bits */
243#define DMA_CHAN_CTRL_ENABLE              (1<<31)
244#define DMA_CHAN_CTRL_BUSY                (1<<30)
245#define DMA_CHAN_CTRL_LINK                (1<<29)
246
247#define DMA0_READY                        0x114
248#define DMA1_READY                        0x134
249#define DMA2_READY                        0x154
250#define DMA3_READY                        0x174
251#define DMA4_READY                        0x194
252#define DMA_READY(chan)                   (DMA_BREG(DMA0_READY, chan))
253
254#define DMA_GLOBAL_REGISTER               0x908
255
256#define FIFO_SIZES                        0xa00
257
258#define FIFO_CONTROL                      0xa10
259#define FIFO_CONTROL_GRF_FLUSH            (1<<4)
260#define FIFO_CONTROL_ITF_FLUSH            (1<<3)
261#define FIFO_CONTROL_ATF_FLUSH            (1<<2)
262
263#define FIFO_XMIT_THRESHOLD               0xa14
264
265#define DMA0_WORD0_CMP_VALUE              0xb00
266#define DMA1_WORD0_CMP_VALUE              0xb10
267#define DMA2_WORD0_CMP_VALUE              0xb20
268#define DMA3_WORD0_CMP_VALUE              0xb30
269#define DMA4_WORD0_CMP_VALUE              0xb40
270#define DMA_WORD0_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
271
272#define DMA0_WORD0_CMP_ENABLE             0xb04
273#define DMA1_WORD0_CMP_ENABLE             0xb14
274#define DMA2_WORD0_CMP_ENABLE             0xb24
275#define DMA3_WORD0_CMP_ENABLE             0xb34
276#define DMA4_WORD0_CMP_ENABLE             0xb44
277#define DMA_WORD0_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan))
278
279#define DMA0_WORD1_CMP_VALUE              0xb08
280#define DMA1_WORD1_CMP_VALUE              0xb18
281#define DMA2_WORD1_CMP_VALUE              0xb28
282#define DMA3_WORD1_CMP_VALUE              0xb38
283#define DMA4_WORD1_CMP_VALUE              0xb48
284#define DMA_WORD1_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
285
286#define DMA0_WORD1_CMP_ENABLE             0xb0c
287#define DMA1_WORD1_CMP_ENABLE             0xb1c
288#define DMA2_WORD1_CMP_ENABLE             0xb2c
289#define DMA3_WORD1_CMP_ENABLE             0xb3c
290#define DMA4_WORD1_CMP_ENABLE             0xb4c
291#define DMA_WORD1_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan))
292/* word 1 compare enable flags */
293#define DMA_WORD1_CMP_MATCH_OTHERBUS      (1<<15)
294#define DMA_WORD1_CMP_MATCH_BROADCAST     (1<<14)
295#define DMA_WORD1_CMP_MATCH_BUS_BCAST     (1<<13)
296#define DMA_WORD1_CMP_MATCH_LOCAL_NODE    (1<<12)
297#define DMA_WORD1_CMP_MATCH_EXACT         (1<<11)
298#define DMA_WORD1_CMP_ENABLE_SELF_ID      (1<<10)
299#define DMA_WORD1_CMP_ENABLE_MASTER       (1<<8)
300
301#define LINK_ID                           0xf00
302#define LINK_ID_BUS(id)                   (id<<22)
303#define LINK_ID_NODE(id)                  (id<<16)
304
305#define LINK_CONTROL                      0xf04
306#define LINK_CONTROL_BUSY                 (1<<29)
307#define LINK_CONTROL_TX_ISO_EN            (1<<26)
308#define LINK_CONTROL_RX_ISO_EN            (1<<25)
309#define LINK_CONTROL_TX_ASYNC_EN          (1<<24)
310#define LINK_CONTROL_RX_ASYNC_EN          (1<<23)
311#define LINK_CONTROL_RESET_TX             (1<<21)
312#define LINK_CONTROL_RESET_RX             (1<<20)
313#define LINK_CONTROL_CYCMASTER            (1<<11)
314#define LINK_CONTROL_CYCSOURCE            (1<<10)
315#define LINK_CONTROL_CYCTIMEREN           (1<<9)
316#define LINK_CONTROL_RCV_CMP_VALID        (1<<7)
317#define LINK_CONTROL_SNOOP_ENABLE         (1<<6)
318
319#define CYCLE_TIMER                       0xf08
320
321#define LINK_PHY                          0xf0c
322#define LINK_PHY_READ                     (1<<31)
323#define LINK_PHY_WRITE                    (1<<30)
324#define LINK_PHY_ADDR(addr)               (addr<<24)
325#define LINK_PHY_WDATA(data)              (data<<16)
326#define LINK_PHY_RADDR(addr)              (addr<<8)
327
328
329#define LINK_INT_STATUS                   0xf14
330#define LINK_INT_ENABLE                   0xf18
331/* status and enable have identical bit numbers */
332#define LINK_INT_LINK_INT                 (1<<31)
333#define LINK_INT_PHY_TIMEOUT              (1<<30)
334#define LINK_INT_PHY_REG_RCVD             (1<<29)
335#define LINK_INT_PHY_BUSRESET             (1<<28)
336#define LINK_INT_TX_RDY                   (1<<26)
337#define LINK_INT_RX_DATA_RDY              (1<<25)
338#define LINK_INT_ISO_STUCK                (1<<20)
339#define LINK_INT_ASYNC_STUCK              (1<<19)
340#define LINK_INT_SENT_REJECT              (1<<17)
341#define LINK_INT_HDR_ERR                  (1<<16)
342#define LINK_INT_TX_INVALID_TC            (1<<15)
343#define LINK_INT_CYC_SECOND               (1<<11)
344#define LINK_INT_CYC_START                (1<<10)
345#define LINK_INT_CYC_DONE                 (1<<9)
346#define LINK_INT_CYC_PENDING              (1<<8)
347#define LINK_INT_CYC_LOST                 (1<<7)
348#define LINK_INT_CYC_ARB_FAILED           (1<<6)
349#define LINK_INT_GRF_OVERFLOW             (1<<5)
350#define LINK_INT_ITF_UNDERFLOW            (1<<4)
351#define LINK_INT_ATF_UNDERFLOW            (1<<3)
352#define LINK_INT_ISOARB_FAILED            (1<<0)
353
354/* PHY specifics */
355#define PHY_VENDORID_TI                 0x800028
356#define PHY_PRODUCTID_TSB41LV03         0x000000
357
358
359/* this is the physical layout of a PCL, its size is 128 bytes */
360struct ti_pcl {
361        u32 next;
362        u32 async_error_next;
363        u32 user_data;
364        u32 pcl_status;
365        u32 remaining_transfer_count;
366        u32 next_data_buffer;
367        struct {
368                u32 control;
369                u32 pointer;
370        } buffer[13] __attribute__ ((packed));
371} __attribute__ ((packed));
372
373#include <linux/stddef.h>
374#define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))
375
376
377#ifdef CONFIG_IEEE1394_PCILYNX_LOCALRAM
378
379static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
380                           const struct ti_pcl *pcl)
381{
382        int i;
383        u32 *in = (u32 *)pcl;
384        u32 *out = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
385
386        for (i = 0; i < 32; i++, out++, in++) {
387                writel(*in, out);
388        }
389}
390
391static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
392                           struct ti_pcl *pcl)
393{
394        int i;
395        u32 *out = (u32 *)pcl;
396        u32 *in = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
397
398        for (i = 0; i < 32; i++, out++, in++) {
399                *out = readl(in);
400        }
401}
402
403static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
404{
405        return pci_resource_start(lynx->dev, 1) + pclid * sizeof(struct ti_pcl);
406}
407
408#else /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
409
410static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
411                           const struct ti_pcl *pcl)
412{
413        memcpy_le32((u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
414                    (u32 *)pcl, sizeof(struct ti_pcl));
415}
416
417static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
418                           struct ti_pcl *pcl)
419{
420        memcpy_le32((u32 *)pcl,
421                    (u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
422                    sizeof(struct ti_pcl));
423}
424
425static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
426{
427        return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
428}
429
430#endif /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
431
432
433#if defined(CONFIG_IEEE1394_PCILYNX_LOCALRAM) || defined(__BIG_ENDIAN)
434typedef struct ti_pcl pcltmp_t;
435
436static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
437                                      pcltmp_t *tmp)
438{
439        get_pcl(lynx, pclid, tmp);
440        return tmp;
441}
442
443static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
444                              pcltmp_t *tmp)
445{
446        put_pcl(lynx, pclid, tmp);
447}
448
449#else
450typedef int pcltmp_t; /* just a dummy */
451
452static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
453                                      pcltmp_t *tmp)
454{
455        return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
456}
457
458static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
459                              pcltmp_t *tmp)
460{
461}
462#endif
463
464
465static inline void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
466                               int dmachan)
467{
468        reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
469                  pcl_bus(lynx, pclid) + idx * 4);
470        reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
471                  DMA_CHAN_CTRL_ENABLE | DMA_CHAN_CTRL_LINK);
472}
473
474static inline void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
475{
476        run_sub_pcl(lynx, pclid, 0, dmachan);
477}
478
479#define PCL_NEXT_INVALID (1<<0)
480
481/* transfer commands */
482#define PCL_CMD_RCV            (0x1<<24)
483#define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
484#define PCL_CMD_XMT            (0x2<<24)
485#define PCL_CMD_UNFXMT         (0xc<<24)
486#define PCL_CMD_PCI_TO_LBUS    (0x8<<24)
487#define PCL_CMD_LBUS_TO_PCI    (0x9<<24)
488
489/* aux commands */
490#define PCL_CMD_NOP            (0x0<<24)
491#define PCL_CMD_LOAD           (0x3<<24)
492#define PCL_CMD_STOREQ         (0x4<<24)
493#define PCL_CMD_STORED         (0xb<<24)
494#define PCL_CMD_STORE0         (0x5<<24)
495#define PCL_CMD_STORE1         (0x6<<24)
496#define PCL_CMD_COMPARE        (0xe<<24)
497#define PCL_CMD_SWAP_COMPARE   (0xf<<24)
498#define PCL_CMD_ADD            (0xd<<24)
499#define PCL_CMD_BRANCH         (0x7<<24)
500
501/* BRANCH condition codes */
502#define PCL_COND_DMARDY_SET    (0x1<<20)
503#define PCL_COND_DMARDY_CLEAR  (0x2<<20)
504
505#define PCL_GEN_INTR           (1<<19)
506#define PCL_LAST_BUFF          (1<<18)
507#define PCL_LAST_CMD           (PCL_LAST_BUFF)
508#define PCL_WAITSTAT           (1<<17)
509#define PCL_BIGENDIAN          (1<<16)
510#define PCL_ISOMODE            (1<<12)
511
512
513#define _(x) (__constant_cpu_to_be32(x))
514
515static quadlet_t lynx_csr_rom[] = {
516/* bus info block     offset (hex) */
517        _(0x04040000), /* info/CRC length, CRC              400  */
518        _(0x31333934), /* 1394 magic number                 404  */
519        _(0xf064a000), /* misc. settings                    408  */
520        _(0x08002850), /* vendor ID, chip ID high           40c  */
521        _(0x0000ffff), /* chip ID low                       410  */
522/* root directory */
523        _(0x00090000), /* directory length, CRC             414  */
524        _(0x03080028), /* vendor ID (Texas Instr.)          418  */
525        _(0x81000008), /* offset to textual ID              41c  */
526        _(0x0c000200), /* node capabilities                 420  */
527        _(0x8d00000e), /* offset to unique ID               424  */
528        _(0xc7000010), /* offset to module independent info 428  */
529        _(0x04000000), /* module hardware version           42c  */
530        _(0x81000014), /* offset to textual ID              430  */
531        _(0x09000000), /* node hardware version             434  */
532        _(0x81000018), /* offset to textual ID              438  */
533  /* module vendor ID textual */
534        _(0x00070000), /* CRC length, CRC                   43c  */
535        _(0x00000000), /*                                   440  */
536        _(0x00000000), /*                                   444  */
537        _(0x54455841), /* "Texas Instruments"               448  */
538        _(0x5320494e), /*                                   44c  */
539        _(0x53545255), /*                                   450  */
540        _(0x4d454e54), /*                                   454  */
541        _(0x53000000), /*                                   458  */
542/* node unique ID leaf */
543        _(0x00020000), /* CRC length, CRC                   45c  */
544        _(0x08002850), /* vendor ID, chip ID high           460  */
545        _(0x0000ffff), /* chip ID low                       464  */
546/* module dependent info */
547        _(0x00050000), /* CRC length, CRC                   468  */
548        _(0x81000012), /* offset to module textual ID       46c  */
549        _(0x81000017), /* textual descriptor                470  */
550        _(0x39010000), /* SRAM size                         474  */
551        _(0x3a010000), /* AUXRAM size                       478  */
552        _(0x3b000000), /* AUX device                        47c  */
553/* module textual ID */
554        _(0x00050000), /* CRC length, CRC                   480  */
555        _(0x00000000), /*                                   484  */
556        _(0x00000000), /*                                   488  */
557        _(0x54534231), /* "TSB12LV21"                       48c  */
558        _(0x324c5632), /*                                   490  */
559        _(0x31000000), /*                                   494  */
560/* part number */
561        _(0x00060000), /* CRC length, CRC                   498  */
562        _(0x00000000), /*                                   49c  */
563        _(0x00000000), /*                                   4a0  */
564        _(0x39383036), /* "9806000-0001"                    4a4  */
565        _(0x3030302d), /*                                   4a8  */
566        _(0x30303031), /*                                   4ac  */
567        _(0x20000001), /*                                   4b0  */
568/* module hardware version textual */
569        _(0x00050000), /* CRC length, CRC                   4b4  */
570        _(0x00000000), /*                                   4b8  */
571        _(0x00000000), /*                                   4bc  */
572        _(0x5453424b), /* "TSBKPCITST"                      4c0  */
573        _(0x50434954), /*                                   4c4  */
574        _(0x53540000), /*                                   4c8  */
575/* node hardware version textual */
576        _(0x00050000), /* CRC length, CRC                   4d0  */
577        _(0x00000000), /*                                   4d4  */
578        _(0x00000000), /*                                   4d8  */
579        _(0x54534232), /* "TSB21LV03"                       4dc  */
580        _(0x314c5630), /*                                   4e0  */
581        _(0x33000000)  /*                                   4e4  */
582};
583
584#undef _
585