1/* 2 * ohci1394.h - driver for OHCI 1394 boards 3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au> 4 * Gord Peters <GordPeters@smarttech.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21#ifndef _OHCI1394_H 22#define _OHCI1394_H 23 24#include <asm/io.h> 25 26#include "ieee1394_types.h" 27#include <asm/io.h> 28 29#define OHCI1394_DRIVER_NAME "ohci1394" 30 31#define OHCI1394_MAX_AT_REQ_RETRIES 0x2 32#define OHCI1394_MAX_AT_RESP_RETRIES 0x2 33#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8 34#define OHCI1394_MAX_SELF_ID_ERRORS 16 35 36#define AR_REQ_NUM_DESC 4 /* number of AR req descriptors */ 37#define AR_REQ_BUF_SIZE PAGE_SIZE /* size of AR req buffers */ 38#define AR_REQ_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */ 39 40#define AR_RESP_NUM_DESC 4 /* number of AR resp descriptors */ 41#define AR_RESP_BUF_SIZE PAGE_SIZE /* size of AR resp buffers */ 42#define AR_RESP_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */ 43 44#define IR_NUM_DESC 16 /* number of IR descriptors */ 45#define IR_BUF_SIZE PAGE_SIZE /* 4096 bytes/buffer */ 46#define IR_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */ 47 48#define IT_NUM_DESC 16 /* number of IT descriptors */ 49 50#define AT_REQ_NUM_DESC 32 /* number of AT req descriptors */ 51#define AT_RESP_NUM_DESC 32 /* number of AT resp descriptors */ 52 53#define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */ 54 55#define OHCI_CONFIG_ROM_LEN 1024 /* Length of the mapped configrom space */ 56 57#define OHCI1394_SI_DMA_BUF_SIZE 8192 /* length of the selfid buffer */ 58 59/* PCI configuration space addresses */ 60#define OHCI1394_PCI_HCI_Control 0x40 61 62struct dma_cmd { 63 u32 control; 64 u32 address; 65 u32 branchAddress; 66 u32 status; 67}; 68 69struct at_dma_prg { 70 struct dma_cmd begin; 71 quadlet_t data[4]; 72 struct dma_cmd end; 73 quadlet_t pad[4]; 74}; 75 76/* identify whether a DMA context is asynchronous or isochronous */ 77enum context_type { DMA_CTX_ASYNC_REQ, DMA_CTX_ASYNC_RESP, DMA_CTX_ISO }; 78 79/* DMA receive context */ 80struct dma_rcv_ctx { 81 struct ti_ohci *ohci; 82 enum context_type type; 83 int ctx; 84 unsigned int num_desc; 85 86 unsigned int buf_size; 87 unsigned int split_buf_size; 88 89 /* dma block descriptors */ 90 struct dma_cmd **prg_cpu; 91 dma_addr_t *prg_bus; 92 93 /* dma buffers */ 94 quadlet_t **buf_cpu; 95 dma_addr_t *buf_bus; 96 97 unsigned int buf_ind; 98 unsigned int buf_offset; 99 quadlet_t *spb; 100 spinlock_t lock; 101 struct tasklet_struct task; 102 int ctrlClear; 103 int ctrlSet; 104 int cmdPtr; 105}; 106 107/* DMA transmit context */ 108struct dma_trm_ctx { 109 struct ti_ohci *ohci; 110 enum context_type type; 111 int ctx; 112 unsigned int num_desc; 113 114 /* dma block descriptors */ 115 struct at_dma_prg **prg_cpu; 116 dma_addr_t *prg_bus; 117 118 unsigned int prg_ind; 119 unsigned int sent_ind; 120 int free_prgs; 121 quadlet_t *branchAddrPtr; 122 123 /* list of packets inserted in the AT FIFO */ 124 struct list_head fifo_list; 125 126 /* list of pending packets to be inserted in the AT FIFO */ 127 struct list_head pending_list; 128 129 spinlock_t lock; 130 struct tasklet_struct task; 131 int ctrlClear; 132 int ctrlSet; 133 int cmdPtr; 134}; 135 136struct ohci1394_iso_tasklet { 137 struct tasklet_struct tasklet; 138 struct list_head link; 139 int context; 140 enum { OHCI_ISO_TRANSMIT, OHCI_ISO_RECEIVE } type; 141}; 142 143struct ti_ohci { 144 int id; /* sequential card number */ 145 146 struct pci_dev *dev; 147 148 enum { 149 OHCI_INIT_ALLOC_HOST, 150 OHCI_INIT_HAVE_MEM_REGION, 151 OHCI_INIT_HAVE_IOMAPPING, 152 OHCI_INIT_HAVE_CONFIG_ROM_BUFFER, 153 OHCI_INIT_HAVE_SELFID_BUFFER, 154 OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE, 155 OHCI_INIT_HAVE_IRQ, 156 OHCI_INIT_DONE, 157 } init_state; 158 159 /* remapped memory spaces */ 160 void *registers; 161 162 /* dma buffer for self-id packets */ 163 quadlet_t *selfid_buf_cpu; 164 dma_addr_t selfid_buf_bus; 165 166 /* buffer for csr config rom */ 167 quadlet_t *csr_config_rom_cpu; 168 dma_addr_t csr_config_rom_bus; 169 int csr_config_rom_length; 170 171 unsigned int max_packet_size; 172 173 /* async receive */ 174 struct dma_rcv_ctx ar_resp_context; 175 struct dma_rcv_ctx ar_req_context; 176 177 /* async transmit */ 178 struct dma_trm_ctx at_resp_context; 179 struct dma_trm_ctx at_req_context; 180 181 /* iso receive */ 182 struct dma_rcv_ctx ir_context; 183 struct ohci1394_iso_tasklet ir_tasklet; 184 spinlock_t IR_channel_lock; 185 int nb_iso_rcv_ctx; 186 unsigned long ir_ctx_usage; /* use test_and_set_bit() for atomicity */ 187 188 /* iso transmit */ 189 struct dma_trm_ctx it_context; 190 struct ohci1394_iso_tasklet it_tasklet; 191 int nb_iso_xmit_ctx; 192 unsigned long it_ctx_usage; /* use test_and_set_bit() for atomicity */ 193 194 u64 ISO_channel_usage; 195 196 /* IEEE-1394 part follows */ 197 struct hpsb_host *host; 198 199 int phyid, isroot; 200 201 spinlock_t phy_reg_lock; 202 spinlock_t event_lock; 203 204 int self_id_errors; 205 206 /* Tasklets for iso receive and transmit, used by video1394, 207 * amdtp and dv1394 */ 208 209 struct list_head iso_tasklet_list; 210 spinlock_t iso_tasklet_list_lock; 211 212 /* Swap the selfid buffer? */ 213 unsigned int selfid_swap:1; 214 /* Some Apple chipset seem to swap incoming headers for us */ 215 unsigned int no_swap_incoming:1; 216}; 217 218static inline int cross_bound(unsigned long addr, unsigned int size) 219{ 220 int cross=0; 221 if (size>PAGE_SIZE) { 222 cross = size/PAGE_SIZE; 223 size -= cross*PAGE_SIZE; 224 } 225 if ((PAGE_SIZE-addr%PAGE_SIZE)<size) 226 cross++; 227 return cross; 228} 229 230/* 231 * Register read and write helper functions. 232 */ 233static inline void reg_write(const struct ti_ohci *ohci, int offset, u32 data) 234{ 235 writel(data, ohci->registers + offset); 236} 237 238static inline u32 reg_read(const struct ti_ohci *ohci, int offset) 239{ 240 return readl(ohci->registers + offset); 241} 242 243 244/* 2 KiloBytes of register space */ 245#define OHCI1394_REGISTER_SIZE 0x800 246 247/* Offsets relative to context bases defined below */ 248 249#define OHCI1394_ContextControlSet 0x000 250#define OHCI1394_ContextControlClear 0x004 251#define OHCI1394_ContextCommandPtr 0x00C 252 253/* register map */ 254#define OHCI1394_Version 0x000 255#define OHCI1394_GUID_ROM 0x004 256#define OHCI1394_ATRetries 0x008 257#define OHCI1394_CSRData 0x00C 258#define OHCI1394_CSRCompareData 0x010 259#define OHCI1394_CSRControl 0x014 260#define OHCI1394_ConfigROMhdr 0x018 261#define OHCI1394_BusID 0x01C 262#define OHCI1394_BusOptions 0x020 263#define OHCI1394_GUIDHi 0x024 264#define OHCI1394_GUIDLo 0x028 265#define OHCI1394_ConfigROMmap 0x034 266#define OHCI1394_PostedWriteAddressLo 0x038 267#define OHCI1394_PostedWriteAddressHi 0x03C 268#define OHCI1394_VendorID 0x040 269#define OHCI1394_HCControlSet 0x050 270#define OHCI1394_HCControlClear 0x054 271#define OHCI1394_SelfIDBuffer 0x064 272#define OHCI1394_SelfIDCount 0x068 273#define OHCI1394_IRMultiChanMaskHiSet 0x070 274#define OHCI1394_IRMultiChanMaskHiClear 0x074 275#define OHCI1394_IRMultiChanMaskLoSet 0x078 276#define OHCI1394_IRMultiChanMaskLoClear 0x07C 277#define OHCI1394_IntEventSet 0x080 278#define OHCI1394_IntEventClear 0x084 279#define OHCI1394_IntMaskSet 0x088 280#define OHCI1394_IntMaskClear 0x08C 281#define OHCI1394_IsoXmitIntEventSet 0x090 282#define OHCI1394_IsoXmitIntEventClear 0x094 283#define OHCI1394_IsoXmitIntMaskSet 0x098 284#define OHCI1394_IsoXmitIntMaskClear 0x09C 285#define OHCI1394_IsoRecvIntEventSet 0x0A0 286#define OHCI1394_IsoRecvIntEventClear 0x0A4 287#define OHCI1394_IsoRecvIntMaskSet 0x0A8 288#define OHCI1394_IsoRecvIntMaskClear 0x0AC 289#define OHCI1394_FairnessControl 0x0DC 290#define OHCI1394_LinkControlSet 0x0E0 291#define OHCI1394_LinkControlClear 0x0E4 292#define OHCI1394_NodeID 0x0E8 293#define OHCI1394_PhyControl 0x0EC 294#define OHCI1394_IsochronousCycleTimer 0x0F0 295#define OHCI1394_AsReqFilterHiSet 0x100 296#define OHCI1394_AsReqFilterHiClear 0x104 297#define OHCI1394_AsReqFilterLoSet 0x108 298#define OHCI1394_AsReqFilterLoClear 0x10C 299#define OHCI1394_PhyReqFilterHiSet 0x110 300#define OHCI1394_PhyReqFilterHiClear 0x114 301#define OHCI1394_PhyReqFilterLoSet 0x118 302#define OHCI1394_PhyReqFilterLoClear 0x11C 303#define OHCI1394_PhyUpperBound 0x120 304 305#define OHCI1394_AsReqTrContextBase 0x180 306#define OHCI1394_AsReqTrContextControlSet 0x180 307#define OHCI1394_AsReqTrContextControlClear 0x184 308#define OHCI1394_AsReqTrCommandPtr 0x18C 309 310#define OHCI1394_AsRspTrContextBase 0x1A0 311#define OHCI1394_AsRspTrContextControlSet 0x1A0 312#define OHCI1394_AsRspTrContextControlClear 0x1A4 313#define OHCI1394_AsRspTrCommandPtr 0x1AC 314 315#define OHCI1394_AsReqRcvContextBase 0x1C0 316#define OHCI1394_AsReqRcvContextControlSet 0x1C0 317#define OHCI1394_AsReqRcvContextControlClear 0x1C4 318#define OHCI1394_AsReqRcvCommandPtr 0x1CC 319 320#define OHCI1394_AsRspRcvContextBase 0x1E0 321#define OHCI1394_AsRspRcvContextControlSet 0x1E0 322#define OHCI1394_AsRspRcvContextControlClear 0x1E4 323#define OHCI1394_AsRspRcvCommandPtr 0x1EC 324 325/* Isochronous transmit registers */ 326/* Add (16 * n) for context n */ 327#define OHCI1394_IsoXmitContextBase 0x200 328#define OHCI1394_IsoXmitContextControlSet 0x200 329#define OHCI1394_IsoXmitContextControlClear 0x204 330#define OHCI1394_IsoXmitCommandPtr 0x20C 331 332/* Isochronous receive registers */ 333/* Add (32 * n) for context n */ 334#define OHCI1394_IsoRcvContextBase 0x400 335#define OHCI1394_IsoRcvContextControlSet 0x400 336#define OHCI1394_IsoRcvContextControlClear 0x404 337#define OHCI1394_IsoRcvCommandPtr 0x40C 338#define OHCI1394_IsoRcvContextMatch 0x410 339 340/* Interrupts Mask/Events */ 341 342#define OHCI1394_reqTxComplete 0x00000001 343#define OHCI1394_respTxComplete 0x00000002 344#define OHCI1394_ARRQ 0x00000004 345#define OHCI1394_ARRS 0x00000008 346#define OHCI1394_RQPkt 0x00000010 347#define OHCI1394_RSPkt 0x00000020 348#define OHCI1394_isochTx 0x00000040 349#define OHCI1394_isochRx 0x00000080 350#define OHCI1394_postedWriteErr 0x00000100 351#define OHCI1394_lockRespErr 0x00000200 352#define OHCI1394_selfIDComplete 0x00010000 353#define OHCI1394_busReset 0x00020000 354#define OHCI1394_phy 0x00080000 355#define OHCI1394_cycleSynch 0x00100000 356#define OHCI1394_cycle64Seconds 0x00200000 357#define OHCI1394_cycleLost 0x00400000 358#define OHCI1394_cycleInconsistent 0x00800000 359#define OHCI1394_unrecoverableError 0x01000000 360#define OHCI1394_cycleTooLong 0x02000000 361#define OHCI1394_phyRegRcvd 0x04000000 362#define OHCI1394_masterIntEnable 0x80000000 363 364/* DMA Control flags */ 365#define DMA_CTL_OUTPUT_MORE 0x00000000 366#define DMA_CTL_OUTPUT_LAST 0x10000000 367#define DMA_CTL_INPUT_MORE 0x20000000 368#define DMA_CTL_INPUT_LAST 0x30000000 369#define DMA_CTL_UPDATE 0x08000000 370#define DMA_CTL_IMMEDIATE 0x02000000 371#define DMA_CTL_IRQ 0x00300000 372#define DMA_CTL_BRANCH 0x000c0000 373#define DMA_CTL_WAIT 0x00030000 374 375/* OHCI evt_* error types, table 3-2 of the OHCI 1.1 spec. */ 376#define EVT_NO_STATUS 0x0 /* No event status */ 377#define EVT_RESERVED 0x1 /* Reserved, not used !!! */ 378#define EVT_LONG_PACKET 0x2 /* The revc data was longer than the buf */ 379#define EVT_MISSING_ACK 0x3 /* A subaction gap was detected before an ack 380 arrived, or recv'd ack had a parity error */ 381#define EVT_UNDERRUN 0x4 /* Underrun on corresponding FIFO, packet 382 truncated */ 383#define EVT_OVERRUN 0x5 /* A recv FIFO overflowed on reception of ISO 384 packet */ 385#define EVT_DESCRIPTOR_READ 0x6 /* An unrecoverable error occured while host was 386 reading a descriptor block */ 387#define EVT_DATA_READ 0x7 /* An error occured while host controller was 388 attempting to read from host memory in the data 389 stage of descriptor processing */ 390#define EVT_DATA_WRITE 0x8 /* An error occured while host controller was 391 attempting to write either during the data stage 392 of descriptor processing, or when processing a single 393 16-bit host memory write */ 394#define EVT_BUS_RESET 0x9 /* Identifies a PHY packet in the recv buffer as 395 being a synthesized bus reset packet */ 396 397#define OHCI1394_TCODE_PHY 0xE 398 399void ohci1394_init_iso_tasklet(struct ohci1394_iso_tasklet *tasklet, 400 int type, 401 void (*func)(unsigned long), 402 unsigned long data); 403int ohci1394_register_iso_tasklet(struct ti_ohci *ohci, 404 struct ohci1394_iso_tasklet *tasklet); 405void ohci1394_unregister_iso_tasklet(struct ti_ohci *ohci, 406 struct ohci1394_iso_tasklet *tasklet); 407 408void ohci1394_stop_context (struct ti_ohci *ohci, int reg, char *msg); 409struct ti_ohci *ohci1394_get_struct(int card_num); 410 411#endif 412 413