1/* 2 * linux/drivers/ide/ide-pci.c Version 1.05 June 9, 2000 3 * 4 * Copyright (c) 1998-2000 Andre Hedrick <andre@linux-ide.org> 5 * 6 * Copyright (c) 1995-1998 Mark Lord 7 * May be copied or modified under the terms of the GNU General Public License 8 */ 9 10/* 11 * This module provides support for automatic detection and 12 * configuration of all PCI IDE interfaces present in a system. 13 */ 14 15#include <linux/config.h> 16#include <linux/types.h> 17#include <linux/kernel.h> 18#include <linux/timer.h> 19#include <linux/mm.h> 20#include <linux/interrupt.h> 21#include <linux/pci.h> 22#include <linux/init.h> 23#include <linux/ide.h> 24 25#include <asm/io.h> 26#include <asm/irq.h> 27 28#define DEVID_PIIXa ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0}) 29#define DEVID_PIIXb ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1}) 30#define DEVID_MPIIX ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX}) 31#define DEVID_PIIX3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1}) 32#define DEVID_PIIX4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB}) 33#define DEVID_ICH0 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1}) 34#define DEVID_PIIX4E2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1}) 35#define DEVID_ICH ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1}) 36#define DEVID_PIIX4U2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1}) 37#define DEVID_PIIX4NX ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX}) 38#define DEVID_ICH2 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9}) 39#define DEVID_ICH2M ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8}) 40#define DEVID_ICH3M ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10}) 41#define DEVID_ICH3 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11}) 42#define DEVID_ICH4 ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11}) 43#define DEVID_CICH ((ide_pci_devid_t){PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11}) 44#define DEVID_VIA_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561}) 45#define DEVID_MR_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1}) 46#define DEVID_VP_IDE ((ide_pci_devid_t){PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1}) 47#define DEVID_PDC20246 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246}) 48#define DEVID_PDC20262 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262}) 49#define DEVID_PDC20265 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265}) 50#define DEVID_PDC20267 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267}) 51#define DEVID_PDC20268 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268}) 52#define DEVID_PDC20270 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270}) 53#define DEVID_PDC20269 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269}) 54#define DEVID_PDC20275 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275}) 55#define DEVID_PDC20276 ((ide_pci_devid_t){PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276}) 56#define DEVID_RZ1000 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000}) 57#define DEVID_RZ1001 ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001}) 58#define DEVID_SAMURAI ((ide_pci_devid_t){PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE}) 59#define DEVID_CMD640 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640}) 60#define DEVID_CMD643 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643}) 61#define DEVID_CMD646 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646}) 62#define DEVID_CMD648 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648}) 63#define DEVID_CMD649 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649}) 64#define DEVID_CMD680 ((ide_pci_devid_t){PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_680}) 65#define DEVID_SIS5513 ((ide_pci_devid_t){PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513}) 66#define DEVID_OPTI621 ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621}) 67#define DEVID_OPTI621V ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558}) 68#define DEVID_OPTI621X ((ide_pci_devid_t){PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825}) 69#define DEVID_TRM290 ((ide_pci_devid_t){PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290}) 70#define DEVID_NS87410 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410}) 71#define DEVID_NS87415 ((ide_pci_devid_t){PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415}) 72#define DEVID_HT6565 ((ide_pci_devid_t){PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565}) 73#define DEVID_AEC6210 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF}) 74#define DEVID_AEC6260 ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860}) 75#define DEVID_AEC6260R ((ide_pci_devid_t){PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R}) 76#define DEVID_W82C105 ((ide_pci_devid_t){PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105}) 77#define DEVID_UM8673F ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F}) 78#define DEVID_UM8886A ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A}) 79#define DEVID_UM8886BF ((ide_pci_devid_t){PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF}) 80#define DEVID_HPT34X ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343}) 81#define DEVID_HPT366 ((ide_pci_devid_t){PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366}) 82#define DEVID_ALI15X3 ((ide_pci_devid_t){PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229}) 83#define DEVID_CY82C693 ((ide_pci_devid_t){PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693}) 84#define DEVID_HINT ((ide_pci_devid_t){0x3388, 0x8013}) 85#define DEVID_CS5530 ((ide_pci_devid_t){PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE}) 86#define DEVID_AMD7401 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401}) 87#define DEVID_AMD7409 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409}) 88#define DEVID_AMD7411 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411}) 89#define DEVID_AMD7441 ((ide_pci_devid_t){PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7441}) 90#define DEVID_PDCADMA ((ide_pci_devid_t){PCI_VENDOR_ID_PDC, PCI_DEVICE_ID_PDC_1841}) 91#define DEVID_SLC90E66 ((ide_pci_devid_t){PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1}) 92#define DEVID_OSB4 ((ide_pci_devid_t){PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE}) 93#define DEVID_CSB5 ((ide_pci_devid_t){PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE}) 94#define DEVID_ITE8172G ((ide_pci_devid_t){PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G}) 95 96#define IDE_IGNORE ((void *)-1) 97#define IDE_NO_DRIVER ((void *)-2) 98 99#ifdef CONFIG_BLK_DEV_AEC62XX 100extern unsigned int pci_init_aec62xx(struct pci_dev *, const char *); 101extern unsigned int ata66_aec62xx(ide_hwif_t *); 102extern void ide_init_aec62xx(ide_hwif_t *); 103extern void ide_dmacapable_aec62xx(ide_hwif_t *, unsigned long); 104#define PCI_AEC62XX &pci_init_aec62xx 105#define ATA66_AEC62XX &ata66_aec62xx 106#define INIT_AEC62XX &ide_init_aec62xx 107#define DMA_AEC62XX &ide_dmacapable_aec62xx 108#else 109#define PCI_AEC62XX NULL 110#define ATA66_AEC62XX NULL 111#define INIT_AEC62XX IDE_NO_DRIVER 112#define DMA_AEC62XX NULL 113#endif 114 115#ifdef CONFIG_BLK_DEV_ALI15X3 116extern unsigned int pci_init_ali15x3(struct pci_dev *, const char *); 117extern unsigned int ata66_ali15x3(ide_hwif_t *); 118extern void ide_init_ali15x3(ide_hwif_t *); 119extern void ide_dmacapable_ali15x3(ide_hwif_t *, unsigned long); 120#define PCI_ALI15X3 &pci_init_ali15x3 121#define ATA66_ALI15X3 &ata66_ali15x3 122#define INIT_ALI15X3 &ide_init_ali15x3 123#define DMA_ALI15X3 &ide_dmacapable_ali15x3 124#else 125#define PCI_ALI15X3 NULL 126#define ATA66_ALI15X3 NULL 127#define INIT_ALI15X3 IDE_NO_DRIVER 128#define DMA_ALI15X3 NULL 129#endif 130 131#ifdef CONFIG_BLK_DEV_AMD74XX 132extern unsigned int pci_init_amd74xx(struct pci_dev *, const char *); 133extern unsigned int ata66_amd74xx(ide_hwif_t *); 134extern void ide_init_amd74xx(ide_hwif_t *); 135extern void ide_dmacapable_amd74xx(ide_hwif_t *, unsigned long); 136#define PCI_AMD74XX &pci_init_amd74xx 137#define ATA66_AMD74XX &ata66_amd74xx 138#define INIT_AMD74XX &ide_init_amd74xx 139#define DMA_AMD74XX &ide_dmacapable_amd74xx 140#else 141#define PCI_AMD74XX NULL 142#define ATA66_AMD74XX NULL 143#define INIT_AMD74XX IDE_NO_DRIVER 144#define DMA_AMD74XX NULL 145#endif 146 147#ifdef CONFIG_BLK_DEV_CMD64X 148extern unsigned int pci_init_cmd64x(struct pci_dev *, const char *); 149extern unsigned int ata66_cmd64x(ide_hwif_t *); 150extern void ide_init_cmd64x(ide_hwif_t *); 151extern void ide_dmacapable_cmd64x(ide_hwif_t *, unsigned long); 152#define PCI_CMD64X &pci_init_cmd64x 153#define ATA66_CMD64X &ata66_cmd64x 154#define INIT_CMD64X &ide_init_cmd64x 155#else 156#define PCI_CMD64X NULL 157#define ATA66_CMD64X NULL 158#ifdef __sparc_v9__ 159#define INIT_CMD64X IDE_IGNORE 160#else 161#define INIT_CMD64X IDE_NO_DRIVER 162#endif 163#endif 164 165#ifdef CONFIG_BLK_DEV_CY82C693 166extern unsigned int pci_init_cy82c693(struct pci_dev *, const char *); 167extern void ide_init_cy82c693(ide_hwif_t *); 168#define PCI_CY82C693 &pci_init_cy82c693 169#define INIT_CY82C693 &ide_init_cy82c693 170#else 171#define PCI_CY82C693 NULL 172#define INIT_CY82C693 IDE_NO_DRIVER 173#endif 174 175#ifdef CONFIG_BLK_DEV_CS5530 176extern unsigned int pci_init_cs5530(struct pci_dev *, const char *); 177extern void ide_init_cs5530(ide_hwif_t *); 178#define PCI_CS5530 &pci_init_cs5530 179#define INIT_CS5530 &ide_init_cs5530 180#else 181#define PCI_CS5530 NULL 182#define INIT_CS5530 IDE_NO_DRIVER 183#endif 184 185#ifdef CONFIG_BLK_DEV_HPT34X 186extern unsigned int pci_init_hpt34x(struct pci_dev *, const char *); 187extern void ide_init_hpt34x(ide_hwif_t *); 188#define PCI_HPT34X &pci_init_hpt34x 189#define INIT_HPT34X &ide_init_hpt34x 190#else 191#define PCI_HPT34X NULL 192#define INIT_HPT34X IDE_IGNORE 193#endif 194 195#ifdef CONFIG_BLK_DEV_HPT366 196extern byte hpt363_shared_irq; 197extern byte hpt363_shared_pin; 198extern unsigned int pci_init_hpt366(struct pci_dev *, const char *); 199extern unsigned int ata66_hpt366(ide_hwif_t *); 200extern void ide_init_hpt366(ide_hwif_t *); 201extern void ide_dmacapable_hpt366(ide_hwif_t *, unsigned long); 202#define PCI_HPT366 &pci_init_hpt366 203#define ATA66_HPT366 &ata66_hpt366 204#define INIT_HPT366 &ide_init_hpt366 205#define DMA_HPT366 &ide_dmacapable_hpt366 206#else 207static byte hpt363_shared_irq; 208static byte hpt363_shared_pin; 209#define PCI_HPT366 NULL 210#define ATA66_HPT366 NULL 211#define INIT_HPT366 IDE_NO_DRIVER 212#define DMA_HPT366 NULL 213#endif 214 215#ifdef CONFIG_BLK_DEV_NS87415 216extern void ide_init_ns87415(ide_hwif_t *); 217#define INIT_NS87415 &ide_init_ns87415 218#else 219#define INIT_NS87415 IDE_IGNORE 220#endif 221 222#ifdef CONFIG_BLK_DEV_OPTI621 223extern void ide_init_opti621(ide_hwif_t *); 224#define INIT_OPTI621 &ide_init_opti621 225#else 226#define INIT_OPTI621 IDE_NO_DRIVER 227#endif 228 229#ifdef CONFIG_BLK_DEV_PDC_ADMA 230extern unsigned int pci_init_pdcadma(struct pci_dev *, const char *); 231extern unsigned int ata66_pdcadma(ide_hwif_t *); 232extern void ide_init_pdcadma(ide_hwif_t *); 233extern void ide_dmacapable_pdcadma(ide_hwif_t *, unsigned long); 234#define PCI_PDCADMA &pci_init_pdcadma 235#define ATA66_PDCADMA &ata66_pdcadma 236#define INIT_PDCADMA &ide_init_pdcadma 237#define DMA_PDCADMA &ide_dmacapable_pdcadma 238#else 239#define PCI_PDCADMA IDE_IGNORE 240#define ATA66_PDCADMA IDE_IGNORE 241#define INIT_PDCADMA IDE_IGNORE 242#define DMA_PDCADMA IDE_IGNORE 243#endif 244 245#ifdef CONFIG_BLK_DEV_PDC202XX 246extern unsigned int pci_init_pdc202xx(struct pci_dev *, const char *); 247extern unsigned int ata66_pdc202xx(ide_hwif_t *); 248extern void ide_init_pdc202xx(ide_hwif_t *); 249#define PCI_PDC202XX &pci_init_pdc202xx 250#define ATA66_PDC202XX &ata66_pdc202xx 251#define INIT_PDC202XX &ide_init_pdc202xx 252#else 253#define PCI_PDC202XX NULL 254#define ATA66_PDC202XX NULL 255#define INIT_PDC202XX NULL 256#endif 257 258#ifdef CONFIG_BLK_DEV_PIIX 259extern unsigned int pci_init_piix(struct pci_dev *, const char *); 260extern unsigned int ata66_piix(ide_hwif_t *); 261extern void ide_init_piix(ide_hwif_t *); 262#define PCI_PIIX &pci_init_piix 263#define ATA66_PIIX &ata66_piix 264#define INIT_PIIX &ide_init_piix 265#else 266#define PCI_PIIX NULL 267#define ATA66_PIIX NULL 268#define INIT_PIIX IDE_NO_DRIVER 269#endif 270 271#ifdef CONFIG_BLK_DEV_IT8172 272extern unsigned int pci_init_it8172(struct pci_dev *, const char *); 273extern unsigned int ata66_it8172(ide_hwif_t *); 274extern void ide_init_it8172(ide_hwif_t *); 275#define PCI_IT8172 &pci_init_it8172 276#define INIT_IT8172 &ide_init_it8172 277#else 278#define PCI_IT8172 NULL 279#define ATA66_IT8172 NULL 280#define INIT_IT8172 NULL 281#endif 282 283#ifdef CONFIG_BLK_DEV_RZ1000 284extern void ide_init_rz1000(ide_hwif_t *); 285#define INIT_RZ1000 &ide_init_rz1000 286#else 287#define INIT_RZ1000 IDE_IGNORE 288#endif 289 290#define INIT_SAMURAI NULL 291 292#ifdef CONFIG_BLK_DEV_SVWKS 293extern unsigned int pci_init_svwks(struct pci_dev *, const char *); 294extern unsigned int ata66_svwks(ide_hwif_t *); 295extern void ide_init_svwks(ide_hwif_t *); 296#define PCI_SVWKS &pci_init_svwks 297#define ATA66_SVWKS &ata66_svwks 298#define INIT_SVWKS &ide_init_svwks 299#else 300#define PCI_SVWKS NULL 301#define ATA66_SVWKS NULL 302#define INIT_SVWKS IDE_NO_DRIVER 303#endif 304 305#ifdef CONFIG_BLK_DEV_SIS5513 306extern unsigned int pci_init_sis5513(struct pci_dev *, const char *); 307extern unsigned int ata66_sis5513(ide_hwif_t *); 308extern void ide_init_sis5513(ide_hwif_t *); 309#define PCI_SIS5513 &pci_init_sis5513 310#define ATA66_SIS5513 &ata66_sis5513 311#define INIT_SIS5513 &ide_init_sis5513 312#else 313#define PCI_SIS5513 NULL 314#define ATA66_SIS5513 NULL 315#define INIT_SIS5513 IDE_NO_DRIVER 316#endif 317 318#ifdef CONFIG_BLK_DEV_SLC90E66 319extern unsigned int pci_init_slc90e66(struct pci_dev *, const char *); 320extern unsigned int ata66_slc90e66(ide_hwif_t *); 321extern void ide_init_slc90e66(ide_hwif_t *); 322#define PCI_SLC90E66 &pci_init_slc90e66 323#define ATA66_SLC90E66 &ata66_slc90e66 324#define INIT_SLC90E66 &ide_init_slc90e66 325#else 326#define PCI_SLC90E66 NULL 327#define ATA66_SLC90E66 NULL 328#define INIT_SLC90E66 IDE_NO_DRIVER 329#endif 330 331#ifdef CONFIG_BLK_DEV_SL82C105 332extern unsigned int pci_init_sl82c105(struct pci_dev *, const char *); 333extern void dma_init_sl82c105(ide_hwif_t *, unsigned long); 334extern void ide_init_sl82c105(ide_hwif_t *); 335#define PCI_W82C105 &pci_init_sl82c105 336#define DMA_W82C105 &dma_init_sl82c105 337#define INIT_W82C105 &ide_init_sl82c105 338#else 339#define PCI_W82C105 NULL 340#define DMA_W82C105 NULL 341#define INIT_W82C105 IDE_IGNORE 342#endif 343 344#ifdef CONFIG_BLK_DEV_TRM290 345extern void ide_init_trm290(ide_hwif_t *); 346#define INIT_TRM290 &ide_init_trm290 347#else 348#define INIT_TRM290 IDE_IGNORE 349#endif 350 351#ifdef CONFIG_BLK_DEV_VIA82CXXX 352extern unsigned int pci_init_via82cxxx(struct pci_dev *, const char *); 353extern unsigned int ata66_via82cxxx(ide_hwif_t *); 354extern void ide_init_via82cxxx(ide_hwif_t *); 355extern void ide_dmacapable_via82cxxx(ide_hwif_t *, unsigned long); 356#define PCI_VIA82CXXX &pci_init_via82cxxx 357#define ATA66_VIA82CXXX &ata66_via82cxxx 358#define INIT_VIA82CXXX &ide_init_via82cxxx 359#define DMA_VIA82CXXX &ide_dmacapable_via82cxxx 360#else 361#define PCI_VIA82CXXX NULL 362#define ATA66_VIA82CXXX NULL 363#define INIT_VIA82CXXX IDE_NO_DRIVER 364#define DMA_VIA82CXXX NULL 365#endif 366 367typedef struct ide_pci_enablebit_s { 368 byte reg; /* byte pci reg holding the enable-bit */ 369 byte mask; /* mask to isolate the enable-bit */ 370 byte val; /* value of masked reg when "enabled" */ 371} ide_pci_enablebit_t; 372 373typedef struct ide_pci_device_s { 374 ide_pci_devid_t devid; 375 char *name; 376 unsigned int (*init_chipset)(struct pci_dev *dev, const char *name); 377 unsigned int (*ata66_check)(ide_hwif_t *hwif); 378 void (*init_hwif)(ide_hwif_t *hwif); 379 void (*dma_init)(ide_hwif_t *hwif, unsigned long dmabase); 380 ide_pci_enablebit_t enablebits[2]; 381 byte bootable; 382 unsigned int extra; 383} ide_pci_device_t; 384 385static ide_pci_device_t ide_pci_chipsets[] __initdata = { 386 {DEVID_PIIXa, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 387 {DEVID_PIIXb, "PIIX", NULL, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 388 {DEVID_MPIIX, "MPIIX", NULL, NULL, INIT_PIIX, NULL, {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}}, ON_BOARD, 0 }, 389 {DEVID_PIIX3, "PIIX3", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 390 {DEVID_PIIX4, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 391 {DEVID_ICH0, "ICH0", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 392 {DEVID_PIIX4E2, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 393 {DEVID_ICH, "ICH", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 394 {DEVID_PIIX4U2, "PIIX4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 395 {DEVID_PIIX4NX, "PIIX4", PCI_PIIX, NULL, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 396 {DEVID_ICH2, "ICH2", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 397 {DEVID_ICH2M, "ICH2M", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 398 {DEVID_ICH3M, "ICH3M", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 399 {DEVID_ICH3, "ICH3", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 400 {DEVID_ICH4, "ICH4", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 401 {DEVID_CICH, "C-ICH", PCI_PIIX, ATA66_PIIX, INIT_PIIX, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 402 {DEVID_VIA_IDE, "VIA_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 403 {DEVID_MR_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 }, 404 {DEVID_VP_IDE, "VP_IDE", PCI_VIA82CXXX, ATA66_VIA82CXXX,INIT_VIA82CXXX, DMA_VIA82CXXX, {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, ON_BOARD, 0 }, 405#ifndef CONFIG_PDC202XX_FORCE 406 {DEVID_PDC20246,"PDC20246", PCI_PDC202XX, NULL, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 16 }, 407 {DEVID_PDC20262,"PDC20262", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48 }, 408 {DEVID_PDC20265,"PDC20265", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48 }, 409 {DEVID_PDC20267,"PDC20267", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 48 }, 410#else /* !CONFIG_PDC202XX_FORCE */ 411 {DEVID_PDC20246,"PDC20246", PCI_PDC202XX, NULL, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 16 }, 412 {DEVID_PDC20262,"PDC20262", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 }, 413 {DEVID_PDC20265,"PDC20265", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 }, 414 {DEVID_PDC20267,"PDC20267", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x50,0x02,0x02}, {0x50,0x04,0x04}}, OFF_BOARD, 48 }, 415#endif 416 {DEVID_PDC20268,"PDC20268", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 }, 417 /* Promise used a different PCI ident for the raid card apparently to try and 418 prevent Linux detecting it and using our own raid code. We want to detect 419 it for the ataraid drivers, so we have to list both here.. */ 420 {DEVID_PDC20270,"PDC20270", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 }, 421 {DEVID_PDC20269,"PDC20269", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 }, 422 {DEVID_PDC20275,"PDC20275", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 }, 423 {DEVID_PDC20276,"PDC20276", PCI_PDC202XX, ATA66_PDC202XX, INIT_PDC202XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 }, 424 {DEVID_RZ1000, "RZ1000", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 425 {DEVID_RZ1001, "RZ1001", NULL, NULL, INIT_RZ1000, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 426 {DEVID_SAMURAI, "SAMURAI", NULL, NULL, INIT_SAMURAI, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 427 {DEVID_CMD640, "CMD640", NULL, NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 428 {DEVID_NS87410, "NS87410", NULL, NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0 }, 429 {DEVID_SIS5513, "SIS5513", PCI_SIS5513, ATA66_SIS5513, INIT_SIS5513, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, ON_BOARD, 0 }, 430 {DEVID_CMD643, "CMD643", PCI_CMD64X, NULL, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 431 {DEVID_CMD646, "CMD646", PCI_CMD64X, NULL, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x51,0x80,0x80}}, ON_BOARD, 0 }, 432 {DEVID_CMD648, "CMD648", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 433 {DEVID_CMD649, "CMD649", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 434#ifndef CONFIG_BLK_DEV_CMD680 435 {DEVID_CMD680, "CMD680", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 436#else /* CONFIG_BLK_DEV_CMD680 */ 437 {DEVID_CMD680, "CMD680", PCI_CMD64X, ATA66_CMD64X, INIT_CMD64X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 438#endif /* !CONFIG_BLK_DEV_CMD680 */ 439 {DEVID_HT6565, "HT6565", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 440 {DEVID_OPTI621, "OPTI621", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 }, 441 {DEVID_OPTI621X,"OPTI621X", NULL, NULL, INIT_OPTI621, NULL, {{0x45,0x80,0x00}, {0x40,0x08,0x00}}, ON_BOARD, 0 }, 442 {DEVID_TRM290, "TRM290", NULL, NULL, INIT_TRM290, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 443 {DEVID_NS87415, "NS87415", NULL, NULL, INIT_NS87415, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 444 {DEVID_AEC6210, "AEC6210", PCI_AEC62XX, NULL, INIT_AEC62XX, DMA_AEC62XX, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 }, 445 {DEVID_AEC6260, "AEC6260", PCI_AEC62XX, ATA66_AEC62XX, INIT_AEC62XX, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 0 }, 446 {DEVID_AEC6260R,"AEC6260R", PCI_AEC62XX, ATA66_AEC62XX, INIT_AEC62XX, NULL, {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, OFF_BOARD, 0 }, 447 {DEVID_W82C105, "W82C105", PCI_W82C105, NULL, INIT_W82C105, DMA_W82C105, {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, ON_BOARD, 0 }, 448 {DEVID_UM8673F, "UM8673F", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 449 {DEVID_UM8886A, "UM8886A", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 450 {DEVID_UM8886BF,"UM8886BF", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 451 {DEVID_HPT34X, "HPT34X", PCI_HPT34X, NULL, INIT_HPT34X, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, NEVER_BOARD, 16 }, 452 {DEVID_HPT366, "HPT366", PCI_HPT366, ATA66_HPT366, INIT_HPT366, DMA_HPT366, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 240 }, 453 {DEVID_ALI15X3, "ALI15X3", PCI_ALI15X3, ATA66_ALI15X3, INIT_ALI15X3, DMA_ALI15X3, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 454 {DEVID_CY82C693,"CY82C693", PCI_CY82C693, NULL, INIT_CY82C693, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 455 {DEVID_HINT, "HINT_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 456 {DEVID_CS5530, "CS5530", PCI_CS5530, NULL, INIT_CS5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 457 {DEVID_AMD7401, "AMD7401", NULL, NULL, NULL, DMA_AMD74XX, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 }, 458 {DEVID_AMD7409, "AMD7409", PCI_AMD74XX, ATA66_AMD74XX, INIT_AMD74XX, DMA_AMD74XX, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 }, 459 {DEVID_AMD7411, "AMD7411", PCI_AMD74XX, ATA66_AMD74XX, INIT_AMD74XX, DMA_AMD74XX, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 }, 460 {DEVID_AMD7441, "AMD7441", PCI_AMD74XX, ATA66_AMD74XX, INIT_AMD74XX, DMA_AMD74XX, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0 }, 461 {DEVID_PDCADMA, "PDCADMA", PCI_PDCADMA, ATA66_PDCADMA, INIT_PDCADMA, DMA_PDCADMA, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0 }, 462 {DEVID_SLC90E66,"SLC90E66", PCI_SLC90E66, ATA66_SLC90E66, INIT_SLC90E66, NULL, {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, ON_BOARD, 0 }, 463 {DEVID_OSB4, "ServerWorks OSB4", PCI_SVWKS, ATA66_SVWKS, INIT_SVWKS, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 464 {DEVID_CSB5, "ServerWorks CSB5", PCI_SVWKS, ATA66_SVWKS, INIT_SVWKS, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }, 465 {DEVID_ITE8172G,"IT8172G", PCI_IT8172, NULL, INIT_IT8172, NULL, {{0x00,0x00,0x00}, {0x40,0x00,0x01}}, ON_BOARD, 0 }, 466 {IDE_PCI_DEVID_NULL, "PCI_IDE", NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0 }}; 467 468/* 469 * This allows offboard ide-pci cards the enable a BIOS, verify interrupt 470 * settings of split-mirror pci-config space, place chipset into init-mode, 471 * and/or preserve an interrupt if the card is not native ide support. 472 */ 473static unsigned int __init ide_special_settings (struct pci_dev *dev, const char *name) 474{ 475 switch(dev->device) { 476 case PCI_DEVICE_ID_TTI_HPT366: 477 case PCI_DEVICE_ID_PROMISE_20246: 478 case PCI_DEVICE_ID_PROMISE_20262: 479 case PCI_DEVICE_ID_PROMISE_20265: 480 case PCI_DEVICE_ID_PROMISE_20267: 481 case PCI_DEVICE_ID_PROMISE_20268: 482 case PCI_DEVICE_ID_PROMISE_20270: 483 case PCI_DEVICE_ID_PROMISE_20269: 484 case PCI_DEVICE_ID_PROMISE_20275: 485 case PCI_DEVICE_ID_PROMISE_20276: 486 case PCI_DEVICE_ID_ARTOP_ATP850UF: 487 case PCI_DEVICE_ID_ARTOP_ATP860: 488 case PCI_DEVICE_ID_ARTOP_ATP860R: 489 return dev->irq; 490 default: 491 break; 492 } 493 return 0; 494} 495 496/* 497 * Match a PCI IDE port against an entry in ide_hwifs[], 498 * based on io_base port if possible. 499 */ 500static ide_hwif_t __init *ide_match_hwif (unsigned long io_base, byte bootable, const char *name) 501{ 502 int h; 503 ide_hwif_t *hwif; 504 505 /* 506 * Look for a hwif with matching io_base specified using 507 * parameters to ide_setup(). 508 */ 509 for (h = 0; h < MAX_HWIFS; ++h) { 510 hwif = &ide_hwifs[h]; 511 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { 512 if (hwif->chipset == ide_generic) 513 return hwif; /* a perfect match */ 514 } 515 } 516 /* 517 * Look for a hwif with matching io_base default value. 518 * If chipset is "ide_unknown", then claim that hwif slot. 519 * Otherwise, some other chipset has already claimed it.. :( 520 */ 521 for (h = 0; h < MAX_HWIFS; ++h) { 522 hwif = &ide_hwifs[h]; 523 if (hwif->io_ports[IDE_DATA_OFFSET] == io_base) { 524 if (hwif->chipset == ide_unknown) 525 return hwif; /* match */ 526 printk("%s: port 0x%04lx already claimed by %s\n", name, io_base, hwif->name); 527 return NULL; /* already claimed */ 528 } 529 } 530 /* 531 * Okay, there is no hwif matching our io_base, 532 * so we'll just claim an unassigned slot. 533 * Give preference to claiming other slots before claiming ide0/ide1, 534 * just in case there's another interface yet-to-be-scanned 535 * which uses ports 1f0/170 (the ide0/ide1 defaults). 536 * 537 * Unless there is a bootable card that does not use the standard 538 * ports 1f0/170 (the ide0/ide1 defaults). The (bootable) flag. 539 */ 540 if (bootable) { 541 for (h = 0; h < MAX_HWIFS; ++h) { 542 hwif = &ide_hwifs[h]; 543 if (hwif->chipset == ide_unknown) 544 return hwif; /* pick an unused entry */ 545 } 546 } else { 547 for (h = 2; h < MAX_HWIFS; ++h) { 548 hwif = ide_hwifs + h; 549 if (hwif->chipset == ide_unknown) 550 return hwif; /* pick an unused entry */ 551 } 552 } 553 for (h = 0; h < 2; ++h) { 554 hwif = ide_hwifs + h; 555 if (hwif->chipset == ide_unknown) 556 return hwif; /* pick an unused entry */ 557 } 558 printk("%s: too many IDE interfaces, no room in table\n", name); 559 return NULL; 560} 561 562static int __init ide_setup_pci_baseregs (struct pci_dev *dev, const char *name) 563{ 564 byte reg, progif = 0; 565 566 /* 567 * Place both IDE interfaces into PCI "native" mode: 568 */ 569 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) { 570 if ((progif & 0xa) != 0xa) { 571 printk("%s: device not capable of full native PCI mode\n", name); 572 return 1; 573 } 574 printk("%s: placing both ports into native PCI mode\n", name); 575 (void) pci_write_config_byte(dev, PCI_CLASS_PROG, progif|5); 576 if (pci_read_config_byte(dev, PCI_CLASS_PROG, &progif) || (progif & 5) != 5) { 577 printk("%s: rewrite of PROGIF failed, wanted 0x%04x, got 0x%04x\n", name, progif|5, progif); 578 return 1; 579 } 580 } 581 /* 582 * Setup base registers for IDE command/control spaces for each interface: 583 */ 584 for (reg = 0; reg < 4; reg++) { 585 struct resource *res = dev->resource + reg; 586 if ((res->flags & IORESOURCE_IO) == 0) 587 continue; 588 if (!res->start) { 589 printk("%s: Missing I/O address #%d\n", name, reg); 590 return 1; 591 } 592 } 593 return 0; 594} 595 596/* 597 * ide_setup_pci_device() looks at the primary/secondary interfaces 598 * on a PCI IDE device and, if they are enabled, prepares the IDE driver 599 * for use with them. This generic code works for most PCI chipsets. 600 * 601 * One thing that is not standardized is the location of the 602 * primary/secondary interface "enable/disable" bits. For chipsets that 603 * we "know" about, this information is in the ide_pci_device_t struct; 604 * for all other chipsets, we just assume both interfaces are enabled. 605 */ 606static void __init ide_setup_pci_device (struct pci_dev *dev, ide_pci_device_t *d) 607{ 608 unsigned int port, at_least_one_hwif_enabled = 0, autodma = 0, pciirq = 0; 609 unsigned short pcicmd = 0, tried_config = 0; 610 byte tmp = 0; 611 ide_hwif_t *hwif, *mate = NULL; 612 unsigned int class_rev; 613 static int secondpdc = 0; 614 615#ifdef CONFIG_IDEDMA_AUTO 616 if (!noautodma) 617 autodma = 1; 618#endif 619 620 if (d->init_hwif == IDE_NO_DRIVER) { 621 printk(KERN_WARNING "%s: detected chipset, but driver not compiled in!\n", d->name); 622 d->init_hwif = NULL; 623 } 624 625 if (pci_enable_device(dev)) { 626 if(pci_enable_device_bars(dev, 1<<4)) 627 { 628 printk(KERN_WARNING "%s: (ide_setup_pci_device:) Could not enable device.\n", d->name); 629 return; 630 } 631 printk(KERN_INFO "%s: BIOS setup was incomplete.\n", d->name); 632 } 633 634check_if_enabled: 635 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd)) { 636 printk("%s: error accessing PCI regs\n", d->name); 637 return; 638 } 639 if (!(pcicmd & PCI_COMMAND_IO)) { /* is device disabled? */ 640 /* 641 * PnP BIOS was *supposed* to have set this device up for us, 642 * but we can do it ourselves, so long as the BIOS has assigned an IRQ 643 * (or possibly the device is using a "legacy header" for IRQs). 644 * Maybe the user deliberately *disabled* the device, 645 * but we'll eventually ignore it again if no drives respond. 646 */ 647 if (tried_config++ 648 || ide_setup_pci_baseregs(dev, d->name) 649 || pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_IO)) { 650 printk("%s: device disabled (BIOS)\n", d->name); 651 return; 652 } 653 autodma = 0; /* default DMA off if we had to configure it here */ 654 goto check_if_enabled; 655 } 656 if (tried_config) 657 printk("%s: device enabled (Linux)\n", d->name); 658 659 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 660 class_rev &= 0xff; 661 662 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X)) { 663 /* see comments in hpt34x.c on why..... */ 664 char *chipset_names[] = {"HPT343", "HPT345"}; 665 strcpy(d->name, chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0]); 666 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD; 667 } 668 669 printk("%s: chipset revision %d\n", d->name, class_rev); 670 671 /* 672 * Can we trust the reported IRQ? 673 */ 674 pciirq = dev->irq; 675 676 if (dev->class >> 8 == PCI_CLASS_STORAGE_RAID) 677 { 678 /* By rights we want to ignore these, but the Promise Fastrak 679 * people have some strange ideas about proprietary so we have 680 * to act otherwise on those. The supertrak however we need 681 * to skip 682 */ 683 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265)) 684 { 685 printk(KERN_INFO "ide: Found promise 20265 in RAID mode.\n"); 686 if(dev->bus->self && dev->bus->self->vendor == PCI_VENDOR_ID_INTEL && 687 dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) 688 { 689 printk(KERN_INFO "ide: Skipping Promise PDC20265 attached to I2O RAID controller.\n"); 690 return; 691 } 692 } 693 /* Its attached to something else, just a random bridge. 694 Suspect a fastrak and fall through */ 695 } 696 697 if ((dev->class & ~(0xfa)) != ((PCI_CLASS_STORAGE_IDE << 8) | 5)) { 698 printk("%s: not 100%% native mode: will probe irqs later\n", d->name); 699 /* 700 * This allows offboard ide-pci cards the enable a BIOS, 701 * verify interrupt settings of split-mirror pci-config 702 * space, place chipset into init-mode, and/or preserve 703 * an interrupt if the card is not native ide support. 704 */ 705 pciirq = (d->init_chipset) ? d->init_chipset(dev, d->name) : ide_special_settings(dev, d->name); 706 } else if (tried_config) { 707 printk("%s: will probe irqs later\n", d->name); 708 pciirq = 0; 709 } else if (!pciirq) { 710 printk("%s: bad irq (%d): will probe later\n", d->name, pciirq); 711 pciirq = 0; 712 } else { 713 if (d->init_chipset) 714 (void) d->init_chipset(dev, d->name); 715#ifdef __sparc__ 716 printk("%s: 100%% native mode on irq %s\n", 717 d->name, __irq_itoa(pciirq)); 718#else 719 printk("%s: 100%% native mode on irq %d\n", d->name, pciirq); 720#endif 721 } 722 723 /* 724 * Set up the IDE ports 725 */ 726 for (port = 0; port <= 1; ++port) { 727 unsigned long base = 0, ctl = 0; 728 ide_pci_enablebit_t *e = &(d->enablebits[port]); 729 730 /* 731 * If this is a Promise FakeRaid controller, the 2nd controller will be marked as 732 * disabled while it is actually there and enabled by the bios for raid purposes. 733 * Skip the normal "is it enabled" test for those. 734 */ 735 if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265)) && (secondpdc++==1) && (port==1) ) 736 goto controller_ok; 737 if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262)) && (secondpdc++==1) && (port==1) ) 738 goto controller_ok; 739 740 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) || (tmp & e->mask) != e->val)) 741 continue; /* port not enabled */ 742controller_ok: 743 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) && (port) && (class_rev < 0x03)) 744 return; 745 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE || (dev->class & (port ? 4 : 1)) != 0) { 746 ctl = dev->resource[(2*port)+1].start; 747 base = dev->resource[2*port].start; 748 if (!(ctl & PCI_BASE_ADDRESS_IO_MASK) || 749 !(base & PCI_BASE_ADDRESS_IO_MASK)) { 750 printk("%s: IO baseregs (BIOS) are reported as MEM, report to <andre@linux-ide.org>.\n", d->name); 751 } 752 } 753 if ((ctl && !base) || (base && !ctl)) { 754 printk("%s: inconsistent baseregs (BIOS) for port %d, skipping\n", d->name, port); 755 continue; 756 } 757 if (!ctl) 758 ctl = port ? 0x374 : 0x3f4; /* use default value */ 759 if (!base) 760 base = port ? 0x170 : 0x1f0; /* use default value */ 761 if ((hwif = ide_match_hwif(base, d->bootable, d->name)) == NULL) 762 continue; /* no room in ide_hwifs[] */ 763 if (hwif->io_ports[IDE_DATA_OFFSET] != base) { 764 ide_init_hwif_ports(&hwif->hw, base, (ctl | 2), NULL); 765 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports)); 766 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET]; 767 } 768 hwif->chipset = ide_pci; 769 hwif->pci_dev = dev; 770 hwif->pci_devid = d->devid; 771 hwif->channel = port; 772 if (!hwif->irq) 773 hwif->irq = pciirq; 774 if (mate) { 775 hwif->mate = mate; 776 mate->mate = hwif; 777 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210)) { 778 hwif->serialized = 1; 779 mate->serialized = 1; 780 } 781 } 782 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) || 783 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886BF) || 784 IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8673F)) { 785 hwif->irq = hwif->channel ? 15 : 14; 786 goto bypass_umc_dma; 787 } 788 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_MPIIX)) 789 goto bypass_piix_dma; 790 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDCADMA)) 791 goto bypass_legacy_dma; 792#ifdef CONFIG_BLK_DEV_IDEDMA 793 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_SIS5513) || 794 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) || 795 IDE_PCI_DEVID_EQ(d->devid, DEVID_PIIX4NX) || 796 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) || 797 IDE_PCI_DEVID_EQ(d->devid, DEVID_VIA_IDE) || 798 IDE_PCI_DEVID_EQ(d->devid, DEVID_MR_IDE) || 799 IDE_PCI_DEVID_EQ(d->devid, DEVID_VP_IDE)) 800 autodma = 0; 801 if (autodma) 802 hwif->autodma = 1; 803 804 if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20246) || 805 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20262) || 806 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20265) || 807 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20267) || 808 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20268) || 809 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20270) || 810 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20269) || 811 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20275) || 812 IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20276) || 813 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6210) || 814 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260) || 815 IDE_PCI_DEVID_EQ(d->devid, DEVID_AEC6260R) || 816 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT34X) || 817 IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366) || 818 IDE_PCI_DEVID_EQ(d->devid, DEVID_CS5530) || 819 IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) || 820 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD646) || 821 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD648) || 822 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD649) || 823 IDE_PCI_DEVID_EQ(d->devid, DEVID_CMD680) || 824 IDE_PCI_DEVID_EQ(d->devid, DEVID_OSB4) || 825 ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE && (dev->class & 0x80))) { 826 unsigned long dma_base = ide_get_or_set_dma_base(hwif, (!mate && d->extra) ? d->extra : 0, d->name); 827 if (dma_base && !(pcicmd & PCI_COMMAND_MASTER)) { 828 /* 829 * Set up BM-DMA capability (PnP BIOS should have done this) 830 */ 831 if (!IDE_PCI_DEVID_EQ(d->devid, DEVID_CS5530)) 832 hwif->autodma = 0; /* default DMA off if we had to configure it here */ 833 (void) pci_write_config_word(dev, PCI_COMMAND, pcicmd | PCI_COMMAND_MASTER); 834 if (pci_read_config_word(dev, PCI_COMMAND, &pcicmd) || !(pcicmd & PCI_COMMAND_MASTER)) { 835 printk("%s: %s error updating PCICMD\n", hwif->name, d->name); 836 dma_base = 0; 837 } 838 } 839 if (dma_base) { 840 if (d->dma_init) { 841 d->dma_init(hwif, dma_base); 842 } else { 843 ide_setup_dma(hwif, dma_base, 8); 844 } 845 } else { 846 printk("%s: %s Bus-Master DMA disabled (BIOS)\n", hwif->name, d->name); 847 } 848 } 849 if (hwif->udma_four) { 850 printk("%s: ATA-66/100 forced bit set (WARNING)!!\n", d->name); 851 } else { 852 hwif->udma_four = (d->ata66_check) ? d->ata66_check(hwif) : 0; 853 } 854#endif /* CONFIG_BLK_DEV_IDEDMA */ 855bypass_legacy_dma: 856bypass_piix_dma: 857bypass_umc_dma: 858 if (d->init_hwif) /* Call chipset-specific routine for each enabled hwif */ 859 d->init_hwif(hwif); 860 mate = hwif; 861 at_least_one_hwif_enabled = 1; 862 } 863 if (!at_least_one_hwif_enabled) 864 printk("%s: neither IDE port enabled (BIOS)\n", d->name); 865} 866 867static void __init pdc20270_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d) 868{ 869 struct pci_dev *dev2 = NULL, *findev; 870 ide_pci_device_t *d2; 871 872 if ((dev->bus->self && 873 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) && 874 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) { 875 if (PCI_SLOT(dev->devfn) & 2) { 876 return; 877 } 878 d->extra = 0; 879 pci_for_each_dev(findev) { 880 if ((findev->vendor == dev->vendor) && 881 (findev->device == dev->device) && 882 (PCI_SLOT(findev->devfn) & 2)) { 883 byte irq = 0, irq2 = 0; 884 dev2 = findev; 885 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 886 pci_read_config_byte(dev2, PCI_INTERRUPT_LINE, &irq2); 887 if (irq != irq2) { 888 dev2->irq = dev->irq; 889 pci_write_config_byte(dev2, PCI_INTERRUPT_LINE, irq); 890 } 891 892 } 893 } 894 } 895 896 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn); 897 ide_setup_pci_device(dev, d); 898 if (!dev2) 899 return; 900 d2 = d; 901 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d2->name, dev2->bus->number, dev2->devfn); 902 ide_setup_pci_device(dev2, d2); 903} 904 905static void __init hpt366_device_order_fixup (struct pci_dev *dev, ide_pci_device_t *d) 906{ 907 struct pci_dev *dev2 = NULL, *findev; 908 ide_pci_device_t *d2; 909 unsigned char pin1 = 0, pin2 = 0; 910 unsigned int class_rev; 911 char *chipset_names[] = {"HPT366", "HPT366", "HPT368", "HPT370", "HPT370A", "HPT372"}; 912 913 if (PCI_FUNC(dev->devfn) & 1) 914 return; 915 916 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev); 917 class_rev &= 0xff; 918 if (class_rev > 5) 919 class_rev = 5; 920 921 strcpy(d->name, chipset_names[class_rev]); 922 923 switch(class_rev) { 924 case 4: 925 case 3: printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn); 926 ide_setup_pci_device(dev, d); 927 return; 928 default: break; 929 } 930 931 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); 932 pci_for_each_dev(findev) { 933 if ((findev->vendor == dev->vendor) && 934 (findev->device == dev->device) && 935 ((findev->devfn - dev->devfn) == 1) && 936 (PCI_FUNC(findev->devfn) & 1)) { 937 dev2 = findev; 938 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); 939 hpt363_shared_pin = (pin1 != pin2) ? 1 : 0; 940 hpt363_shared_irq = (dev->irq == dev2->irq) ? 1 : 0; 941 if (hpt363_shared_pin && hpt363_shared_irq) { 942 d->bootable = ON_BOARD; 943 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", d->name, pin1, pin2); 944 } 945 break; 946 } 947 } 948 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn); 949 ide_setup_pci_device(dev, d); 950 if (!dev2) 951 return; 952 d2 = d; 953 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d2->name, dev2->bus->number, dev2->devfn); 954 ide_setup_pci_device(dev2, d2); 955} 956 957/* 958 * ide_scan_pcibus() gets invoked at boot time from ide.c. 959 * It finds all PCI IDE controllers and calls ide_setup_pci_device for them. 960 */ 961void __init ide_scan_pcidev (struct pci_dev *dev) 962{ 963 ide_pci_devid_t devid; 964 ide_pci_device_t *d; 965 966 devid.vid = dev->vendor; 967 devid.did = dev->device; 968 for (d = ide_pci_chipsets; d->devid.vid && !IDE_PCI_DEVID_EQ(d->devid, devid); ++d); 969 if (d->init_hwif == IDE_IGNORE) 970 printk("%s: ignored by ide_scan_pci_device() (uses own driver)\n", d->name); 971 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_OPTI621V) && !(PCI_FUNC(dev->devfn) & 1)) 972 return; 973 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_CY82C693) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))) 974 return; /* CY82C693 is more than only a IDE controller */ 975 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_ITE8172G) && (!(PCI_FUNC(dev->devfn) & 1) || !((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))) 976 return; /* IT8172G is also more than only an IDE controller */ 977 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_UM8886A) && !(PCI_FUNC(dev->devfn) & 1)) 978 return; /* UM8886A/BF pair */ 979 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_HPT366)) 980 hpt366_device_order_fixup(dev, d); 981 else if (IDE_PCI_DEVID_EQ(d->devid, DEVID_PDC20270)) 982 pdc20270_device_order_fixup(dev, d); 983 else if (!IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL) || (dev->class >> 8) == PCI_CLASS_STORAGE_IDE) { 984 if (IDE_PCI_DEVID_EQ(d->devid, IDE_PCI_DEVID_NULL)) 985 printk("%s: unknown IDE controller on PCI bus %02x device %02x, VID=%04x, DID=%04x\n", 986 d->name, dev->bus->number, dev->devfn, devid.vid, devid.did); 987 else 988 printk("%s: IDE controller on PCI bus %02x dev %02x\n", d->name, dev->bus->number, dev->devfn); 989 ide_setup_pci_device(dev, d); 990 } 991} 992 993void __init ide_scan_pcibus (int scan_direction) 994{ 995 struct pci_dev *dev; 996 997 if (!scan_direction) { 998 pci_for_each_dev(dev) { 999 ide_scan_pcidev(dev); 1000 } 1001 } else { 1002 pci_for_each_dev_reverse(dev) { 1003 ide_scan_pcidev(dev); 1004 } 1005 } 1006} 1007