1/* r128_drv.h -- Private header for r128 driver -*- linux-c -*- 2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Rickard E. (Rik) Faith <faith@valinux.com> 29 * Kevin E. Martin <martin@valinux.com> 30 * Gareth Hughes <gareth@valinux.com> 31 * 32 */ 33 34#ifndef __R128_DRV_H__ 35#define __R128_DRV_H__ 36 37typedef struct drm_r128_freelist { 38 unsigned int age; 39 drm_buf_t *buf; 40 struct drm_r128_freelist *next; 41 struct drm_r128_freelist *prev; 42} drm_r128_freelist_t; 43 44typedef struct drm_r128_ring_buffer { 45 u32 *start; 46 u32 *end; 47 int size; 48 int size_l2qw; 49 50 volatile u32 *head; 51 u32 tail; 52 u32 tail_mask; 53 int space; 54} drm_r128_ring_buffer_t; 55 56typedef struct drm_r128_private { 57 drm_r128_ring_buffer_t ring; 58 drm_r128_sarea_t *sarea_priv; 59 60 int cce_mode; 61 int cce_fifo_size; 62 int cce_secure; 63 int cce_running; 64 65 drm_r128_freelist_t *head; 66 drm_r128_freelist_t *tail; 67 68 int usec_timeout; 69 int is_pci; 70 71 atomic_t idle_count; 72 73 unsigned int fb_bpp; 74 unsigned int front_offset; 75 unsigned int front_pitch; 76 unsigned int back_offset; 77 unsigned int back_pitch; 78 79 unsigned int depth_bpp; 80 unsigned int depth_offset; 81 unsigned int depth_pitch; 82 unsigned int span_offset; 83 84 u32 front_pitch_offset_c; 85 u32 back_pitch_offset_c; 86 u32 depth_pitch_offset_c; 87 u32 span_pitch_offset_c; 88 89 drm_map_t *sarea; 90 drm_map_t *fb; 91 drm_map_t *mmio; 92 drm_map_t *cce_ring; 93 drm_map_t *ring_rptr; 94 drm_map_t *buffers; 95 drm_map_t *agp_textures; 96} drm_r128_private_t; 97 98typedef struct drm_r128_buf_priv { 99 u32 age; 100 int prim; 101 int discard; 102 int dispatched; 103 drm_r128_freelist_t *list_entry; 104} drm_r128_buf_priv_t; 105 106 /* r128_drv.c */ 107extern int r128_version( struct inode *inode, struct file *filp, 108 unsigned int cmd, unsigned long arg ); 109extern int r128_open( struct inode *inode, struct file *filp ); 110extern int r128_release( struct inode *inode, struct file *filp ); 111extern int r128_ioctl( struct inode *inode, struct file *filp, 112 unsigned int cmd, unsigned long arg ); 113extern int r128_lock( struct inode *inode, struct file *filp, 114 unsigned int cmd, unsigned long arg ); 115extern int r128_unlock( struct inode *inode, struct file *filp, 116 unsigned int cmd, unsigned long arg ); 117 118 /* r128_cce.c */ 119extern int r128_cce_init( struct inode *inode, struct file *filp, 120 unsigned int cmd, unsigned long arg ); 121extern int r128_cce_start( struct inode *inode, struct file *filp, 122 unsigned int cmd, unsigned long arg ); 123extern int r128_cce_stop( struct inode *inode, struct file *filp, 124 unsigned int cmd, unsigned long arg ); 125extern int r128_cce_reset( struct inode *inode, struct file *filp, 126 unsigned int cmd, unsigned long arg ); 127extern int r128_cce_idle( struct inode *inode, struct file *filp, 128 unsigned int cmd, unsigned long arg ); 129extern int r128_engine_reset( struct inode *inode, struct file *filp, 130 unsigned int cmd, unsigned long arg ); 131extern int r128_cce_packet( struct inode *inode, struct file *filp, 132 unsigned int cmd, unsigned long arg ); 133extern int r128_cce_buffers( struct inode *inode, struct file *filp, 134 unsigned int cmd, unsigned long arg ); 135 136extern void r128_freelist_reset( drm_device_t *dev ); 137extern drm_buf_t *r128_freelist_get( drm_device_t *dev ); 138 139extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n ); 140extern void r128_update_ring_snapshot( drm_r128_private_t *dev_priv ); 141 142 /* r128_state.c */ 143extern int r128_cce_clear( struct inode *inode, struct file *filp, 144 unsigned int cmd, unsigned long arg ); 145extern int r128_cce_swap( struct inode *inode, struct file *filp, 146 unsigned int cmd, unsigned long arg ); 147extern int r128_cce_vertex( struct inode *inode, struct file *filp, 148 unsigned int cmd, unsigned long arg ); 149extern int r128_cce_indices( struct inode *inode, struct file *filp, 150 unsigned int cmd, unsigned long arg ); 151extern int r128_cce_blit( struct inode *inode, struct file *filp, 152 unsigned int cmd, unsigned long arg ); 153extern int r128_cce_depth( struct inode *inode, struct file *filp, 154 unsigned int cmd, unsigned long arg ); 155extern int r128_cce_stipple( struct inode *inode, struct file *filp, 156 unsigned int cmd, unsigned long arg ); 157 158 /* r128_bufs.c */ 159extern int r128_addbufs(struct inode *inode, struct file *filp, 160 unsigned int cmd, unsigned long arg); 161extern int r128_mapbufs(struct inode *inode, struct file *filp, 162 unsigned int cmd, unsigned long arg); 163 164 /* r128_context.c */ 165extern int r128_resctx(struct inode *inode, struct file *filp, 166 unsigned int cmd, unsigned long arg); 167extern int r128_addctx(struct inode *inode, struct file *filp, 168 unsigned int cmd, unsigned long arg); 169extern int r128_modctx(struct inode *inode, struct file *filp, 170 unsigned int cmd, unsigned long arg); 171extern int r128_getctx(struct inode *inode, struct file *filp, 172 unsigned int cmd, unsigned long arg); 173extern int r128_switchctx(struct inode *inode, struct file *filp, 174 unsigned int cmd, unsigned long arg); 175extern int r128_newctx(struct inode *inode, struct file *filp, 176 unsigned int cmd, unsigned long arg); 177extern int r128_rmctx(struct inode *inode, struct file *filp, 178 unsigned int cmd, unsigned long arg); 179 180extern int r128_context_switch(drm_device_t *dev, int old, int new); 181extern int r128_context_switch_complete(drm_device_t *dev, int new); 182 183 184/* Register definitions, register access macros and drmAddMap constants 185 * for Rage 128 kernel driver. 186 */ 187 188#define R128_AUX_SC_CNTL 0x1660 189# define R128_AUX1_SC_EN (1 << 0) 190# define R128_AUX1_SC_MODE_OR (0 << 1) 191# define R128_AUX1_SC_MODE_NAND (1 << 1) 192# define R128_AUX2_SC_EN (1 << 2) 193# define R128_AUX2_SC_MODE_OR (0 << 3) 194# define R128_AUX2_SC_MODE_NAND (1 << 3) 195# define R128_AUX3_SC_EN (1 << 4) 196# define R128_AUX3_SC_MODE_OR (0 << 5) 197# define R128_AUX3_SC_MODE_NAND (1 << 5) 198#define R128_AUX1_SC_LEFT 0x1664 199#define R128_AUX1_SC_RIGHT 0x1668 200#define R128_AUX1_SC_TOP 0x166c 201#define R128_AUX1_SC_BOTTOM 0x1670 202#define R128_AUX2_SC_LEFT 0x1674 203#define R128_AUX2_SC_RIGHT 0x1678 204#define R128_AUX2_SC_TOP 0x167c 205#define R128_AUX2_SC_BOTTOM 0x1680 206#define R128_AUX3_SC_LEFT 0x1684 207#define R128_AUX3_SC_RIGHT 0x1688 208#define R128_AUX3_SC_TOP 0x168c 209#define R128_AUX3_SC_BOTTOM 0x1690 210 211#define R128_BRUSH_DATA0 0x1480 212#define R128_BUS_CNTL 0x0030 213# define R128_BUS_MASTER_DIS (1 << 6) 214 215#define R128_CLOCK_CNTL_INDEX 0x0008 216#define R128_CLOCK_CNTL_DATA 0x000c 217# define R128_PLL_WR_EN (1 << 7) 218 219#define R128_CONSTANT_COLOR_C 0x1d34 220 221#define R128_DP_GUI_MASTER_CNTL 0x146c 222# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 223# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 224# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4) 225# define R128_GMC_BRUSH_NONE (15 << 4) 226# define R128_GMC_DST_16BPP (4 << 8) 227# define R128_GMC_DST_24BPP (5 << 8) 228# define R128_GMC_DST_32BPP (6 << 8) 229# define R128_GMC_DST_DATATYPE_SHIFT 8 230# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12) 231# define R128_DP_SRC_SOURCE_MEMORY (2 << 24) 232# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24) 233# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28) 234# define R128_GMC_AUX_CLIP_DIS (1 << 29) 235# define R128_GMC_WR_MSK_DIS (1 << 30) 236# define R128_ROP3_S 0x00cc0000 237# define R128_ROP3_P 0x00f00000 238#define R128_DP_WRITE_MASK 0x16cc 239#define R128_DST_PITCH_OFFSET_C 0x1c80 240# define R128_DST_TILE (1 << 31) 241 242#define R128_GEN_RESET_CNTL 0x00f0 243# define R128_SOFT_RESET_GUI (1 << 0) 244 245#define R128_GUI_SCRATCH_REG0 0x15e0 246#define R128_GUI_SCRATCH_REG1 0x15e4 247#define R128_GUI_SCRATCH_REG2 0x15e8 248#define R128_GUI_SCRATCH_REG3 0x15ec 249#define R128_GUI_SCRATCH_REG4 0x15f0 250#define R128_GUI_SCRATCH_REG5 0x15f4 251 252#define R128_GUI_STAT 0x1740 253# define R128_GUI_FIFOCNT_MASK 0x0fff 254# define R128_GUI_ACTIVE (1 << 31) 255 256#define R128_MCLK_CNTL 0x000f 257# define R128_FORCE_GCP (1 << 16) 258# define R128_FORCE_PIPE3D_CP (1 << 17) 259# define R128_FORCE_RCP (1 << 18) 260 261#define R128_PC_GUI_CTLSTAT 0x1748 262#define R128_PC_NGUI_CTLSTAT 0x0184 263# define R128_PC_FLUSH_GUI (3 << 0) 264# define R128_PC_RI_GUI (1 << 2) 265# define R128_PC_FLUSH_ALL 0x00ff 266# define R128_PC_BUSY (1 << 31) 267 268#define R128_PRIM_TEX_CNTL_C 0x1cb0 269 270#define R128_SCALE_3D_CNTL 0x1a00 271#define R128_SEC_TEX_CNTL_C 0x1d00 272#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c 273#define R128_SETUP_CNTL 0x1bc4 274#define R128_STEN_REF_MASK_C 0x1d40 275 276#define R128_TEX_CNTL_C 0x1c9c 277# define R128_TEX_CACHE_FLUSH (1 << 23) 278 279#define R128_WINDOW_XY_OFFSET 0x1bcc 280 281 282/* CCE registers 283 */ 284#define R128_PM4_BUFFER_OFFSET 0x0700 285#define R128_PM4_BUFFER_CNTL 0x0704 286# define R128_PM4_MASK (15 << 28) 287# define R128_PM4_NONPM4 (0 << 28) 288# define R128_PM4_192PIO (1 << 28) 289# define R128_PM4_192BM (2 << 28) 290# define R128_PM4_128PIO_64INDBM (3 << 28) 291# define R128_PM4_128BM_64INDBM (4 << 28) 292# define R128_PM4_64PIO_128INDBM (5 << 28) 293# define R128_PM4_64BM_128INDBM (6 << 28) 294# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28) 295# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28) 296# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28) 297 298#define R128_PM4_BUFFER_WM_CNTL 0x0708 299# define R128_WMA_SHIFT 0 300# define R128_WMB_SHIFT 8 301# define R128_WMC_SHIFT 16 302# define R128_WB_WM_SHIFT 24 303 304#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c 305#define R128_PM4_BUFFER_DL_RPTR 0x0710 306#define R128_PM4_BUFFER_DL_WPTR 0x0714 307# define R128_PM4_BUFFER_DL_DONE (1 << 31) 308 309#define R128_PM4_VC_FPU_SETUP 0x071c 310 311#define R128_PM4_IW_INDOFF 0x0738 312#define R128_PM4_IW_INDSIZE 0x073c 313 314#define R128_PM4_STAT 0x07b8 315# define R128_PM4_FIFOCNT_MASK 0x0fff 316# define R128_PM4_BUSY (1 << 16) 317# define R128_PM4_GUI_ACTIVE (1 << 31) 318 319#define R128_PM4_MICROCODE_ADDR 0x07d4 320#define R128_PM4_MICROCODE_RADDR 0x07d8 321#define R128_PM4_MICROCODE_DATAH 0x07dc 322#define R128_PM4_MICROCODE_DATAL 0x07e0 323 324#define R128_PM4_BUFFER_ADDR 0x07f0 325#define R128_PM4_MICRO_CNTL 0x07fc 326# define R128_PM4_MICRO_FREERUN (1 << 30) 327 328#define R128_PM4_FIFO_DATA_EVEN 0x1000 329#define R128_PM4_FIFO_DATA_ODD 0x1004 330 331 332/* CCE command packets 333 */ 334#define R128_CCE_PACKET0 0x00000000 335#define R128_CCE_PACKET1 0x40000000 336#define R128_CCE_PACKET2 0x80000000 337#define R128_CCE_PACKET3 0xC0000000 338# define R128_CNTL_HOSTDATA_BLT 0x00009400 339# define R128_CNTL_PAINT_MULTI 0x00009A00 340# define R128_CNTL_BITBLT_MULTI 0x00009B00 341# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300 342 343#define R128_CCE_PACKET_MASK 0xC0000000 344#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000 345#define R128_CCE_PACKET0_REG_MASK 0x000007ff 346#define R128_CCE_PACKET1_REG0_MASK 0x000007ff 347#define R128_CCE_PACKET1_REG1_MASK 0x003ff800 348 349#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000 350#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001 351#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002 352#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003 353#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 354#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 355#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 356#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007 357#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010 358#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020 359#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030 360#define R128_CCE_VC_CNTL_NUM_SHIFT 16 361 362#define R128_DATATYPE_CI8 2 363#define R128_DATATYPE_ARGB1555 3 364#define R128_DATATYPE_RGB565 4 365#define R128_DATATYPE_RGB888 5 366#define R128_DATATYPE_ARGB8888 6 367#define R128_DATATYPE_RGB332 7 368#define R128_DATATYPE_RGB8 9 369#define R128_DATATYPE_ARGB4444 15 370 371/* Constants */ 372#define R128_AGP_OFFSET 0x02000000 373 374#define R128_WATERMARK_L 16 375#define R128_WATERMARK_M 8 376#define R128_WATERMARK_N 8 377#define R128_WATERMARK_K 128 378 379#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 380 381#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0 382#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1 383#define R128_MAX_VB_AGE 0xffffffff 384 385#define R128_MAX_VB_VERTS (0xffff) 386 387 388#define R128_BASE(reg) ((unsigned long)(dev_priv->mmio->handle)) 389#define R128_ADDR(reg) (R128_BASE(reg) + reg) 390 391#define R128_READ(reg) readl(R128_ADDR(reg)) 392#define R128_WRITE(reg,val) writel(val,R128_ADDR(reg)) 393 394#define R128_READ8(reg) readb(R128_ADDR(reg)) 395#define R128_WRITE8(reg,val) writeb(val,R128_ADDR(reg)) 396 397#define R128_WRITE_PLL(addr,val) \ 398do { \ 399 R128_WRITE8(R128_CLOCK_CNTL_INDEX, ((addr) & 0x1f) | R128_PLL_WR_EN); \ 400 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \ 401} while (0) 402 403extern int R128_READ_PLL(drm_device_t *dev, int addr); 404 405#define R128CCE0(p,r,n) ((p) | ((n) << 16) | ((r) >> 2)) 406#define R128CCE1(p,r1,r2) ((p) | (((r2) >> 2) << 11) | ((r1) >> 2)) 407#define R128CCE2(p) ((p)) 408#define R128CCE3(p,n) ((p) | ((n) << 16)) 409 410 411 412 413#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \ 414 ((n) << 16) | ((reg) >> 2)) 415#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \ 416 (((reg1) >> 2) << 11) | ((reg0) >> 2)) 417#define CCE_PACKET2() (R128_CCE_PACKET2) 418#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \ 419 (pkt) | ((n) << 16)) 420 421 422#define r128_flush_write_combine() mb() 423 424 425#define R128_VERBOSE 0 426 427#define RING_LOCALS int write; unsigned int tail_mask; volatile u32 *ring; 428 429#define BEGIN_RING( n ) do { \ 430 if ( R128_VERBOSE ) { \ 431 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \ 432 n, __FUNCTION__ ); \ 433 } \ 434 if ( dev_priv->ring.space < n * sizeof(u32) ) { \ 435 r128_wait_ring( dev_priv, n * sizeof(u32) ); \ 436 } \ 437 dev_priv->ring.space -= n * sizeof(u32); \ 438 ring = dev_priv->ring.start; \ 439 write = dev_priv->ring.tail; \ 440 tail_mask = dev_priv->ring.tail_mask; \ 441} while (0) 442 443#define ADVANCE_RING() do { \ 444 if ( R128_VERBOSE ) { \ 445 DRM_INFO( "ADVANCE_RING() tail=0x%06x wr=0x%06x\n", \ 446 write, dev_priv->ring.tail ); \ 447 } \ 448 if ( write < 32 ) { \ 449 memcpy( dev_priv->ring.end, \ 450 dev_priv->ring.start, \ 451 write * sizeof(u32) ); \ 452 } \ 453 r128_flush_write_combine(); \ 454 dev_priv->ring.tail = write; \ 455 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); \ 456} while (0) 457 458#define OUT_RING( x ) do { \ 459 if ( R128_VERBOSE ) { \ 460 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \ 461 (unsigned int)(x), write ); \ 462 } \ 463 ring[write++] = x; \ 464 write &= tail_mask; \ 465} while (0) 466 467#define R128_PERFORMANCE_BOXES 0 468 469#endif /* __R128_DRV_H__ */ 470