1/* drm.h -- Header for Direct Rendering Manager -*- linux-c -*- 2 * Created: Mon Jan 4 10:05:05 1999 by faith@precisioninsight.com 3 * 4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Rickard E. (Rik) Faith <faith@valinux.com> 29 * 30 * Acknowledgements: 31 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg. 32 * 33 */ 34 35#ifndef _DRM_H_ 36#define _DRM_H_ 37 38#include <linux/config.h> 39#if defined(__linux__) 40#include <asm/ioctl.h> /* For _IO* macros */ 41#define DRM_IOCTL_NR(n) _IOC_NR(n) 42#elif defined(__FreeBSD__) 43#include <sys/ioccom.h> 44#define DRM_IOCTL_NR(n) ((n) & 0xff) 45#endif 46 47#define DRM_PROC_DEVICES "/proc/devices" 48#define DRM_PROC_MISC "/proc/misc" 49#define DRM_PROC_DRM "/proc/drm" 50#define DRM_DEV_DRM "/dev/drm" 51#define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) 52#define DRM_DEV_UID 0 53#define DRM_DEV_GID 0 54 55 56#define DRM_NAME "drm" /* Name in kernel, /dev, and /proc */ 57#define DRM_MIN_ORDER 5 /* At least 2^5 bytes = 32 bytes */ 58#define DRM_MAX_ORDER 22 /* Up to 2^22 bytes = 4MB */ 59#define DRM_RAM_PERCENT 10 /* How much system ram can we lock? */ 60 61#define _DRM_LOCK_HELD 0x80000000 /* Hardware lock is held */ 62#define _DRM_LOCK_CONT 0x40000000 /* Hardware lock is contended */ 63#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 64#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 65#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 66 67typedef unsigned long drm_handle_t; 68typedef unsigned int drm_context_t; 69typedef unsigned int drm_drawable_t; 70typedef unsigned int drm_magic_t; 71 72/* Warning: If you change this structure, make sure you change 73 * XF86DRIClipRectRec in the server as well */ 74 75typedef struct drm_clip_rect { 76 unsigned short x1; 77 unsigned short y1; 78 unsigned short x2; 79 unsigned short y2; 80} drm_clip_rect_t; 81 82/* Seperate include files for the i810/mga/r128 specific structures */ 83#include "mga_drm.h" 84#include "i810_drm.h" 85#include "r128_drm.h" 86#include "radeon_drm.h" 87#ifdef CONFIG_DRM40_SIS 88#include "sis_drm.h" 89#endif 90 91typedef struct drm_version { 92 int version_major; /* Major version */ 93 int version_minor; /* Minor version */ 94 int version_patchlevel;/* Patch level */ 95 size_t name_len; /* Length of name buffer */ 96 char *name; /* Name of driver */ 97 size_t date_len; /* Length of date buffer */ 98 char *date; /* User-space buffer to hold date */ 99 size_t desc_len; /* Length of desc buffer */ 100 char *desc; /* User-space buffer to hold desc */ 101} drm_version_t; 102 103typedef struct drm_unique { 104 size_t unique_len; /* Length of unique */ 105 char *unique; /* Unique name for driver instantiation */ 106} drm_unique_t; 107 108typedef struct drm_list { 109 int count; /* Length of user-space structures */ 110 drm_version_t *version; 111} drm_list_t; 112 113typedef struct drm_block { 114 int unused; 115} drm_block_t; 116 117typedef struct drm_control { 118 enum { 119 DRM_ADD_COMMAND, 120 DRM_RM_COMMAND, 121 DRM_INST_HANDLER, 122 DRM_UNINST_HANDLER 123 } func; 124 int irq; 125} drm_control_t; 126 127typedef enum drm_map_type { 128 _DRM_FRAME_BUFFER = 0, /* WC (no caching), no core dump */ 129 _DRM_REGISTERS = 1, /* no caching, no core dump */ 130 _DRM_SHM = 2, /* shared, cached */ 131 _DRM_AGP = 3 /* AGP/GART */ 132} drm_map_type_t; 133 134typedef enum drm_map_flags { 135 _DRM_RESTRICTED = 0x01, /* Cannot be mapped to user-virtual */ 136 _DRM_READ_ONLY = 0x02, 137 _DRM_LOCKED = 0x04, /* shared, cached, locked */ 138 _DRM_KERNEL = 0x08, /* kernel requires access */ 139 _DRM_WRITE_COMBINING = 0x10, /* use write-combining if available */ 140 _DRM_CONTAINS_LOCK = 0x20 /* SHM page that contains lock */ 141} drm_map_flags_t; 142 143typedef struct drm_map { 144 unsigned long offset; /* Requested physical address (0 for SAREA)*/ 145 unsigned long size; /* Requested physical size (bytes) */ 146 drm_map_type_t type; /* Type of memory to map */ 147 drm_map_flags_t flags; /* Flags */ 148 void *handle; /* User-space: "Handle" to pass to mmap */ 149 /* Kernel-space: kernel-virtual address */ 150 int mtrr; /* MTRR slot used */ 151 /* Private data */ 152} drm_map_t; 153 154typedef enum drm_lock_flags { 155 _DRM_LOCK_READY = 0x01, /* Wait until hardware is ready for DMA */ 156 _DRM_LOCK_QUIESCENT = 0x02, /* Wait until hardware quiescent */ 157 _DRM_LOCK_FLUSH = 0x04, /* Flush this context's DMA queue first */ 158 _DRM_LOCK_FLUSH_ALL = 0x08, /* Flush all DMA queues first */ 159 /* These *HALT* flags aren't supported yet 160 -- they will be used to support the 161 full-screen DGA-like mode. */ 162 _DRM_HALT_ALL_QUEUES = 0x10, /* Halt all current and future queues */ 163 _DRM_HALT_CUR_QUEUES = 0x20 /* Halt all current queues */ 164} drm_lock_flags_t; 165 166typedef struct drm_lock { 167 int context; 168 drm_lock_flags_t flags; 169} drm_lock_t; 170 171typedef enum drm_dma_flags { /* These values *MUST* match xf86drm.h */ 172 /* Flags for DMA buffer dispatch */ 173 _DRM_DMA_BLOCK = 0x01, /* Block until buffer dispatched. 174 Note, the buffer may not yet have 175 been processed by the hardware -- 176 getting a hardware lock with the 177 hardware quiescent will ensure 178 that the buffer has been 179 processed. */ 180 _DRM_DMA_WHILE_LOCKED = 0x02, /* Dispatch while lock held */ 181 _DRM_DMA_PRIORITY = 0x04, /* High priority dispatch */ 182 183 /* Flags for DMA buffer request */ 184 _DRM_DMA_WAIT = 0x10, /* Wait for free buffers */ 185 _DRM_DMA_SMALLER_OK = 0x20, /* Smaller-than-requested buffers ok */ 186 _DRM_DMA_LARGER_OK = 0x40 /* Larger-than-requested buffers ok */ 187} drm_dma_flags_t; 188 189typedef struct drm_buf_desc { 190 int count; /* Number of buffers of this size */ 191 int size; /* Size in bytes */ 192 int low_mark; /* Low water mark */ 193 int high_mark; /* High water mark */ 194 enum { 195 _DRM_PAGE_ALIGN = 0x01, /* Align on page boundaries for DMA */ 196 _DRM_AGP_BUFFER = 0x02 /* Buffer is in agp space */ 197 } flags; 198 unsigned long agp_start; /* Start address of where the agp buffers 199 * are in the agp aperture */ 200} drm_buf_desc_t; 201 202typedef struct drm_buf_info { 203 int count; /* Entries in list */ 204 drm_buf_desc_t *list; 205} drm_buf_info_t; 206 207typedef struct drm_buf_free { 208 int count; 209 int *list; 210} drm_buf_free_t; 211 212typedef struct drm_buf_pub { 213 int idx; /* Index into master buflist */ 214 int total; /* Buffer size */ 215 int used; /* Amount of buffer in use (for DMA) */ 216 void *address; /* Address of buffer */ 217} drm_buf_pub_t; 218 219typedef struct drm_buf_map { 220 int count; /* Length of buflist */ 221 void *virtual; /* Mmaped area in user-virtual */ 222 drm_buf_pub_t *list; /* Buffer information */ 223} drm_buf_map_t; 224 225typedef struct drm_dma { 226 /* Indices here refer to the offset into 227 buflist in drm_buf_get_t. */ 228 int context; /* Context handle */ 229 int send_count; /* Number of buffers to send */ 230 int *send_indices; /* List of handles to buffers */ 231 int *send_sizes; /* Lengths of data to send */ 232 drm_dma_flags_t flags; /* Flags */ 233 int request_count; /* Number of buffers requested */ 234 int request_size; /* Desired size for buffers */ 235 int *request_indices; /* Buffer information */ 236 int *request_sizes; 237 int granted_count; /* Number of buffers granted */ 238} drm_dma_t; 239 240typedef enum { 241 _DRM_CONTEXT_PRESERVED = 0x01, 242 _DRM_CONTEXT_2DONLY = 0x02 243} drm_ctx_flags_t; 244 245typedef struct drm_ctx { 246 drm_context_t handle; 247 drm_ctx_flags_t flags; 248} drm_ctx_t; 249 250typedef struct drm_ctx_res { 251 int count; 252 drm_ctx_t *contexts; 253} drm_ctx_res_t; 254 255typedef struct drm_draw { 256 drm_drawable_t handle; 257} drm_draw_t; 258 259typedef struct drm_auth { 260 drm_magic_t magic; 261} drm_auth_t; 262 263typedef struct drm_irq_busid { 264 int irq; 265 int busnum; 266 int devnum; 267 int funcnum; 268} drm_irq_busid_t; 269 270typedef struct drm_agp_mode { 271 unsigned long mode; 272} drm_agp_mode_t; 273 274 /* For drm_agp_alloc -- allocated a buffer */ 275typedef struct drm_agp_buffer { 276 unsigned long size; /* In bytes -- will round to page boundary */ 277 unsigned long handle; /* Used for BIND/UNBIND ioctls */ 278 unsigned long type; /* Type of memory to allocate */ 279 unsigned long physical; /* Physical used by i810 */ 280} drm_agp_buffer_t; 281 282 /* For drm_agp_bind */ 283typedef struct drm_agp_binding { 284 unsigned long handle; /* From drm_agp_buffer */ 285 unsigned long offset; /* In bytes -- will round to page boundary */ 286} drm_agp_binding_t; 287 288typedef struct drm_agp_info { 289 int agp_version_major; 290 int agp_version_minor; 291 unsigned long mode; 292 unsigned long aperture_base; /* physical address */ 293 unsigned long aperture_size; /* bytes */ 294 unsigned long memory_allowed; /* bytes */ 295 unsigned long memory_used; 296 297 /* PCI information */ 298 unsigned short id_vendor; 299 unsigned short id_device; 300} drm_agp_info_t; 301 302#define DRM_IOCTL_BASE 'd' 303#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 304#define DRM_IOR(nr,size) _IOR(DRM_IOCTL_BASE,nr,size) 305#define DRM_IOW(nr,size) _IOW(DRM_IOCTL_BASE,nr,size) 306#define DRM_IOWR(nr,size) _IOWR(DRM_IOCTL_BASE,nr,size) 307 308 309#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) 310#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) 311#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) 312#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) 313 314#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) 315#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) 316#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) 317#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) 318#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) 319#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) 320#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) 321#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) 322#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) 323#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) 324#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) 325 326#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) 327#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) 328#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) 329#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) 330#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) 331#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) 332#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) 333#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) 334#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) 335#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) 336#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) 337#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) 338#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) 339 340#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 341#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 342#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) 343#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) 344#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) 345#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) 346#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) 347#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) 348 349/* Mga specific ioctls */ 350#define DRM_IOCTL_MGA_INIT DRM_IOW( 0x40, drm_mga_init_t) 351#define DRM_IOCTL_MGA_SWAP DRM_IOW( 0x41, drm_mga_swap_t) 352#define DRM_IOCTL_MGA_CLEAR DRM_IOW( 0x42, drm_mga_clear_t) 353#define DRM_IOCTL_MGA_ILOAD DRM_IOW( 0x43, drm_mga_iload_t) 354#define DRM_IOCTL_MGA_VERTEX DRM_IOW( 0x44, drm_mga_vertex_t) 355#define DRM_IOCTL_MGA_FLUSH DRM_IOW( 0x45, drm_lock_t ) 356#define DRM_IOCTL_MGA_INDICES DRM_IOW( 0x46, drm_mga_indices_t) 357#define DRM_IOCTL_MGA_BLIT DRM_IOW( 0x47, drm_mga_blit_t) 358 359/* I810 specific ioctls */ 360#define DRM_IOCTL_I810_INIT DRM_IOW( 0x40, drm_i810_init_t) 361#define DRM_IOCTL_I810_VERTEX DRM_IOW( 0x41, drm_i810_vertex_t) 362#define DRM_IOCTL_I810_CLEAR DRM_IOW( 0x42, drm_i810_clear_t) 363#define DRM_IOCTL_I810_FLUSH DRM_IO( 0x43) 364#define DRM_IOCTL_I810_GETAGE DRM_IO( 0x44) 365#define DRM_IOCTL_I810_GETBUF DRM_IOWR(0x45, drm_i810_dma_t) 366#define DRM_IOCTL_I810_SWAP DRM_IO( 0x46) 367#define DRM_IOCTL_I810_COPY DRM_IOW( 0x47, drm_i810_copy_t) 368#define DRM_IOCTL_I810_DOCOPY DRM_IO( 0x48) 369 370/* Rage 128 specific ioctls */ 371#define DRM_IOCTL_R128_INIT DRM_IOW( 0x40, drm_r128_init_t) 372#define DRM_IOCTL_R128_CCE_START DRM_IO( 0x41) 373#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( 0x42, drm_r128_cce_stop_t) 374#define DRM_IOCTL_R128_CCE_RESET DRM_IO( 0x43) 375#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( 0x44) 376#define DRM_IOCTL_R128_RESET DRM_IO( 0x46) 377#define DRM_IOCTL_R128_SWAP DRM_IO( 0x47) 378#define DRM_IOCTL_R128_CLEAR DRM_IOW( 0x48, drm_r128_clear_t) 379#define DRM_IOCTL_R128_VERTEX DRM_IOW( 0x49, drm_r128_vertex_t) 380#define DRM_IOCTL_R128_INDICES DRM_IOW( 0x4a, drm_r128_indices_t) 381#define DRM_IOCTL_R128_BLIT DRM_IOW( 0x4b, drm_r128_blit_t) 382#define DRM_IOCTL_R128_DEPTH DRM_IOW( 0x4c, drm_r128_depth_t) 383#define DRM_IOCTL_R128_STIPPLE DRM_IOW( 0x4d, drm_r128_stipple_t) 384#define DRM_IOCTL_R128_PACKET DRM_IOWR(0x4e, drm_r128_packet_t) 385 386/* Radeon specific ioctls */ 387#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t) 388#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41) 389#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t) 390#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43) 391#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44) 392#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45) 393#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t) 394#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47) 395#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t) 396#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t) 397#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t) 398#define DRM_IOCTL_RADEON_BLIT DRM_IOW( 0x4b, drm_radeon_blit_t) 399#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t) 400#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t) 401 402#ifdef CONFIG_DRM40_SIS 403/* SiS specific ioctls */ 404#define SIS_IOCTL_FB_ALLOC DRM_IOWR(0x44, drm_sis_mem_t) 405#define SIS_IOCTL_FB_FREE DRM_IOW( 0x45, drm_sis_mem_t) 406#define SIS_IOCTL_AGP_INIT DRM_IOWR(0x53, drm_sis_agp_t) 407#define SIS_IOCTL_AGP_ALLOC DRM_IOWR(0x54, drm_sis_mem_t) 408#define SIS_IOCTL_AGP_FREE DRM_IOW( 0x55, drm_sis_mem_t) 409#define SIS_IOCTL_FLIP DRM_IOW( 0x48, drm_sis_flip_t) 410#define SIS_IOCTL_FLIP_INIT DRM_IO( 0x49) 411#define SIS_IOCTL_FLIP_FINAL DRM_IO( 0x50) 412#endif 413 414#endif 415