1/*
2 * Begin 765/766
3 */
4/* C2/C3/POS options in C3A50, page 63 in AMD-766 doc */
5#define ZZ_CACHE_EN	1
6#define DCSTOP_EN	(1 << 1)
7#define STPCLK_EN	(1 << 2)
8#define CPUSTP_EN	(1 << 3)
9#define PCISTP_EN	(1 << 4)
10#define CPUSLP_EN	(1 << 5)
11#define SUSPND_EN	(1 << 6)
12#define CPURST_EN	(1 << 7)
13
14#define C2_REGS		0
15#define C3_REGS		8
16#define POS_REGS	16
17/*
18 * End 765/766
19 */
20
21
22/*
23 * Begin 768
24 */
25/* C2/C3 options in DevB:3x4F, page 100 in AMD-768 doc */
26#define C2EN		1
27#define C3EN		(1 << 1)
28#define ZZ_C3EN		(1 << 2)
29#define CSLP_C3EN	(1 << 3)
30#define CSTP_C3EN	(1 << 4)
31
32/* POS options in DevB:3x50, page 101 in AMD-768 doc */
33#define POSEN	1
34#define CSTP	(1 << 2)
35#define PSTP	(1 << 3)
36#define ASTP	(1 << 4)
37#define DCSTP	(1 << 5)
38#define CSLP	(1 << 6)
39#define SUSP	(1 << 8)
40#define MSRSM	(1 << 14)
41#define PITRSM	(1 << 15)
42
43/* NTH options DevB:3x40, pg 93 of 768 doc */
44#define NTPER(x) (x << 3)
45#define THMINEN(x) (x << 4)
46
47/*
48 * End 768
49 */
50
51/* NTH activate. PM10, pg 110 of 768 doc, pg 70 of 766 doc */
52#define NTH_RATIO(x) (x << 1)
53#define NTH_EN (1 << 4)
54
55/* Sleep state. PM04, pg 109 of 768 doc, pg 69 of 766 doc */
56#define SLP_EN (1 << 13)
57#define SLP_TYP(x) (x << 10)
58
59#define LAZY_IDLE_DELAY	800	/* 0: Best savings,  3000: More responsive */
60