1/* 2 * Disk Array driver for Compaq SMART2 Controllers 3 * Copyright 1998 Compaq Computer Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 * 19 * Questions/Comments/Bugfixes to arrays@compaq.com 20 * 21 */ 22#ifndef ARRAYCMD_H 23#define ARRAYCMD_H 24 25#include <asm/types.h> 26 27/* for the Smart Array 42XX cards */ 28#define S42XX_REQUEST_PORT_OFFSET 0x40 29#define S42XX_REPLY_INTR_MASK_OFFSET 0x34 30#define S42XX_REPLY_PORT_OFFSET 0x44 31#define S42XX_INTR_STATUS 0x30 32 33#define S42XX_INTR_OFF 0x08 34#define S42XX_INTR_PENDING 0x08 35 36#define COMMAND_FIFO 0x04 37#define COMMAND_COMPLETE_FIFO 0x08 38#define INTR_MASK 0x0C 39#define INTR_STATUS 0x10 40#define INTR_PENDING 0x14 41 42#define FIFO_NOT_EMPTY 0x01 43#define FIFO_NOT_FULL 0x02 44 45#define BIG_PROBLEM 0x40 46#define LOG_NOT_CONF 2 47 48#pragma pack(1) 49typedef struct { 50 __u32 size; 51 __u32 addr; 52} sg_t; 53 54#define RCODE_NONFATAL 0x02 55#define RCODE_FATAL 0x04 56#define RCODE_INVREQ 0x10 57typedef struct { 58 __u16 next; 59 __u8 cmd; 60 __u8 rcode; 61 __u32 blk; 62 __u16 blk_cnt; 63 __u8 sg_cnt; 64 __u8 reserved; 65} rhdr_t; 66 67#define SG_MAX 32 68typedef struct { 69 rhdr_t hdr; 70 sg_t sg[SG_MAX]; 71 __u32 bp; 72} rblk_t; 73 74typedef struct { 75 __u8 unit; 76 __u8 prio; 77 __u16 size; 78} chdr_t; 79 80#define CMD_RWREQ 0x00 81#define CMD_IOCTL_PEND 0x01 82#define CMD_IOCTL_DONE 0x02 83 84typedef struct cmdlist { 85 chdr_t hdr; 86 rblk_t req; 87 __u32 size; 88 int retry_cnt; 89 __u32 busaddr; 90 int ctlr; 91 struct cmdlist *prev; 92 struct cmdlist *next; 93 struct request *rq; 94 int type; 95} cmdlist_t; 96 97#define ID_CTLR 0x11 98typedef struct { 99 __u8 nr_drvs; 100 __u32 cfg_sig; 101 __u8 firm_rev[4]; 102 __u8 rom_rev[4]; 103 __u8 hw_rev; 104 __u32 bb_rev; 105 __u32 drv_present_map; 106 __u32 ext_drv_map; 107 __u32 board_id; 108 __u8 cfg_error; 109 __u32 non_disk_bits; 110 __u8 bad_ram_addr; 111 __u8 cpu_rev; 112 __u8 pdpi_rev; 113 __u8 epic_rev; 114 __u8 wcxc_rev; 115 __u8 marketing_rev; 116 __u8 ctlr_flags; 117 __u8 host_flags; 118 __u8 expand_dis; 119 __u8 scsi_chips; 120 __u32 max_req_blocks; 121 __u32 ctlr_clock; 122 __u8 drvs_per_bus; 123 __u16 big_drv_present_map[8]; 124 __u16 big_ext_drv_map[8]; 125 __u16 big_non_disk_map[8]; 126 __u16 task_flags; 127 __u8 icl_bus; 128 __u8 red_modes; 129 __u8 cur_red_mode; 130 __u8 red_ctlr_stat; 131 __u8 red_fail_reason; 132 __u8 reserved[403]; 133} id_ctlr_t; 134 135typedef struct { 136 __u16 cyl; 137 __u8 heads; 138 __u8 xsig; 139 __u8 psectors; 140 __u16 wpre; 141 __u8 maxecc; 142 __u8 drv_ctrl; 143 __u16 pcyls; 144 __u8 pheads; 145 __u16 landz; 146 __u8 sect_per_track; 147 __u8 cksum; 148} drv_param_t; 149 150#define ID_LOG_DRV 0x10 151typedef struct { 152 __u16 blk_size; 153 __u32 nr_blks; 154 drv_param_t drv; 155 __u8 fault_tol; 156 __u8 reserved; 157 __u8 bios_disable; 158} id_log_drv_t; 159 160#define ID_LOG_DRV_EXT 0x18 161typedef struct { 162 __u32 log_drv_id; 163 __u8 log_drv_label[64]; 164 __u8 reserved[418]; 165} id_log_drv_ext_t; 166 167#define SENSE_LOG_DRV_STAT 0x12 168typedef struct { 169 __u8 status; 170 __u32 fail_map; 171 __u16 read_err[32]; 172 __u16 write_err[32]; 173 __u8 drv_err_data[256]; 174 __u8 drq_timeout[32]; 175 __u32 blks_to_recover; 176 __u8 drv_recovering; 177 __u16 remap_cnt[32]; 178 __u32 replace_drv_map; 179 __u32 act_spare_map; 180 __u8 spare_stat; 181 __u8 spare_repl_map[32]; 182 __u32 repl_ok_map; 183 __u8 media_exch; 184 __u8 cache_fail; 185 __u8 expn_fail; 186 __u8 unit_flags; 187 __u16 big_fail_map[8]; 188 __u16 big_remap_map[128]; 189 __u16 big_repl_map[8]; 190 __u16 big_act_spare_map[8]; 191 __u8 big_spar_repl_map[128]; 192 __u16 big_repl_ok_map[8]; 193 __u8 big_drv_rebuild; 194 __u8 reserved[36]; 195} sense_log_drv_stat_t; 196 197#define START_RECOVER 0x13 198 199#define ID_PHYS_DRV 0x15 200typedef struct { 201 __u8 scsi_bus; 202 __u8 scsi_id; 203 __u16 blk_size; 204 __u32 nr_blks; 205 __u32 rsvd_blks; 206 __u8 drv_model[40]; 207 __u8 drv_sn[40]; 208 __u8 drv_fw[8]; 209 __u8 scsi_iq_bits; 210 __u8 compaq_drv_stmp; 211 __u8 last_fail; 212 __u8 phys_drv_flags; 213 __u8 phys_drv_flags1; 214 __u8 scsi_lun; 215 __u8 phys_drv_flags2; 216 __u8 reserved; 217 __u32 spi_speed_rules; 218 __u8 phys_connector[2]; 219 __u8 phys_box_on_bus; 220 __u8 phys_bay_in_box; 221} id_phys_drv_t; 222 223#define BLINK_DRV_LEDS 0x16 224typedef struct { 225 __u32 blink_duration; 226 __u32 reserved; 227 __u8 blink[256]; 228 __u8 reserved1[248]; 229} blink_drv_leds_t; 230 231#define SENSE_BLINK_LEDS 0x17 232typedef struct { 233 __u32 blink_duration; 234 __u32 btime_elap; 235 __u8 blink[256]; 236 __u8 reserved1[248]; 237} sense_blink_leds_t; 238 239#define IDA_READ 0x20 240#define IDA_WRITE 0x30 241#define IDA_WRITE_MEDIA 0x31 242#define RESET_TO_DIAG 0x40 243#define DIAG_PASS_THRU 0x41 244 245#define SENSE_CONFIG 0x50 246#define SET_CONFIG 0x51 247typedef struct { 248 __u32 cfg_sig; 249 __u16 compat_port; 250 __u8 data_dist_mode; 251 __u8 surf_an_ctrl; 252 __u16 ctlr_phys_drv; 253 __u16 log_unit_phys_drv; 254 __u16 fault_tol_mode; 255 __u8 phys_drv_param[16]; 256 drv_param_t drv; 257 __u32 drv_asgn_map; 258 __u16 dist_factor; 259 __u32 spare_asgn_map; 260 __u8 reserved[6]; 261 __u16 os; 262 __u8 ctlr_order; 263 __u8 extra_info; 264 __u32 data_offs; 265 __u8 parity_backedout_write_drvs; 266 __u8 parity_dist_mode; 267 __u8 parity_shift_fact; 268 __u8 bios_disable_flag; 269 __u32 blks_on_vol; 270 __u32 blks_per_drv; 271 __u8 scratch[16]; 272 __u16 big_drv_map[8]; 273 __u16 big_spare_map[8]; 274 __u8 ss_source_vol; 275 __u8 mix_drv_cap_range; 276 struct { 277 __u16 big_drv_map[8]; 278 __u32 blks_per_drv; 279 __u16 fault_tol_mode; 280 __u16 dist_factor; 281 } MDC_range[4]; 282 __u8 reserved1[248]; 283} config_t; 284 285#define BYPASS_VOL_STATE 0x52 286#define SS_CREATE_VOL 0x53 287#define CHANGE_CONFIG 0x54 288#define SENSE_ORIG_CONF 0x55 289#define REORDER_LOG_DRV 0x56 290typedef struct { 291 __u8 old_units[32]; 292} reorder_log_drv_t; 293 294#define LABEL_LOG_DRV 0x57 295typedef struct { 296 __u8 log_drv_label[64]; 297} label_log_drv_t; 298 299#define SS_TO_VOL 0x58 300 301#define SET_SURF_DELAY 0x60 302typedef struct { 303 __u16 delay; 304 __u8 reserved[510]; 305} surf_delay_t; 306 307#define SET_OVERHEAT_DELAY 0x61 308typedef struct { 309 __u16 delay; 310} overhead_delay_t; 311 312#define SET_MP_DELAY 313typedef struct { 314 __u16 delay; 315 __u8 reserved[510]; 316} mp_delay_t; 317 318#define PASSTHRU_A 0x91 319typedef struct { 320 __u8 target; 321 __u8 bus; 322 __u8 lun; 323 __u32 timeout; 324 __u32 flags; 325 __u8 status; 326 __u8 error; 327 __u8 cdb_len; 328 __u8 sense_error; 329 __u8 sense_key; 330 __u32 sense_info; 331 __u8 sense_code; 332 __u8 sense_qual; 333 __u32 residual; 334 __u8 reserved[4]; 335 __u8 cdb[12]; 336} scsi_param_t; 337 338#define RESUME_BACKGROUND_ACTIVITY 0x99 339#define SENSE_CONTROLLER_PERFORMANCE 0xa8 340#define FLUSH_CACHE 0xc2 341#define COLLECT_BUFFER 0xd2 342#define READ_FLASH_ROM 0xf6 343#define WRITE_FLASH_ROM 0xf7 344#pragma pack() 345 346#endif /* ARRAYCMD_H */ 347