1/* 2 * Copyright 2001 MontaVista Software Inc. 3 * Author: jsun@mvista.com or jsun@junsun.net 4 * 5 * First-level interrupt dispatcher for ocelot board. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12#define __ASSEMBLY__ 13#include <linux/config.h> 14#include <asm/asm.h> 15#include <asm/mipsregs.h> 16#include <asm/addrspace.h> 17#include <asm/regdef.h> 18#include <asm/stackframe.h> 19 20/* 21 * first level interrupt dispatcher for ocelot board - 22 * We check for the timer first, then check PCI ints A and D. 23 * Then check for serial IRQ and fall through. 24 */ 25 .align 5 26 NESTED(ocelot_handle_int, PT_SIZE, sp) 27 SAVE_ALL 28 CLI 29 .set at 30 mfc0 t0, CP0_CAUSE 31 mfc0 t2, CP0_STATUS 32 33 and t0, t2 34 35 andi t1, t0, STATUSF_IP2 /* int0 hardware line */ 36 bnez t1, ll_pri_enet_irq 37 andi t1, t0, STATUSF_IP3 /* int1 hardware line */ 38 bnez t1, ll_sec_enet_irq 39 andi t1, t0, STATUSF_IP4 /* int2 hardware line */ 40 bnez t1, ll_uart_irq 41 andi t1, t0, STATUSF_IP5 /* int3 hardware line */ 42 bnez t1, ll_cpci_irq 43 andi t1, t0, STATUSF_IP6 /* int4 hardware line */ 44 bnez t1, ll_galileo_p0_irq 45 andi t1, t0, STATUSF_IP7 /* cpu timer */ 46 bnez t1, ll_cputimer_irq 47 48 /* now look at the extended interrupts */ 49 mfc0 t0, CP0_CAUSE 50 cfc0 t1, CP0_S1_INTCONTROL 51 52 /* shift the mask 8 bits left to line up the bits */ 53 sll t2, t1, 8 54 55 and t0, t2 56 srl t0, t0, 16 57 58 andi t1, t0, STATUSF_IP8 /* int6 hardware line */ 59 bnez t1, ll_galileo_p1_irq 60 andi t1, t0, STATUSF_IP9 /* int7 hardware line */ 61 bnez t1, ll_pmc_irq 62 andi t1, t0, STATUSF_IP10 /* int8 hardware line */ 63 bnez t1, ll_cpci_abcd_irq 64 andi t1, t0, STATUSF_IP11 /* int9 hardware line */ 65 bnez t1, ll_testpoint_irq 66 67 .set reorder 68 69 /* wrong alarm or masked ... */ 70 j spurious_interrupt 71 nop 72 END(ocelot_handle_int) 73 74 .align 5 75ll_pri_enet_irq: 76 li a0, 2 77 move a1, sp 78 jal do_IRQ 79 j ret_from_irq 80 81ll_sec_enet_irq: 82 li a0, 3 83 move a1, sp 84 jal do_IRQ 85 j ret_from_irq 86 87ll_uart_irq: 88 li a0, 4 89 move a1, sp 90 jal do_IRQ 91 j ret_from_irq 92 93ll_cpci_irq: 94 li a0, 5 95 move a1, sp 96 jal do_IRQ 97 j ret_from_irq 98 99ll_galileo_p0_irq: 100 li a0, 6 101 move a1, sp 102 jal do_IRQ 103 j ret_from_irq 104 105ll_cputimer_irq: 106 li a0, 7 107 move a1, sp 108 jal do_IRQ 109 j ret_from_irq 110 111ll_galileo_p1_irq: 112 li a0, 8 113 move a1, sp 114 jal do_IRQ 115 j ret_from_irq 116 117ll_pmc_irq: 118 li a0, 9 119 move a1, sp 120 jal do_IRQ 121 j ret_from_irq 122 123ll_cpci_abcd_irq: 124 li a0, 10 125 move a1, sp 126 jal do_IRQ 127 j ret_from_irq 128 129ll_testpoint_irq: 130 li a0, 11 131 move a1, sp 132 jal do_IRQ 133 j ret_from_irq 134