1/* 2 * Carsten Langgaard, carstenl@mips.com 3 * Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. 4 * 5 * ######################################################################## 6 * 7 * This program is free software; you can distribute it and/or modify it 8 * under the terms of the GNU General Public License (Version 2) as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 19 * 20 * ######################################################################## 21 * 22 * Setting up the clock on the MIPS boards. 23 * 24 */ 25 26#include <linux/config.h> 27#include <linux/init.h> 28#include <linux/kernel_stat.h> 29#include <linux/sched.h> 30#include <linux/spinlock.h> 31 32#include <asm/mipsregs.h> 33#include <asm/ptrace.h> 34#include <asm/hardirq.h> 35#include <asm/cpu.h> 36 37#include <linux/interrupt.h> 38#include <linux/timex.h> 39 40#include <asm/mips-boards/generic.h> 41#include <asm/mips-boards/prom.h> 42 43extern volatile unsigned long wall_jiffies; 44 45static unsigned long r4k_offset; /* Amount to increment compare reg each time */ 46static unsigned long r4k_cur; /* What counter should be at next timer irq */ 47extern rwlock_t xtime_lock; 48 49#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5) 50 51static char display_string[] = " LINUX ON SEAD "; 52 53static unsigned int display_count = 0; 54#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8) 55 56#define MIPS_CPU_TIMER_IRQ 7 57 58static unsigned int timer_tick_count=0; 59 60static inline void ack_r4ktimer(unsigned long newval) 61{ 62 write_c0_compare(newval); 63} 64 65/* 66 * There are a lot of conceptually broken versions of the MIPS timer interrupt 67 * handler floating around. This one is rather different, but the algorithm 68 * is provably more robust. 69 */ 70void mips_timer_interrupt(struct pt_regs *regs) 71{ 72 int cpu = smp_processor_id(); 73 int irq = MIPS_CPU_TIMER_IRQ; 74 75 irq_enter(cpu, irq); 76 77 do { 78 kstat.irqs[cpu][irq]++; 79 do_timer(regs); 80 81 if ((timer_tick_count++ % HZ) == 0) { 82 mips_display_message(&display_string[display_count++]); 83 if (display_count == MAX_DISPLAY_COUNT) 84 display_count = 0; 85 } 86 87 r4k_cur += r4k_offset; 88 ack_r4ktimer(r4k_cur); 89 90 } while (((unsigned long)read_c0_count() 91 - r4k_cur) < 0x7fffffff); 92 93 irq_exit(cpu, irq); 94 if (softirq_pending(cpu)) 95 do_softirq(); 96} 97 98/* 99 * Figure out the r4k offset, the amount to increment the compare 100 * register for each time tick. 101 */ 102static unsigned long __init cal_r4koff(void) 103{ 104 /* 105 * The SEAD board doesn't have a real time clock, so we can't 106 * really calculate the timer offset. 107 * For now we hardwire the SEAD board frequency to 12MHz. 108 */ 109 return(6000000/HZ); 110} 111 112void __init mips_time_init(void) 113{ 114 unsigned int est_freq, flags; 115 116 __save_and_cli(flags); 117 118 /* Start r4k counter. */ 119 write_c0_count(0); 120 121 printk("calculating r4koff... "); 122 r4k_offset = cal_r4koff(); 123 printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); 124 125 if ((read_c0_prid() & 0xffff00) == 126 (PRID_COMP_MIPS | PRID_IMP_20KC)) 127 est_freq = r4k_offset*HZ; 128 else 129 est_freq = 2*r4k_offset*HZ; 130 131 est_freq += 5000; /* round */ 132 est_freq -= est_freq%10000; 133 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 134 (est_freq%1000000)*100/1000000); 135 136 __restore_flags(flags); 137} 138 139void __init mips_timer_setup(struct irqaction *irq) 140{ 141 /* we are using the cpu counter for timer interrupts */ 142 irq->handler = no_action; /* we use our own handler */ 143 setup_irq(MIPS_CPU_TIMER_IRQ, irq); 144 145 /* to generate the first timer interrupt */ 146 r4k_cur = (read_c0_count() + r4k_offset); 147 write_c0_compare(r4k_cur); 148 set_c0_status(ALLINTS); 149} 150