1#include <linux/config.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/pci.h>
5#include <asm/bootinfo.h>
6
7#include <asm/lasat/lasat.h>
8#include <asm/gt64120.h>
9#include <asm/nile4.h>
10
11#define PCI_ACCESS_READ  0
12#define PCI_ACCESS_WRITE 1
13
14#undef DEBUG_PCI
15#ifdef DEBUG_PCI
16#define Dprintk(fmt...) printk(fmt)
17#else
18#define Dprintk(fmt...)
19#endif
20
21static int (*lasat_pcibios_config_access)(unsigned char access_type,
22				       struct pci_dev *dev,
23				       unsigned char reg,
24				       u32 *data);
25
26/*
27 * Because of an error/peculiarity in the Galileo chip, we need to swap the
28 * bytes when running bigendian.
29 */
30#define GT_WRITE(ofs, data)  \
31             *(volatile u32 *)(LASAT_GT_BASE+ofs) = cpu_to_le32(data)
32#define GT_READ(ofs, data)   \
33             data = le32_to_cpu(*(volatile u32 *)(LASAT_GT_BASE+ofs))
34
35
36static int lasat_pcibios_config_access_100(unsigned char access_type,
37				       struct pci_dev *dev,
38				       unsigned char reg,
39				       u32 *data)
40{
41	unsigned char bus = dev->bus->number;
42	unsigned char dev_fn = dev->devfn;
43        u32 intr;
44
45	if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0)))
46	        return -1; /* Because of a bug in the Galileo (for slot 31). */
47
48	/* Clear cause register bits */
49	GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
50				      GT_INTRCAUSE_TARABORT0_BIT) );
51
52	/* Setup address */
53	GT_WRITE( GT_PCI0_CFGADDR_OFS,
54		  (bus       << GT_PCI0_CFGADDR_BUSNUM_SHF) |
55		  (dev_fn    << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
56		  ((reg / 4) << GT_PCI0_CFGADDR_REGNUM_SHF)   |
57		  GT_PCI0_CFGADDR_CONFIGEN_BIT );
58
59	if (access_type == PCI_ACCESS_WRITE) {
60	        GT_WRITE( GT_PCI0_CFGDATA_OFS, *data );
61	} else {
62	        GT_READ( GT_PCI0_CFGDATA_OFS, *data );
63	}
64
65	/* Check for master or target abort */
66	GT_READ( GT_INTRCAUSE_OFS, intr );
67
68	if( intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT) )
69	{
70	        /* Error occured */
71
72	        /* Clear bits */
73	        GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
74					      GT_INTRCAUSE_TARABORT0_BIT) );
75
76		return -1;
77	}
78
79	return 0;
80}
81
82#define LO(reg) (reg / 4)
83#define HI(reg) (reg / 4 + 1)
84
85volatile unsigned long * const vrc_pciregs = (void *)Vrc5074_BASE;
86
87static int lasat_pcibios_config_access_200(unsigned char access_type,
88				       struct pci_dev *dev,
89				       unsigned char reg,
90				       u32 *data)
91{
92	unsigned char bus = dev->bus->number;
93	unsigned char dev_fn = dev->devfn;
94	u32 adr, mask, err;
95
96	if ((bus == 0) && (PCI_SLOT(dev_fn) > 8))
97		/* The addressing scheme chosen leaves room for just
98		 * 8 devices on the first bus (besides the PCI
99		 * controller itself) */
100		return -1;
101
102	if ((bus == 0) && (dev_fn == PCI_DEVFN(0,0))) {
103		/* Access controller registers directly */
104		if (access_type == PCI_ACCESS_WRITE) {
105			vrc_pciregs[(0x200+reg) >> 2] = *data;
106		} else {
107			*data = vrc_pciregs[(0x200+reg) >> 2];
108		}
109	        return 0;
110	}
111
112	/* Temporarily map PCI Window 1 to config space */
113	mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
114	vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (bus ? 0x200 : 0);
115
116	/* Clear PCI Error register. This also clears the Error Type
117	 * bits in the Control register */
118	vrc_pciregs[LO(NILE4_PCIERR)] = 0;
119	vrc_pciregs[HI(NILE4_PCIERR)] = 0;
120
121	/* Setup address */
122	if (bus == 0)
123	        adr = KSEG1ADDR(PCI_WINDOW1) + ((1 << (PCI_SLOT(dev_fn) + 15)) | (PCI_FUNC(dev_fn) << 8) | (reg & ~3));
124	else
125	        adr = KSEG1ADDR(PCI_WINDOW1) | (bus << 16) | (dev_fn << 8) | (reg & ~3);
126
127#ifdef DEBUG_PCI
128	printk("PCI config %s: adr %x", access_type == PCI_ACCESS_WRITE ? "write" : "read", adr);
129#endif
130
131	if (access_type == PCI_ACCESS_WRITE) {
132	        *(u32 *)adr = *data;
133	} else {
134	        *data = *(u32 *)adr;
135	}
136
137#ifdef DEBUG_PCI
138	printk(" value = %x\n", *data);
139#endif
140
141	/* Check for master or target abort */
142	err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
143
144	/* Restore PCI Window 1 */
145	vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
146
147	if (err)
148	{
149		/* Error occured */
150#ifdef DEBUG_PCI
151	        printk("\terror %x at adr %x\n", err, vrc_pciregs[LO(PCIERR)]);
152#endif
153		return -1;
154	}
155
156	return 0;
157}
158
159/*
160 * We can't address 8 and 16 bit words directly.  Instead we have to
161 * read/write a 32bit word and mask/modify the data we actually want.
162 */
163static int lasat_pcibios_read_config_byte(struct pci_dev *dev, int reg, u8 *val)
164{
165        u32 data=0, flags;
166
167	save_and_cli(flags);
168
169	if (lasat_pcibios_config_access(PCI_ACCESS_READ, dev, reg, &data)) {
170		restore_flags(flags);
171		return -1;
172	}
173
174	*val = (data >> ((reg & 3) << 3)) & 0xff;
175
176	restore_flags(flags);
177	return PCIBIOS_SUCCESSFUL;
178}
179
180
181static int lasat_pcibios_read_config_word(struct pci_dev *dev, int reg, u16 *val)
182{
183        u32 data=0, flags;
184
185	if (reg & 1)
186		return PCIBIOS_BAD_REGISTER_NUMBER;
187
188	save_and_cli(flags);
189
190	if (lasat_pcibios_config_access(PCI_ACCESS_READ, dev, reg, &data)) {
191		restore_flags(flags);
192		return -1;
193	}
194
195	*val = (data >> ((reg & 3) << 3)) & 0xffff;
196
197	restore_flags(flags);
198	return PCIBIOS_SUCCESSFUL;
199}
200
201static int lasat_pcibios_read_config_dword(struct pci_dev *dev, int reg, u32 *val)
202{
203        u32 data=0, flags;
204
205	if (reg & 3)
206		return PCIBIOS_BAD_REGISTER_NUMBER;
207
208	save_and_cli(flags);
209
210	if (lasat_pcibios_config_access(PCI_ACCESS_READ, dev, reg, &data)) {
211		restore_flags(flags);
212		return -1;
213	}
214
215	*val = data;
216
217	restore_flags(flags);
218	return PCIBIOS_SUCCESSFUL;
219}
220
221
222static int lasat_pcibios_write_config_byte(struct pci_dev *dev, int reg, u8 val)
223{
224        u32 data=0, flags, err;
225
226	save_and_cli(flags);
227
228        err = lasat_pcibios_config_access(PCI_ACCESS_READ, dev, reg, &data);
229        if (err)
230		goto out;
231
232	data = (data & ~(0xff << ((reg & 3) << 3))) |
233		(val << ((reg & 3) << 3));
234
235	err = lasat_pcibios_config_access(PCI_ACCESS_WRITE, dev, reg, &data);
236out:
237	restore_flags(flags);
238
239	if (err)
240		return -1;
241	else
242		return PCIBIOS_SUCCESSFUL;
243}
244
245static int lasat_pcibios_write_config_word(struct pci_dev *dev, int reg, u16 val)
246{
247	u32 data=0, flags, err;
248
249	if (reg & 1)
250		return PCIBIOS_BAD_REGISTER_NUMBER;
251
252	save_and_cli(flags);
253
254        err = lasat_pcibios_config_access(PCI_ACCESS_READ, dev, reg, &data);
255        if (err)
256	       goto out;
257
258	data = (data & ~(0xffff << ((reg & 3) << 3))) |
259	       (val << ((reg & 3) << 3));
260
261	err = lasat_pcibios_config_access(PCI_ACCESS_WRITE, dev, reg, &data);
262out:
263	restore_flags(flags);
264
265	if (err)
266		return -1;
267	else
268		return PCIBIOS_SUCCESSFUL;
269}
270
271static int lasat_pcibios_write_config_dword(struct pci_dev *dev, int reg, u32 val)
272{
273        u32 flags, err;
274
275	if (reg & 3)
276		return PCIBIOS_BAD_REGISTER_NUMBER;
277
278	save_and_cli(flags);
279
280	err = lasat_pcibios_config_access(PCI_ACCESS_WRITE, dev, reg, &val);
281	restore_flags(flags);
282
283	if (err)
284		return -1;
285	else
286		return PCIBIOS_SUCCESSFUL;
287}
288
289struct pci_ops lasat_pci_ops = {
290	lasat_pcibios_read_config_byte,
291	lasat_pcibios_read_config_word,
292	lasat_pcibios_read_config_dword,
293	lasat_pcibios_write_config_byte,
294	lasat_pcibios_write_config_word,
295	lasat_pcibios_write_config_dword
296};
297
298char * __init pcibios_setup(char *str)
299{
300	return str;
301}
302
303void __init pcibios_init(void)
304{
305	switch (mips_machtype) {
306	case MACH_LASAT_100:
307		lasat_pcibios_config_access = &lasat_pcibios_config_access_100;
308		break;
309	case MACH_LASAT_200:
310		lasat_pcibios_config_access = &lasat_pcibios_config_access_200;
311		break;
312	default:
313		panic("pcibios_init: mips_machtype incorrect");
314	}
315
316	Dprintk("pcibios_init()\n");
317	pci_scan_bus(0, &lasat_pci_ops, NULL);
318}
319
320void __init pcibios_fixup_bus(struct pci_bus *b)
321{
322	Dprintk("pcibios_fixup_bus()\n");
323}
324
325void pcibios_update_resource(struct pci_dev *dev, struct resource *root,
326			     struct resource *res, int resource)
327{
328}
329
330int __init pcibios_enable_device(struct pci_dev *dev, int mask)
331{
332	/* Not needed, since we enable all devices at startup.  */
333	return 0;
334}
335
336void __init pcibios_align_resource(void *data, struct resource *res,
337	unsigned long size, unsigned long align)
338{
339}
340
341unsigned __init int pcibios_assign_all_busses(void)
342{
343	return 1;
344}
345
346struct pci_fixup pcibios_fixups[] = {
347	{ 0 }
348};
349