1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * ITE 8172G interrupt/setup routines. 5 * 6 * Copyright 2000,2001 MontaVista Software Inc. 7 * Author: MontaVista Software, Inc. 8 * ppopov@mvista.com or source@mvista.com 9 * 10 * Part of this file was derived from Carsten Langgaard's 11 * arch/mips/mips-boards/atlas/atlas_int.c. 12 * 13 * Carsten Langgaard, carstenl@mips.com 14 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. 15 * 16 * This program is free software; you can redistribute it and/or modify it 17 * under the terms of the GNU General Public License as published by the 18 * Free Software Foundation; either version 2 of the License, or (at your 19 * option) any later version. 20 * 21 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * You should have received a copy of the GNU General Public License along 33 * with this program; if not, write to the Free Software Foundation, Inc., 34 * 675 Mass Ave, Cambridge, MA 02139, USA. 35 */ 36#include <linux/config.h> 37#include <linux/errno.h> 38#include <linux/init.h> 39#include <linux/kernel_stat.h> 40#include <linux/module.h> 41#include <linux/signal.h> 42#include <linux/sched.h> 43#include <linux/types.h> 44#include <linux/interrupt.h> 45#include <linux/ioport.h> 46#include <linux/timex.h> 47#include <linux/slab.h> 48#include <linux/random.h> 49#include <linux/serial_reg.h> 50 51#include <asm/bitops.h> 52#include <asm/bootinfo.h> 53#include <asm/io.h> 54#include <asm/mipsregs.h> 55#include <asm/system.h> 56#include <asm/it8172/it8172.h> 57#include <asm/it8172/it8172_int.h> 58#include <asm/it8172/it8172_dbg.h> 59 60#undef DEBUG_IRQ 61#ifdef DEBUG_IRQ 62/* note: prints function name for you */ 63#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args) 64#else 65#define DPRINTK(fmt, args...) 66#endif 67 68#ifdef CONFIG_REMOTE_DEBUG 69extern void breakpoint(void); 70#endif 71 72/* revisit */ 73#define EXT_IRQ0_TO_IP 2 /* IP 2 */ 74#define EXT_IRQ5_TO_IP 7 /* IP 7 */ 75 76#define ALLINTS_NOTIMER (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4) 77 78unsigned int local_bh_count[NR_CPUS]; 79unsigned int local_irq_count[NR_CPUS]; 80void disable_it8172_irq(unsigned int irq_nr); 81void enable_it8172_irq(unsigned int irq_nr); 82 83extern void set_debug_traps(void); 84extern void mips_timer_interrupt(int irq, struct pt_regs *regs); 85extern asmlinkage void it8172_IRQ(void); 86 87struct it8172_intc_regs volatile *it8172_hw0_icregs 88 = (struct it8172_intc_regs volatile *)(KSEG1ADDR(IT8172_PCI_IO_BASE + IT_INTC_BASE)); 89 90/* Function for careful CP0 interrupt mask access */ 91static inline void modify_cp0_intmask(unsigned clr_mask, unsigned set_mask) 92{ 93 unsigned long status = read_c0_status(); 94 status &= ~((clr_mask & 0xFF) << 8); 95 status |= (set_mask & 0xFF) << 8; 96 write_c0_status(status); 97} 98 99static inline void mask_irq(unsigned int irq_nr) 100{ 101 modify_cp0_intmask(irq_nr, 0); 102} 103 104static inline void unmask_irq(unsigned int irq_nr) 105{ 106 modify_cp0_intmask(0, irq_nr); 107} 108 109void local_disable_irq(unsigned int irq_nr) 110{ 111 unsigned long flags; 112 113 save_and_cli(flags); 114 disable_it8172_irq(irq_nr); 115 restore_flags(flags); 116} 117 118void local_enable_irq(unsigned int irq_nr) 119{ 120 unsigned long flags; 121 122 save_and_cli(flags); 123 enable_it8172_irq(irq_nr); 124 restore_flags(flags); 125} 126 127 128void disable_it8172_irq(unsigned int irq_nr) 129{ 130 DPRINTK("disable_it8172_irq %d\n", irq_nr); 131 132 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) { 133 /* LPC interrupt */ 134 DPRINTK("DB lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); 135 it8172_hw0_icregs->lpc_mask |= 136 (1 << (irq_nr - IT8172_LPC_IRQ_BASE)); 137 DPRINTK("DA lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); 138 } 139 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) { 140 /* Local Bus interrupt */ 141 DPRINTK("DB lb_mask %x\n", it8172_hw0_icregs->lb_mask); 142 it8172_hw0_icregs->lb_mask |= 143 (1 << (irq_nr - IT8172_LB_IRQ_BASE)); 144 DPRINTK("DA lb_mask %x\n", it8172_hw0_icregs->lb_mask); 145 } 146 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) { 147 /* PCI and other interrupts */ 148 DPRINTK("DB pci_mask %x\n", it8172_hw0_icregs->pci_mask); 149 it8172_hw0_icregs->pci_mask |= 150 (1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); 151 DPRINTK("DA pci_mask %x\n", it8172_hw0_icregs->pci_mask); 152 } 153 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) { 154 /* NMI interrupts */ 155 DPRINTK("DB nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); 156 it8172_hw0_icregs->nmi_mask |= 157 (1 << (irq_nr - IT8172_NMI_IRQ_BASE)); 158 DPRINTK("DA nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); 159 } 160 else { 161 panic("disable_it8172_irq: bad irq %d", irq_nr); 162 } 163} 164 165void enable_it8172_irq(unsigned int irq_nr) 166{ 167 DPRINTK("enable_it8172_irq %d\n", irq_nr); 168 if ( (irq_nr >= IT8172_LPC_IRQ_BASE) && (irq_nr <= IT8172_SERIRQ_15)) { 169 /* LPC interrupt */ 170 DPRINTK("EB before lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); 171 it8172_hw0_icregs->lpc_mask &= 172 ~(1 << (irq_nr - IT8172_LPC_IRQ_BASE)); 173 DPRINTK("EA after lpc_mask %x\n", it8172_hw0_icregs->lpc_mask); 174 } 175 else if ( (irq_nr >= IT8172_LB_IRQ_BASE) && (irq_nr <= IT8172_IOCHK_IRQ)) { 176 /* Local Bus interrupt */ 177 DPRINTK("EB lb_mask %x\n", it8172_hw0_icregs->lb_mask); 178 it8172_hw0_icregs->lb_mask &= 179 ~(1 << (irq_nr - IT8172_LB_IRQ_BASE)); 180 DPRINTK("EA lb_mask %x\n", it8172_hw0_icregs->lb_mask); 181 } 182 else if ( (irq_nr >= IT8172_PCI_DEV_IRQ_BASE) && (irq_nr <= IT8172_DMA_IRQ)) { 183 /* PCI and other interrupts */ 184 DPRINTK("EB pci_mask %x\n", it8172_hw0_icregs->pci_mask); 185 it8172_hw0_icregs->pci_mask &= 186 ~(1 << (irq_nr - IT8172_PCI_DEV_IRQ_BASE)); 187 DPRINTK("EA pci_mask %x\n", it8172_hw0_icregs->pci_mask); 188 } 189 else if ( (irq_nr >= IT8172_NMI_IRQ_BASE) && (irq_nr <= IT8172_POWER_NMI_IRQ)) { 190 /* NMI interrupts */ 191 DPRINTK("EB nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); 192 it8172_hw0_icregs->nmi_mask &= 193 ~(1 << (irq_nr - IT8172_NMI_IRQ_BASE)); 194 DPRINTK("EA nmi_mask %x\n", it8172_hw0_icregs->nmi_mask); 195 } 196 else { 197 panic("enable_it8172_irq: bad irq %d", irq_nr); 198 } 199} 200 201static unsigned int startup_ite_irq(unsigned int irq) 202{ 203 enable_it8172_irq(irq); 204 return 0; 205} 206 207#define shutdown_ite_irq disable_it8172_irq 208#define mask_and_ack_ite_irq disable_it8172_irq 209 210static void end_ite_irq(unsigned int irq) 211{ 212 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 213 enable_it8172_irq(irq); 214} 215 216static struct hw_interrupt_type it8172_irq_type = { 217 "ITE8172", 218 startup_ite_irq, 219 shutdown_ite_irq, 220 enable_it8172_irq, 221 disable_it8172_irq, 222 mask_and_ack_ite_irq, 223 end_ite_irq, 224 NULL 225}; 226 227 228static void enable_none(unsigned int irq) { } 229static unsigned int startup_none(unsigned int irq) { return 0; } 230static void disable_none(unsigned int irq) { } 231static void ack_none(unsigned int irq) { } 232 233/* startup is the same as "enable", shutdown is same as "disable" */ 234#define shutdown_none disable_none 235#define end_none enable_none 236 237static struct hw_interrupt_type cp0_irq_type = { 238 "CP0 Count", 239 startup_none, 240 shutdown_none, 241 enable_none, 242 disable_none, 243 ack_none, 244 end_none 245}; 246 247 248void enable_cpu_timer(void) 249{ 250 unsigned long flags; 251 252 save_and_cli(flags); 253 unmask_irq(1<<EXT_IRQ5_TO_IP); /* timer interrupt */ 254 restore_flags(flags); 255} 256 257 258void __init init_IRQ(void) 259{ 260 int i; 261 unsigned long flags; 262 263 memset(irq_desc, 0, sizeof(irq_desc)); 264 set_except_vector(0, it8172_IRQ); 265 266 init_generic_irq(); 267 268 /* mask all interrupts */ 269 it8172_hw0_icregs->lb_mask = 0xffff; 270 it8172_hw0_icregs->lpc_mask = 0xffff; 271 it8172_hw0_icregs->pci_mask = 0xffff; 272 it8172_hw0_icregs->nmi_mask = 0xffff; 273 274 /* make all interrupts level triggered */ 275 it8172_hw0_icregs->lb_trigger = 0; 276 it8172_hw0_icregs->lpc_trigger = 0; 277 it8172_hw0_icregs->pci_trigger = 0; 278 it8172_hw0_icregs->nmi_trigger = 0; 279 280 /* active level setting */ 281 /* uart, keyboard, and mouse are active high */ 282 it8172_hw0_icregs->lpc_level = (0x10 | 0x2 | 0x1000); 283 it8172_hw0_icregs->lb_level |= 0x20; 284 285 /* keyboard and mouse are edge triggered */ 286 it8172_hw0_icregs->lpc_trigger |= (0x2 | 0x1000); 287 288 289 290 for (i = 0; i <= IT8172_LAST_IRQ; i++) { 291 irq_desc[i].handler = &it8172_irq_type; 292 } 293 irq_desc[MIPS_CPU_TIMER_IRQ].handler = &cp0_irq_type; 294 set_c0_status(ALLINTS_NOTIMER); 295 296#ifdef CONFIG_REMOTE_DEBUG 297 /* If local serial I/O used for debug port, enter kgdb at once */ 298 puts("Waiting for kgdb to connect..."); 299 set_debug_traps(); 300 breakpoint(); 301#endif 302} 303 304void mips_spurious_interrupt(struct pt_regs *regs) 305{ 306 return; 307} 308 309void it8172_hw0_irqdispatch(struct pt_regs *regs) 310{ 311 int irq; 312 unsigned short intstatus = 0, status = 0; 313 314 intstatus = it8172_hw0_icregs->intstatus; 315 if (intstatus & 0x8) { 316 panic("Got NMI interrupt"); 317 } 318 else if (intstatus & 0x4) { 319 /* PCI interrupt */ 320 irq = 0; 321 status |= it8172_hw0_icregs->pci_req; 322 while (!(status & 0x1)) { 323 irq++; 324 status >>= 1; 325 } 326 irq += IT8172_PCI_DEV_IRQ_BASE; 327 //printk("pci int %d\n", irq); 328 } 329 else if (intstatus & 0x1) { 330 /* Local Bus interrupt */ 331 irq = 0; 332 status |= it8172_hw0_icregs->lb_req; 333 while (!(status & 0x1)) { 334 irq++; 335 status >>= 1; 336 } 337 irq += IT8172_LB_IRQ_BASE; 338 //printk("lb int %d\n", irq); 339 } 340 else if (intstatus & 0x2) { 341 /* LPC interrupt */ 342 /* Since some lpc interrupts are edge triggered, 343 * we could lose an interrupt this way because 344 * we acknowledge all ints at onces. Revisit. 345 */ 346 status |= it8172_hw0_icregs->lpc_req; 347 it8172_hw0_icregs->lpc_req = 0; /* acknowledge ints */ 348 irq = 0; 349 while (!(status & 0x1)) { 350 irq++; 351 status >>= 1; 352 } 353 irq += IT8172_LPC_IRQ_BASE; 354 //printk("LPC int %d\n", irq); 355 } 356 else { 357 return; 358 } 359 do_IRQ(irq, regs); 360} 361 362void show_pending_irqs(void) 363{ 364 fputs("intstatus: "); 365 put32(it8172_hw0_icregs->intstatus); 366 puts(""); 367 368 fputs("pci_req: "); 369 put32(it8172_hw0_icregs->pci_req); 370 puts(""); 371 372 fputs("lb_req: "); 373 put32(it8172_hw0_icregs->lb_req); 374 puts(""); 375 376 fputs("lpc_req: "); 377 put32(it8172_hw0_icregs->lpc_req); 378 puts(""); 379} 380