1/* 2 * Define BUSWIDTH to usually be real buswidth X 2 (i.e assuming 3 * 2-way interleaving). This is so that the test pattern and 4 * inverted pattern are written to the same bank of memory, which 5 * prevents us reading back data sitting in the dram buffers and 6 * getting a false match. 7 */ 8 9#ifndef BUSWIDTH 10# if #cpu(r3000) || #cpu(r4300) || #cpu(r4650) 11# define BUSWIDTH 8 /* 32 bit memory, bank interleaved */ 12# elif #cpu(r4000) 13# define BUSWIDTH 16 /* 64 bit memory, bank interleaved */ 14# endif 15#endif 16 17#ifndef RAM_BASE 18#define RAM_BASE KSEG1_BASE 19#endif 20 21#ifndef MEMSTART 22#define MEMSTART 0x0 /* start of physical memory */ 23#endif 24 25#ifndef MEMINCR 26# define MEMINCR 0x10000 /* work up in 64Kb increments */ 27#endif 28 29SLEAF(size_mem) 30 mfc0 t8,C0_STATUS 31#if #cpu(r4000) 32 /* disable cache and memory parity checking */ 33 or t0,t8,SR_DE 34 mtc0 t0,C0_STATUS 35#endif 36 37 li t0,RAM_BASE+MEMSTART # start at bottom of phys mem 38 move t1,t0 # remember start address 39 li t2,0xaa55aa55 # pattern 40 not t3,t2 # ~pattern 41 42 move t7,k0 43 la t4,.fail # bus error exception catcher 44 addu k0,t4,s8 # RELOC 45 46 /* fill first 64Kb with zero (for cache init) */ 47 move t4,t0 48 li t5,0x10000 491: sw zero,0(t4) 50 sw zero,4(t4) 51 sw zero,8(t4) 52 sw zero,12(t4) 53 subu t5,16 54 addu t4,16 55 bnez t5,1b 56 57.loop: 58 addu t0,MEMINCR 59 move t4,t0 60 61 /* store pattern in bank 0, line 0 */ 62 sw t2,0(t4) 63 addu t4,4 64 65#if BUSWIDTH > 4 66 /* fill remainder of line with zeros */ 67 li t5,BUSWIDTH-4 681: sw zero,0(t4) 69 subu t5,4 70 addu t4,4 71 bnez t5,1b 72#endif 73 74 /* store inverse pattern in bank 0, line 1 */ 75 sw t3,0(t4) 76 addu t4,4 77 78#if BUSWIDTH > 4 79 /* fill remainder of line with zeros */ 80 li t5,BUSWIDTH-4 811: sw zero,0(t4) 82 subu t5,4 83 addu t4,4 84 bnez t5,1b 85#endif 86 87 /* defeat write buffering */ 88#if #cpu(r4000) 89 sync 90#else 91 lw zero,-4(t4) 92#endif 93 94 lw t4,0(t0) # read first word of line 95 lw t5,0(t1) # read start of memory (should be zero) 96 bne t4,t2,.fail # this line wrong? 97 beq t5,zero,.loop # start of mem overwritten? 98 99.fail: 100 move k0,t7 # clear exception catcher 101 102 /* restore Status register */ 103 mtc0 t8,C0_STATUS 104 105 /* return top of memory offset (normally == size) */ 106 subu v0,t0,RAM_BASE 107 j ra 108END(size_mem) 109 110 111/* 112 * We must often initialise memory so that it has good parity/ecc, 113 * and this must be done before the caches are used. 114 */ 115 116/* 117 clear_mem (size) 118 - clear memory from RAM_BASE+MEMSTART to RAM_BASE+MEMSTART+size 119 clear_mem_range (size, start) 120 - clear memory from start to start+size 121*/ 122 123SLEAF(clear_mem) 124 li a1,RAM_BASE+MEMSTART # start at bottom of phys mem 125clear_mem_range: 126 beqz a0,9f 127 addu a0,a1 # end of memory 128 129 .set noreorder 130#if __mips >= 3 1311: sd zero,0(a1) 132 sd zero,8(a1) 133 sd zero,16(a1) 134 sd zero,24(a1) 135 sd zero,32(a1) 136 sd zero,40(a1) 137 sd zero,48(a1) 138 addu a1,64 139 bne a1,a0,1b 140 sd zero,-8(a1) # BDSLOT 141#else 1421: sw zero,0(a1) 143 sw zero,4(a1) 144 sw zero,8(a1) 145 sw zero,12(a1) 146 sw zero,16(a1) 147 sw zero,20(a1) 148 sw zero,24(a1) 149 sw zero,28(a1) 150 sw zero,32(a1) 151 sw zero,36(a1) 152 sw zero,40(a1) 153 sw zero,44(a1) 154 sw zero,48(a1) 155 sw zero,52(a1) 156 sw zero,56(a1) 157 addu a1,64 158 bne a1,a0,1b 159 sw zero,-4(a1) # BDSLOT 160#endif 161 .set reorder 162 1639: j ra 164END(clear_mem) 165 166 167SLEAF(init_tlb) 168 /* initialise tlb */ 169 mtc0 zero,C0_TLBLO0 /* tlblo0 = invalid */ 170 mtc0 zero,C0_TLBLO1 /* tlblo1 = invalid */ 171 mtc0 zero,C0_PGMASK 172 li t8,K1BASE /* tlbhi = impossible vpn */ 173 li t9,(NTLBENTRIES-1) /* index */ 174 175 .set noreorder 176 nop 1771: mtc0 t8,C0_TLBHI 178 mtc0 t9,C0_INX 179 addu t8,0x2000 /* inc vpn */ 180 tlbwi 181 bnez t9,1b 182 subu t9,1 # BDSLOT 183 .set reorder 184 185 j ra 186END(init_tlb) 187