1/* 2 * I/O Processor (IOP) management 3 * Written and (C) 1999 by Joshua M. Thompson (funaho@jurai.org) 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice and this list of conditions. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice and this list of conditions in the documentation and/or other 12 * materials provided with the distribution. 13 */ 14 15/* 16 * The IOP chips are used in the IIfx and some Quadras (900, 950) to manage 17 * serial and ADB. They are actually a 6502 processor and some glue logic. 18 * 19 * 990429 (jmt) - Initial implementation, just enough to knock the SCC IOP 20 * into compatible mode so nobody has to fiddle with the 21 * Serial Switch control panel anymore. 22 * 990603 (jmt) - Added code to grab the correct ISM IOP interrupt for OSS 23 * and non-OSS machines (at least I hope it's correct on a 24 * non-OSS machine -- someone with a Q900 or Q950 needs to 25 * check this.) 26 * 990605 (jmt) - Rearranged things a bit wrt IOP detection; iop_present is 27 * gone, IOP base addresses are now in an array and the 28 * globally-visible functions take an IOP number instead of an 29 * an actual base address. 30 * 990610 (jmt) - Finished the message passing framework and it seems to work. 31 * Sending _definately_ works; my adb-bus.c mods can send 32 * messages and receive the MSG_COMPLETED status back from the 33 * IOP. The trick now is figuring out the message formats. 34 * 990611 (jmt) - More cleanups. Fixed problem where unclaimed messages on a 35 * receive channel were never properly acknowledged. Bracketed 36 * the remaining debug printk's with #ifdef's and disabled 37 * debugging. I can now type on the console. 38 * 990612 (jmt) - Copyright notice added. Reworked the way replies are handled. 39 * It turns out that replies are placed back in the send buffer 40 * for that channel; messages on the receive channels are always 41 * unsolicited messages from the IOP (and our replies to them 42 * should go back in the receive channel.) Also added tracking 43 * of device names to the listener functions ala the interrupt 44 * handlers. 45 * 990729 (jmt) - Added passing of pt_regs structure to IOP handlers. This is 46 * used by the new unified ADB driver. 47 * 48 * TODO: 49 * 50 * o Something should be periodically checking iop_alive() to make sure the 51 * IOP hasn't died. 52 * o Some of the IOP manager routines need better error checking and 53 * return codes. Nothing major, just prettying up. 54 */ 55 56/* 57 * ----------------------- 58 * IOP Message Passing 101 59 * ----------------------- 60 * 61 * The host talks to the IOPs using a rather simple message-passing scheme via 62 * a shared memory area in the IOP RAM. Each IOP has seven "channels"; each 63 * channel is conneced to a specific software driver on the IOP. For example 64 * on the SCC IOP there is one channel for each serial port. Each channel has 65 * an incoming and and outgoing message queue with a depth of one. 66 * 67 * A message is 32 bytes plus a state byte for the channel (MSG_IDLE, MSG_NEW, 68 * MSG_RCVD, MSG_COMPLETE). To send a message you copy the message into the 69 * buffer, set the state to MSG_NEW and signal the IOP by setting the IRQ flag 70 * in the IOP control to 1. The IOP will move the state to MSG_RCVD when it 71 * receives the message and then to MSG_COMPLETE when the message processing 72 * has completed. It is the host's responsibility at that point to read the 73 * reply back out of the send channel buffer and reset the channel state back 74 * to MSG_IDLE. 75 * 76 * To receive message from the IOP the same procedure is used except the roles 77 * are reversed. That is, the IOP puts message in the channel with a state of 78 * MSG_NEW, and the host receives the message and move its state to MSG_RCVD 79 * and then to MSG_COMPLETE when processing is completed and the reply (if any) 80 * has been placed back in the receive channel. The IOP will then reset the 81 * channel state to MSG_IDLE. 82 * 83 * Two sets of host interrupts are provided, INT0 and INT1. Both appear on one 84 * interrupt level; they are distinguished by a pair of bits in the IOP status 85 * register. The IOP will raise INT0 when one or more messages in the send 86 * channels have gone to the MSG_COMPLETE state and it will raise INT1 when one 87 * or more messages on the receive channels have gone to the MSG_NEW state. 88 * 89 * Since each channel handles only one message we have to implement a small 90 * interrupt-driven queue on our end. Messages to e sent are placed on the 91 * queue for sending and contain a pointer to an optional callback function. 92 * The handler for a message is called when the message state goes to 93 * MSG_COMPLETE. 94 * 95 * For receiving message we maintain a list of handler functions to call when 96 * a message is received on that IOP/channel combination. The handlers are 97 * called much like an interrupt handler and are passed a copy of the message 98 * from the IOP. The message state will be in MSG_RCVD while the handler runs; 99 * it is the handler's responsibility to call iop_complete_message() when 100 * finished; this function moves the message state to MSG_COMPLETE and signals 101 * the IOP. This two-step process is provided to allow the handler to defer 102 * message processing to a bottom-half handler if the processing will take 103 * a signifigant amount of time (handlers are called at interrupt time so they 104 * should execute quickly.) 105 */ 106 107#include <linux/config.h> 108#include <linux/types.h> 109#include <linux/kernel.h> 110#include <linux/mm.h> 111#include <linux/delay.h> 112#include <linux/init.h> 113#include <linux/proc_fs.h> 114 115#include <asm/bootinfo.h> 116#include <asm/macintosh.h> 117#include <asm/macints.h> 118#include <asm/mac_iop.h> 119#include <asm/mac_oss.h> 120 121/*#define DEBUG_IOP*/ 122 123/* Set to nonezero if the IOPs are present. Set by iop_init() */ 124 125int iop_scc_present,iop_ism_present; 126 127#ifdef CONFIG_PROC_FS 128static int iop_get_proc_info(char *, char **, off_t, int); 129#endif /* CONFIG_PROC_FS */ 130 131/* structure for tracking channel listeners */ 132 133struct listener { 134 const char *devname; 135 void (*handler)(struct iop_msg *, struct pt_regs *); 136}; 137 138/* 139 * IOP structures for the two IOPs 140 * 141 * The SCC IOP controls both serial ports (A and B) as its two functions. 142 * The ISM IOP controls the SWIM (floppy drive) and ADB. 143 */ 144 145static volatile struct mac_iop *iop_base[NUM_IOPS]; 146 147/* 148 * IOP message queues 149 */ 150 151static struct iop_msg iop_msg_pool[NUM_IOP_MSGS]; 152static struct iop_msg *iop_send_queue[NUM_IOPS][NUM_IOP_CHAN]; 153static struct listener iop_listeners[NUM_IOPS][NUM_IOP_CHAN]; 154 155void iop_ism_irq(int, void *, struct pt_regs *); 156 157extern void oss_irq_enable(int); 158 159/* 160 * Private access functions 161 */ 162 163static __inline__ void iop_loadaddr(volatile struct mac_iop *iop, __u16 addr) 164{ 165 iop->ram_addr_lo = addr; 166 iop->ram_addr_hi = addr >> 8; 167} 168 169static __inline__ __u8 iop_readb(volatile struct mac_iop *iop, __u16 addr) 170{ 171 iop->ram_addr_lo = addr; 172 iop->ram_addr_hi = addr >> 8; 173 return iop->ram_data; 174} 175 176static __inline__ void iop_writeb(volatile struct mac_iop *iop, __u16 addr, __u8 data) 177{ 178 iop->ram_addr_lo = addr; 179 iop->ram_addr_hi = addr >> 8; 180 iop->ram_data = data; 181} 182 183static __inline__ void iop_stop(volatile struct mac_iop *iop) 184{ 185 iop->status_ctrl &= ~IOP_RUN; 186} 187 188static __inline__ void iop_start(volatile struct mac_iop *iop) 189{ 190 iop->status_ctrl = IOP_RUN | IOP_AUTOINC; 191} 192 193static __inline__ void iop_bypass(volatile struct mac_iop *iop) 194{ 195 iop->status_ctrl |= IOP_BYPASS; 196} 197 198static __inline__ void iop_interrupt(volatile struct mac_iop *iop) 199{ 200 iop->status_ctrl |= IOP_IRQ; 201} 202 203static int iop_alive(volatile struct mac_iop *iop) 204{ 205 int retval; 206 207 retval = (iop_readb(iop, IOP_ADDR_ALIVE) == 0xFF); 208 iop_writeb(iop, IOP_ADDR_ALIVE, 0); 209 return retval; 210} 211 212static struct iop_msg *iop_alloc_msg(void) 213{ 214 int i; 215 ulong cpu_flags; 216 217 save_flags(cpu_flags); 218 cli(); 219 220 for (i = 0 ; i < NUM_IOP_MSGS ; i++) { 221 if (iop_msg_pool[i].status == IOP_MSGSTATUS_UNUSED) { 222 iop_msg_pool[i].status = IOP_MSGSTATUS_WAITING; 223 restore_flags(cpu_flags); 224 return &iop_msg_pool[i]; 225 } 226 } 227 228 restore_flags(cpu_flags); 229 return NULL; 230} 231 232static void iop_free_msg(struct iop_msg *msg) 233{ 234 msg->status = IOP_MSGSTATUS_UNUSED; 235} 236 237/* 238 * This is called by the startup code before anything else. Its purpose 239 * is to find and initalize the IOPs early in the boot sequence, so that 240 * the serial IOP can be placed into bypass mode _before_ we try to 241 * initialize the serial console. 242 */ 243 244void __init iop_preinit(void) 245{ 246 if (macintosh_config->scc_type == MAC_SCC_IOP) { 247 if (macintosh_config->ident == MAC_MODEL_IIFX) { 248 iop_base[IOP_NUM_SCC] = (struct mac_iop *) SCC_IOP_BASE_IIFX; 249 } else { 250 iop_base[IOP_NUM_SCC] = (struct mac_iop *) SCC_IOP_BASE_QUADRA; 251 } 252 iop_base[IOP_NUM_SCC]->status_ctrl = 0x87; 253 iop_scc_present = 1; 254 } else { 255 iop_base[IOP_NUM_SCC] = NULL; 256 iop_scc_present = 0; 257 } 258 if (macintosh_config->adb_type == MAC_ADB_IOP) { 259 if (macintosh_config->ident == MAC_MODEL_IIFX) { 260 iop_base[IOP_NUM_ISM] = (struct mac_iop *) ISM_IOP_BASE_IIFX; 261 } else { 262 iop_base[IOP_NUM_ISM] = (struct mac_iop *) ISM_IOP_BASE_QUADRA; 263 } 264 iop_base[IOP_NUM_SCC]->status_ctrl = 0; 265 iop_ism_present = 1; 266 } else { 267 iop_base[IOP_NUM_ISM] = NULL; 268 iop_ism_present = 0; 269 } 270} 271 272/* 273 * Initialize the IOPs, if present. 274 */ 275 276void __init iop_init(void) 277{ 278 int i; 279 280 if (iop_scc_present) { 281 printk("IOP: detected SCC IOP at %p\n", iop_base[IOP_NUM_SCC]); 282 } 283 if (iop_ism_present) { 284 printk("IOP: detected ISM IOP at %p\n", iop_base[IOP_NUM_ISM]); 285 iop_start(iop_base[IOP_NUM_ISM]); 286 iop_alive(iop_base[IOP_NUM_ISM]); /* clears the alive flag */ 287 } 288 289 /* Make the whole pool available and empty the queues */ 290 291 for (i = 0 ; i < NUM_IOP_MSGS ; i++) { 292 iop_msg_pool[i].status = IOP_MSGSTATUS_UNUSED; 293 } 294 295 for (i = 0 ; i < NUM_IOP_CHAN ; i++) { 296 iop_send_queue[IOP_NUM_SCC][i] = 0; 297 iop_send_queue[IOP_NUM_ISM][i] = 0; 298 iop_listeners[IOP_NUM_SCC][i].devname = NULL; 299 iop_listeners[IOP_NUM_SCC][i].handler = NULL; 300 iop_listeners[IOP_NUM_ISM][i].devname = NULL; 301 iop_listeners[IOP_NUM_ISM][i].handler = NULL; 302 } 303 304} 305 306/* 307 * Register the interrupt handler for the IOPs. 308 * TODO: might be wrong for non-OSS machines. Anyone? 309 */ 310 311void __init iop_register_interrupts(void) 312{ 313 if (iop_ism_present) { 314 if (oss_present) { 315 sys_request_irq(OSS_IRQLEV_IOPISM, iop_ism_irq, 316 IRQ_FLG_LOCK, "ISM IOP", 317 (void *) IOP_NUM_ISM); 318 oss_irq_enable(IRQ_MAC_ADB); 319 } else { 320 request_irq(IRQ_VIA2_0, iop_ism_irq, 321 IRQ_FLG_LOCK|IRQ_FLG_FAST, "ISM IOP", 322 (void *) IOP_NUM_ISM); 323 } 324 if (!iop_alive(iop_base[IOP_NUM_ISM])) { 325 printk("IOP: oh my god, they killed the ISM IOP!\n"); 326 } else { 327 printk("IOP: the ISM IOP seems to be alive.\n"); 328 } 329 } 330} 331 332/* 333 * Register or unregister a listener for a specific IOP and channel 334 * 335 * If the handler pointer is NULL the current listener (if any) is 336 * unregistered. Otherwise the new listener is registered provided 337 * there is no existing listener registered. 338 */ 339 340int iop_listen(uint iop_num, uint chan, 341 void (*handler)(struct iop_msg *, struct pt_regs *), 342 const char *devname) 343{ 344 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return -EINVAL; 345 if (chan >= NUM_IOP_CHAN) return -EINVAL; 346 if (iop_listeners[iop_num][chan].handler && handler) return -EINVAL; 347 iop_listeners[iop_num][chan].devname = devname; 348 iop_listeners[iop_num][chan].handler = handler; 349 return 0; 350} 351 352/* 353 * Complete reception of a message, which just means copying the reply 354 * into the buffer, setting the channel state to MSG_COMPLETE and 355 * notifying the IOP. 356 */ 357 358void iop_complete_message(struct iop_msg *msg) 359{ 360 int iop_num = msg->iop_num; 361 int chan = msg->channel; 362 int i,offset; 363 364#ifdef DEBUG_IOP 365 printk("iop_complete(%p): iop %d chan %d\n", msg, msg->iop_num, msg->channel); 366#endif 367 368 offset = IOP_ADDR_RECV_MSG + (msg->channel * IOP_MSG_LEN); 369 370 for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { 371 iop_writeb(iop_base[iop_num], offset, msg->reply[i]); 372 } 373 374 iop_writeb(iop_base[iop_num], 375 IOP_ADDR_RECV_STATE + chan, IOP_MSG_COMPLETE); 376 iop_interrupt(iop_base[msg->iop_num]); 377 378 iop_free_msg(msg); 379} 380 381/* 382 * Actually put a message into a send channel buffer 383 */ 384 385static void iop_do_send(struct iop_msg *msg) 386{ 387 volatile struct mac_iop *iop = iop_base[msg->iop_num]; 388 int i,offset; 389 390 offset = IOP_ADDR_SEND_MSG + (msg->channel * IOP_MSG_LEN); 391 392 for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { 393 iop_writeb(iop, offset, msg->message[i]); 394 } 395 396 iop_writeb(iop, IOP_ADDR_SEND_STATE + msg->channel, IOP_MSG_NEW); 397 398 iop_interrupt(iop); 399} 400 401/* 402 * Handle sending a message on a channel that 403 * has gone into the IOP_MSG_COMPLETE state. 404 */ 405 406static void iop_handle_send(uint iop_num, uint chan, struct pt_regs *regs) 407{ 408 volatile struct mac_iop *iop = iop_base[iop_num]; 409 struct iop_msg *msg,*msg2; 410 int i,offset; 411 412#ifdef DEBUG_IOP 413 printk("iop_handle_send: iop %d channel %d\n", iop_num, chan); 414#endif 415 416 iop_writeb(iop, IOP_ADDR_SEND_STATE + chan, IOP_MSG_IDLE); 417 418 if (!(msg = iop_send_queue[iop_num][chan])) return; 419 420 msg->status = IOP_MSGSTATUS_COMPLETE; 421 offset = IOP_ADDR_SEND_MSG + (chan * IOP_MSG_LEN); 422 for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { 423 msg->reply[i] = iop_readb(iop, offset); 424 } 425 if (msg->handler) (*msg->handler)(msg, regs); 426 msg2 = msg; 427 msg = msg->next; 428 iop_free_msg(msg2); 429 430 iop_send_queue[iop_num][chan] = msg; 431 if (msg) iop_do_send(msg); 432} 433 434/* 435 * Handle reception of a message on a channel that has 436 * gone into the IOP_MSG_NEW state. 437 */ 438 439static void iop_handle_recv(uint iop_num, uint chan, struct pt_regs *regs) 440{ 441 volatile struct mac_iop *iop = iop_base[iop_num]; 442 int i,offset; 443 struct iop_msg *msg; 444 445#ifdef DEBUG_IOP 446 printk("iop_handle_recv: iop %d channel %d\n", iop_num, chan); 447#endif 448 449 msg = iop_alloc_msg(); 450 msg->iop_num = iop_num; 451 msg->channel = chan; 452 msg->status = IOP_MSGSTATUS_UNSOL; 453 msg->handler = iop_listeners[iop_num][chan].handler; 454 455 offset = IOP_ADDR_RECV_MSG + (chan * IOP_MSG_LEN); 456 457 for (i = 0 ; i < IOP_MSG_LEN ; i++, offset++) { 458 msg->message[i] = iop_readb(iop, offset); 459 } 460 461 iop_writeb(iop, IOP_ADDR_RECV_STATE + chan, IOP_MSG_RCVD); 462 463 /* If there is a listener, call it now. Otherwise complete */ 464 /* the message ourselves to avoid possible stalls. */ 465 466 if (msg->handler) { 467 (*msg->handler)(msg, regs); 468 } else { 469#ifdef DEBUG_IOP 470 printk("iop_handle_recv: unclaimed message on iop %d channel %d\n", iop_num, chan); 471 printk("iop_handle_recv:"); 472 for (i = 0 ; i < IOP_MSG_LEN ; i++) { 473 printk(" %02X", (uint) msg->message[i]); 474 } 475 printk("\n"); 476#endif 477 iop_complete_message(msg); 478 } 479} 480 481/* 482 * Send a message 483 * 484 * The message is placed at the end of the send queue. Afterwards if the 485 * channel is idle we force an immediate send of the next message in the 486 * queue. 487 */ 488 489int iop_send_message(uint iop_num, uint chan, void *privdata, 490 uint msg_len, __u8 *msg_data, 491 void (*handler)(struct iop_msg *, struct pt_regs *)) 492{ 493 struct iop_msg *msg, *q; 494 495 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return -EINVAL; 496 if (chan >= NUM_IOP_CHAN) return -EINVAL; 497 if (msg_len > IOP_MSG_LEN) return -EINVAL; 498 499 msg = iop_alloc_msg(); 500 if (!msg) return -ENOMEM; 501 502 msg->next = NULL; 503 msg->status = IOP_MSGSTATUS_WAITING; 504 msg->iop_num = iop_num; 505 msg->channel = chan; 506 msg->caller_priv = privdata; 507 memcpy(msg->message, msg_data, msg_len); 508 msg->handler = handler; 509 510 if (!(q = iop_send_queue[iop_num][chan])) { 511 iop_send_queue[iop_num][chan] = msg; 512 } else { 513 while (q->next) q = q->next; 514 q->next = msg; 515 } 516 517 if (iop_readb(iop_base[iop_num], 518 IOP_ADDR_SEND_STATE + chan) == IOP_MSG_IDLE) { 519 iop_do_send(msg); 520 } 521 522 return 0; 523} 524 525/* 526 * Upload code to the shared RAM of an IOP. 527 */ 528 529void iop_upload_code(uint iop_num, __u8 *code_start, 530 uint code_len, __u16 shared_ram_start) 531{ 532 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return; 533 534 iop_loadaddr(iop_base[iop_num], shared_ram_start); 535 536 while (code_len--) { 537 iop_base[iop_num]->ram_data = *code_start++; 538 } 539} 540 541/* 542 * Download code from the shared RAM of an IOP. 543 */ 544 545void iop_download_code(uint iop_num, __u8 *code_start, 546 uint code_len, __u16 shared_ram_start) 547{ 548 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return; 549 550 iop_loadaddr(iop_base[iop_num], shared_ram_start); 551 552 while (code_len--) { 553 *code_start++ = iop_base[iop_num]->ram_data; 554 } 555} 556 557/* 558 * Compare the code in the shared RAM of an IOP with a copy in system memory 559 * and return 0 on match or the first nonmatching system memory address on 560 * failure. 561 */ 562 563__u8 *iop_compare_code(uint iop_num, __u8 *code_start, 564 uint code_len, __u16 shared_ram_start) 565{ 566 if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return code_start; 567 568 iop_loadaddr(iop_base[iop_num], shared_ram_start); 569 570 while (code_len--) { 571 if (*code_start != iop_base[iop_num]->ram_data) { 572 return code_start; 573 } 574 code_start++; 575 } 576 return (__u8 *) 0; 577} 578 579/* 580 * Handle an ISM IOP interrupt 581 */ 582 583void iop_ism_irq(int irq, void *dev_id, struct pt_regs *regs) 584{ 585 uint iop_num = (uint) dev_id; 586 volatile struct mac_iop *iop = iop_base[iop_num]; 587 int i,state; 588 589#ifdef DEBUG_IOP 590 printk("iop_ism_irq: status = %02X\n", (uint) iop->status_ctrl); 591#endif 592 593 /* INT0 indicates a state change on an outgoing message channel */ 594 595 if (iop->status_ctrl & IOP_INT0) { 596 iop->status_ctrl = IOP_INT0 | IOP_RUN | IOP_AUTOINC; 597#ifdef DEBUG_IOP 598 printk("iop_ism_irq: new status = %02X, send states", 599 (uint) iop->status_ctrl); 600#endif 601 for (i = 0 ; i < NUM_IOP_CHAN ; i++) { 602 state = iop_readb(iop, IOP_ADDR_SEND_STATE + i); 603#ifdef DEBUG_IOP 604 printk(" %02X", state); 605#endif 606 if (state == IOP_MSG_COMPLETE) { 607 iop_handle_send(iop_num, i, regs); 608 } 609 } 610#ifdef DEBUG_IOP 611 printk("\n"); 612#endif 613 } 614 615 if (iop->status_ctrl & IOP_INT1) { /* INT1 for incoming msgs */ 616 iop->status_ctrl = IOP_INT1 | IOP_RUN | IOP_AUTOINC; 617#ifdef DEBUG_IOP 618 printk("iop_ism_irq: new status = %02X, recv states", 619 (uint) iop->status_ctrl); 620#endif 621 for (i = 0 ; i < NUM_IOP_CHAN ; i++) { 622 state = iop_readb(iop, IOP_ADDR_RECV_STATE + i); 623#ifdef DEBUG_IOP 624 printk(" %02X", state); 625#endif 626 if (state == IOP_MSG_NEW) { 627 iop_handle_recv(iop_num, i, regs); 628 } 629 } 630#ifdef DEBUG_IOP 631 printk("\n"); 632#endif 633 } 634 635} 636 637#ifdef CONFIG_PROC_FS 638 639char *iop_chan_state(int state) 640{ 641 switch(state) { 642 case IOP_MSG_IDLE : return "idle "; 643 case IOP_MSG_NEW : return "new "; 644 case IOP_MSG_RCVD : return "received "; 645 case IOP_MSG_COMPLETE : return "completed "; 646 default : return "unknown "; 647 } 648} 649 650int iop_dump_one_iop(char *buf, int iop_num, char *iop_name) 651{ 652 int i,len = 0; 653 volatile struct mac_iop *iop = iop_base[iop_num]; 654 655 len += sprintf(buf+len, "%s IOP channel states:\n\n", iop_name); 656 len += sprintf(buf+len, "## send_state recv_state device\n"); 657 len += sprintf(buf+len, "------------------------------------------------\n"); 658 for (i = 0 ; i < NUM_IOP_CHAN ; i++) { 659 len += sprintf(buf+len, "%2d %10s %10s %s\n", i, 660 iop_chan_state(iop_readb(iop, IOP_ADDR_SEND_STATE+i)), 661 iop_chan_state(iop_readb(iop, IOP_ADDR_RECV_STATE+i)), 662 iop_listeners[iop_num][i].handler? 663 iop_listeners[iop_num][i].devname : ""); 664 665 } 666 len += sprintf(buf+len, "\n"); 667 return len; 668} 669 670static int iop_get_proc_info(char *buf, char **start, off_t pos, int count) 671{ 672 int len, cnt; 673 674 cnt = 0; 675 len = sprintf(buf, "IOPs detected:\n\n"); 676 677 if (iop_scc_present) { 678 len += sprintf(buf+len, "SCC IOP (%p): status %02X\n", 679 iop_base[IOP_NUM_SCC], 680 (uint) iop_base[IOP_NUM_SCC]->status_ctrl); 681 } 682 if (iop_ism_present) { 683 len += sprintf(buf+len, "ISM IOP (%p): status %02X\n\n", 684 iop_base[IOP_NUM_ISM], 685 (uint) iop_base[IOP_NUM_ISM]->status_ctrl); 686 } 687 688 if (iop_scc_present) { 689 len += iop_dump_one_iop(buf+len, IOP_NUM_SCC, "SCC"); 690 691 } 692 693 if (iop_ism_present) { 694 len += iop_dump_one_iop(buf+len, IOP_NUM_ISM, "ISM"); 695 696 } 697 698 if (len >= pos) { 699 if (!*start) { 700 *start = buf + pos; 701 cnt = len - pos; 702 } else { 703 cnt += len; 704 } 705 } 706 return (count > cnt) ? cnt : count; 707} 708 709#endif /* CONFIG_PROC_FS */ 710