1/* $Id: pci_bus_cvlink.c,v 1.1.1.1 2008/10/15 03:26:03 james26_jang Exp $ 2 * 3 * This file is subject to the terms and conditions of the GNU General Public 4 * License. See the file "COPYING" in the main directory of this archive 5 * for more details. 6 * 7 * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved. 8 */ 9 10#include <linux/config.h> 11#include <linux/init.h> 12#include <linux/types.h> 13#include <linux/pci.h> 14#include <linux/pci_ids.h> 15#include <linux/sched.h> 16#include <linux/ioport.h> 17#include <asm/sn/types.h> 18#include <asm/sn/hack.h> 19#include <asm/sn/sgi.h> 20#include <asm/sn/io.h> 21#include <asm/sn/driver.h> 22#include <asm/sn/iograph.h> 23#include <asm/param.h> 24#include <asm/sn/pio.h> 25#include <asm/sn/xtalk/xwidget.h> 26#include <asm/sn/sn_private.h> 27#include <asm/sn/addrs.h> 28#include <asm/sn/invent.h> 29#include <asm/sn/hcl.h> 30#include <asm/sn/hcl_util.h> 31#include <asm/sn/intr.h> 32#include <asm/sn/xtalk/xtalkaddrs.h> 33#include <asm/sn/klconfig.h> 34#include <asm/sn/nodepda.h> 35#include <asm/sn/pci/pciio.h> 36#include <asm/sn/pci/pcibr.h> 37#include <asm/sn/pci/pcibr_private.h> 38#include <asm/sn/pci/pci_bus_cvlink.h> 39#include <asm/sn/simulator.h> 40#include <asm/sn/sn_cpuid.h> 41 42extern int bridge_rev_b_data_check_disable; 43 44devfs_handle_t busnum_to_pcibr_vhdl[MAX_PCI_XWIDGET]; 45nasid_t busnum_to_nid[MAX_PCI_XWIDGET]; 46void * busnum_to_atedmamaps[MAX_PCI_XWIDGET]; 47unsigned char num_bridges; 48static int done_probing = 0; 49 50static int pci_bus_map_create(devfs_handle_t xtalk); 51devfs_handle_t devfn_to_vertex(unsigned char busnum, unsigned int devfn); 52 53#define SN_IOPORTS_UNIT 256 54#define MAX_IOPORTS 0xffff 55#define MAX_IOPORTS_CHUNKS (MAX_IOPORTS / SN_IOPORTS_UNIT) 56struct ioports_to_tlbs_s ioports_to_tlbs[MAX_IOPORTS_CHUNKS]; 57unsigned long sn_allocate_ioports(unsigned long pci_address); 58 59extern void sn_init_irq_desc(void); 60 61 62 63/* 64 * pci_bus_cvlink_init() - To be called once during initialization before 65 * SGI IO Infrastructure init is called. 66 */ 67void 68pci_bus_cvlink_init(void) 69{ 70 memset(busnum_to_pcibr_vhdl, 0x0, sizeof(devfs_handle_t) * MAX_PCI_XWIDGET); 71 memset(busnum_to_nid, 0x0, sizeof(nasid_t) * MAX_PCI_XWIDGET); 72 73 memset(busnum_to_atedmamaps, 0x0, sizeof(void *) * MAX_PCI_XWIDGET); 74 75 memset(ioports_to_tlbs, 0x0, sizeof(ioports_to_tlbs)); 76 77 num_bridges = 0; 78} 79 80/* 81 * pci_bus_to_vertex() - Given a logical Linux Bus Number returns the associated 82 * pci bus vertex from the SGI IO Infrastructure. 83 */ 84devfs_handle_t 85pci_bus_to_vertex(unsigned char busnum) 86{ 87 88 devfs_handle_t pci_bus = NULL; 89 90 91 /* 92 * First get the xwidget vertex. 93 */ 94 pci_bus = busnum_to_pcibr_vhdl[busnum]; 95 return(pci_bus); 96} 97 98/* 99 * devfn_to_vertex() - returns the vertex of the device given the bus, slot, 100 * and function numbers. 101 */ 102devfs_handle_t 103devfn_to_vertex(unsigned char busnum, unsigned int devfn) 104{ 105 106 int slot = 0; 107 int func = 0; 108 char name[16]; 109 devfs_handle_t pci_bus = NULL; 110 devfs_handle_t device_vertex = (devfs_handle_t)NULL; 111 112 /* 113 * Go get the pci bus vertex. 114 */ 115 pci_bus = pci_bus_to_vertex(busnum); 116 if (!pci_bus) { 117 /* 118 * During probing, the Linux pci code invents non-existent 119 * bus numbers and pci_dev structures and tries to access 120 * them to determine existence. Don't crib during probing. 121 */ 122 if (done_probing) 123 printk("devfn_to_vertex: Invalid bus number %d given.\n", busnum); 124 return(NULL); 125 } 126 127 128 /* 129 * Go get the slot&function vertex. 130 * Should call pciio_slot_func_to_name() when ready. 131 */ 132 slot = PCI_SLOT(devfn); 133 func = PCI_FUNC(devfn); 134 135 /* 136 * For a NON Multi-function card the name of the device looks like: 137 * ../pci/1, ../pci/2 .. 138 */ 139 if (func == 0) { 140 sprintf(name, "%d", slot); 141 if (hwgraph_traverse(pci_bus, name, &device_vertex) == 142 GRAPH_SUCCESS) { 143 if (device_vertex) { 144 return(device_vertex); 145 } 146 } 147 } 148 149 /* 150 * This maybe a multifunction card. It's names look like: 151 * ../pci/1a, ../pci/1b, etc. 152 */ 153 sprintf(name, "%d%c", slot, 'a'+func); 154 if (hwgraph_traverse(pci_bus, name, &device_vertex) != GRAPH_SUCCESS) { 155 if (!device_vertex) { 156 return(NULL); 157 } 158 } 159 160 return(device_vertex); 161} 162 163/* 164 * For the given device, initialize the addresses for both the Device(x) Flush 165 * Write Buffer register and the Xbow Flush Register for the port the PCI bus 166 * is connected. 167 */ 168static void 169set_flush_addresses(struct pci_dev *device_dev, 170 struct sn_device_sysdata *device_sysdata) 171{ 172 pciio_info_t pciio_info = pciio_info_get(device_sysdata->vhdl); 173 pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info); 174 pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info); 175 bridge_t *bridge = pcibr_soft->bs_base; 176 177 device_sysdata->dma_buf_sync = (volatile unsigned int *) 178 &(bridge->b_wr_req_buf[pciio_slot].reg); 179 device_sysdata->xbow_buf_sync = (volatile unsigned int *) 180 XBOW_PRIO_LINKREGS_PTR(NODE_SWIN_BASE(get_nasid(), 0), 181 pcibr_soft->bs_xid); 182#ifdef DEBUG 183 184 printk("set_flush_addresses: dma_buf_sync %p xbow_buf_sync %p\n", 185 device_sysdata->dma_buf_sync, device_sysdata->xbow_buf_sync); 186 187 while((volatile unsigned int )*device_sysdata->dma_buf_sync); 188 while((volatile unsigned int )*device_sysdata->xbow_buf_sync); 189#endif 190 191} 192 193/* 194 * Most drivers currently do not properly tell the arch specific pci dma 195 * interfaces whether they can handle A64. Here is where we privately 196 * keep track of this. 197 */ 198static void __init 199set_sn_pci64(struct pci_dev *dev) 200{ 201 unsigned short vendor = dev->vendor; 202 unsigned short device = dev->device; 203 204 if (vendor == PCI_VENDOR_ID_QLOGIC) { 205 if ((device == PCI_DEVICE_ID_QLOGIC_ISP2100) || 206 (device == PCI_DEVICE_ID_QLOGIC_ISP2200)) { 207 SET_PCIA64(dev); 208 return; 209 } 210 } 211 212 if (vendor == PCI_VENDOR_ID_SGI) { 213 if (device == PCI_DEVICE_ID_SGI_IOC3) { 214 SET_PCIA64(dev); 215 return; 216 } 217 } 218 219} 220 221/* 222 * sn_allocate_ioports() - This routine provides the allocation and 223 * mappings between Linux style IOPORTs management. 224 * 225 * For simplicity sake, SN1 will allocate IOPORTs in chunks of 226 * 256bytes .. irrespective of what the card desires. This may 227 * have to change when we understand how to deal with legacy ioports 228 * which are hardcoded in some drivers e.g. SVGA. 229 * 230 * Ofcourse, the SN1 IO Infrastructure has no concept of IOPORT numbers. 231 * It will remain so. The IO Infrastructure will continue to map 232 * IO Resource just like IRIX. When this is done, we map IOPORT 233 * chunks to these resources. The Linux drivers will see and use real 234 * IOPORT numbers. The various IOPORT access macros e.g. inb/outb etc. 235 * does the munging of these IOPORT numbers to make a Uncache Virtual 236 * Address. This address via the tlb entries generates the PCI Address 237 * allocated by the SN1 IO Infrastructure Layer. 238 */ 239static unsigned long sn_ioport_num = 0x1000; /* Reserve room for Legacy stuff */ 240unsigned long 241sn_allocate_ioports(unsigned long pci_address) 242{ 243 244 unsigned long ioport_index; 245 246 /* 247 * Just some idiot checking .. 248 */ 249 if ( sn_ioport_num > 0xffff ) { 250 printk("sn_allocate_ioports: No more IO PORTS available\n"); 251 return(-1); 252 } 253 254 /* 255 * See Section 4.1.1.5 of Intel IA-64 Acrchitecture Software Developer's 256 * Manual for details. 257 */ 258 ioport_index = sn_ioport_num / SN_IOPORTS_UNIT; 259 260 ioports_to_tlbs[ioport_index].p = 1; /* Present Bit */ 261 ioports_to_tlbs[ioport_index].rv_1 = 0; /* 1 Bit */ 262 ioports_to_tlbs[ioport_index].ma = 4; /* Memory Attributes 3 bits*/ 263 ioports_to_tlbs[ioport_index].a = 1; /* Set Data Access Bit Fault 1 Bit*/ 264 ioports_to_tlbs[ioport_index].d = 1; /* Dirty Bit */ 265 ioports_to_tlbs[ioport_index].pl = 0;/* Privilege Level - All levels can R/W*/ 266 ioports_to_tlbs[ioport_index].ar = 3; /* Access Rights - R/W only*/ 267 ioports_to_tlbs[ioport_index].ppn = pci_address >> 12; /* 4K page size */ 268 ioports_to_tlbs[ioport_index].ed = 0; /* Exception Deferral Bit */ 269 ioports_to_tlbs[ioport_index].ig = 0; /* Ignored */ 270 271 /* printk("sn_allocate_ioports: ioport_index 0x%x ioports_to_tlbs 0x%p\n", ioport_index, ioports_to_tlbs[ioport_index]); */ 272 273 sn_ioport_num += SN_IOPORTS_UNIT; 274 275 return(sn_ioport_num - SN_IOPORTS_UNIT); 276} 277 278/* 279 * sn_pci_fixup() - This routine is called when platform_pci_fixup() is 280 * invoked at the end of pcibios_init() to link the Linux pci 281 * infrastructure to SGI IO Infrasturcture - ia64/kernel/pci.c 282 * 283 * Other platform specific fixup can also be done here. 284 */ 285void 286sn_pci_fixup(int arg) 287{ 288 struct list_head *ln; 289 struct pci_bus *pci_bus = NULL; 290 struct pci_dev *device_dev = NULL; 291 struct sn_widget_sysdata *widget_sysdata; 292 struct sn_device_sysdata *device_sysdata; 293#ifdef SN_IOPORTS 294 unsigned long ioport; 295#endif 296 pciio_intr_t intr_handle; 297 int cpuid, bit; 298 devfs_handle_t device_vertex; 299 pciio_intr_line_t lines; 300 extern void sn_pci_find_bios(void); 301#ifdef CONFIG_IA64_SGI_SN2 302 extern int numnodes; 303 int cnode; 304#endif /* CONFIG_IA64_SGI_SN2 */ 305 306 307 if (arg == 0) { 308 sn_init_irq_desc(); 309 sn_pci_find_bios(); 310#ifdef CONFIG_IA64_SGI_SN2 311 for (cnode = 0; cnode < numnodes; cnode++) { 312 extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int); 313 intr_init_vecblk(NODEPDA(cnode), cnode, 0); 314 } 315#endif /* CONFIG_IA64_SGI_SN2 */ 316 return; 317 } 318 319 done_probing = 1; 320 321 /* 322 * Initialize the pci bus vertex in the pci_bus struct. 323 */ 324 for( ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) { 325 pci_bus = pci_bus_b(ln); 326 widget_sysdata = kmalloc(sizeof(struct sn_widget_sysdata), 327 GFP_KERNEL); 328 widget_sysdata->vhdl = pci_bus_to_vertex(pci_bus->number); 329 pci_bus->sysdata = (void *)widget_sysdata; 330 } 331 332 /* 333 * set the root start and end so that drivers calling check_region() 334 * won't see a conflict 335 */ 336#ifdef SN_IOPORTS 337 ioport_resource.start = sn_ioport_num; 338 ioport_resource.end = 0xffff; 339#else 340#if defined(CONFIG_IA64_SGI_SN1) 341 if ( IS_RUNNING_ON_SIMULATOR() ) { 342 /* 343 * IDE legacy IO PORTs are supported in Medusa. 344 * Just open up IO PORTs from 0 .. ioport_resource.end. 345 */ 346 ioport_resource.start = 0; 347 } else { 348 /* 349 * We do not support Legacy IO PORT numbers. 350 */ 351 ioport_resource.start |= IO_SWIZ_BASE | __IA64_UNCACHED_OFFSET; 352 } 353 ioport_resource.end |= (HSPEC_SWIZ_BASE-1) | __IA64_UNCACHED_OFFSET; 354#else 355 // Need something here for sn2.... ZXZXZX 356#endif 357#endif 358 359 /* 360 * Set the root start and end for Mem Resource. 361 */ 362 iomem_resource.start = 0; 363 iomem_resource.end = 0xffffffffffffffff; 364 365 /* 366 * Initialize the device vertex in the pci_dev struct. 367 */ 368 pci_for_each_dev(device_dev) { 369 unsigned int irq; 370 int idx; 371 u16 cmd; 372 devfs_handle_t vhdl; 373 unsigned long size; 374 extern int bit_pos_to_irq(int); 375 376 if (device_dev->vendor == PCI_VENDOR_ID_SGI && 377 device_dev->device == PCI_DEVICE_ID_SGI_IOC3) { 378 extern void pci_fixup_ioc3(struct pci_dev *d); 379 pci_fixup_ioc3(device_dev); 380 } 381 382 /* Set the device vertex */ 383 384 device_sysdata = kmalloc(sizeof(struct sn_device_sysdata), 385 GFP_KERNEL); 386 device_sysdata->vhdl = devfn_to_vertex(device_dev->bus->number, device_dev->devfn); 387 device_sysdata->isa64 = 0; 388 /* 389 * Set the xbridge Device(X) Write Buffer Flush and Xbow Flush 390 * register addresses. 391 */ 392 (void) set_flush_addresses(device_dev, device_sysdata); 393 394 device_dev->sysdata = (void *) device_sysdata; 395 set_sn_pci64(device_dev); 396 pci_read_config_word(device_dev, PCI_COMMAND, &cmd); 397 398 /* 399 * Set the resources address correctly. The assumption here 400 * is that the addresses in the resource structure has been 401 * read from the card and it was set in the card by our 402 * Infrastructure .. 403 */ 404 vhdl = device_sysdata->vhdl; 405 for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) { 406 size = 0; 407 size = device_dev->resource[idx].end - 408 device_dev->resource[idx].start; 409 if (size) { 410 device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(vhdl, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, PCIIO_BYTE_STREAM); 411 device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET; 412 } 413 else 414 continue; 415 416 device_dev->resource[idx].end = 417 device_dev->resource[idx].start + size; 418 419#ifdef CONFIG_IA64_SGI_SN1 420 /* 421 * Adjust the addresses to go to the SWIZZLE .. 422 */ 423 device_dev->resource[idx].start = 424 device_dev->resource[idx].start & 0xfffff7ffffffffff; 425 device_dev->resource[idx].end = 426 device_dev->resource[idx].end & 0xfffff7ffffffffff; 427#endif 428 429 if (device_dev->resource[idx].flags & IORESOURCE_IO) { 430 cmd |= PCI_COMMAND_IO; 431#ifdef SN_IOPORTS 432 ioport = sn_allocate_ioports(device_dev->resource[idx].start); 433 if (ioport < 0) { 434 printk("sn_pci_fixup: PCI Device 0x%x on PCI Bus %d not mapped to IO PORTs .. IO PORTs exhausted\n", device_dev->devfn, device_dev->bus->number); 435 continue; 436 } 437 pciio_config_set(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + (idx * 4), 4, (res + (ioport & 0xfff))); 438 439printk("sn_pci_fixup: ioport number %d mapped to pci address 0x%lx\n", ioport, (res + (ioport & 0xfff))); 440 441 device_dev->resource[idx].start = ioport; 442 device_dev->resource[idx].end = ioport + SN_IOPORTS_UNIT; 443#endif 444 } 445 if (device_dev->resource[idx].flags & IORESOURCE_MEM) 446 cmd |= PCI_COMMAND_MEMORY; 447 } 448 /* 449 * Now handle the ROM resource .. 450 */ 451 size = device_dev->resource[PCI_ROM_RESOURCE].end - 452 device_dev->resource[PCI_ROM_RESOURCE].start; 453 454 if (size) { 455 device_dev->resource[PCI_ROM_RESOURCE].start = 456 (unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0, 457 size, 0, PCIIO_BYTE_STREAM); 458 device_dev->resource[PCI_ROM_RESOURCE].start |= __IA64_UNCACHED_OFFSET; 459 device_dev->resource[PCI_ROM_RESOURCE].end = 460 device_dev->resource[PCI_ROM_RESOURCE].start + size; 461 462#ifdef CONFIG_IA64_SGI_SN1 463 /* 464 * go through synergy swizzled space 465 */ 466 device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL; 467 device_dev->resource[PCI_ROM_RESOURCE].end &= 0xfffff7ffffffffffUL; 468#endif 469 470 } 471 472 /* 473 * Update the Command Word on the Card. 474 */ 475 cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */ 476 /* bit gets dropped .. no harm */ 477 pci_write_config_word(device_dev, PCI_COMMAND, cmd); 478 479 pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines); 480 if (device_dev->vendor == PCI_VENDOR_ID_SGI && 481 device_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) { 482 lines = 1; 483 } 484 485 device_sysdata = (struct sn_device_sysdata *)device_dev->sysdata; 486 device_vertex = device_sysdata->vhdl; 487 488 intr_handle = pciio_intr_alloc(device_vertex, NULL, lines, device_vertex); 489 490 bit = intr_handle->pi_irq; 491 cpuid = intr_handle->pi_cpu; 492#ifdef CONFIG_IA64_SGI_SN1 493 irq = bit_pos_to_irq(bit); 494#else /* SN2 */ 495 irq = bit; 496#endif 497 irq = irq + (cpuid << 8); 498 pciio_intr_connect(intr_handle); 499 device_dev->irq = irq; 500#ifdef ajmtestintr 501 { 502 int slot = PCI_SLOT(device_dev->devfn); 503 static int timer_set = 0; 504 pcibr_intr_t pcibr_intr = (pcibr_intr_t)intr_handle; 505 pcibr_soft_t pcibr_soft = pcibr_intr->bi_soft; 506 extern void intr_test_handle_intr(int, void*, struct pt_regs *); 507 508 if (!timer_set) { 509 intr_test_set_timer(); 510 timer_set = 1; 511 } 512 intr_test_register_irq(irq, pcibr_soft, slot); 513 request_irq(irq, intr_test_handle_intr,0,NULL, NULL); 514 } 515#endif 516 517 } 518 519 520} 521 522/* 523 * pci_bus_map_create() - Called by pci_bus_to_hcl_cvlink() to finish the job. 524 * 525 * Linux PCI Bus numbers are assigned from lowest module_id numbers 526 * (rack/slot etc.) starting from HUB_WIDGET_ID_MAX down to 527 * HUB_WIDGET_ID_MIN: 528 * widgetnum 15 gets lower Bus Number than widgetnum 14 etc. 529 * 530 * Given 2 modules 001c01 and 001c02 we get the following mappings: 531 * 001c01, widgetnum 15 = Bus number 0 532 * 001c01, widgetnum 14 = Bus number 1 533 * 001c02, widgetnum 15 = Bus number 3 534 * 001c02, widgetnum 14 = Bus number 4 535 * etc. 536 * 537 * The rational for starting Bus Number 0 with Widget number 15 is because 538 * the system boot disks are always connected via Widget 15 Slot 0 of the 539 * I-brick. Linux creates /dev/sd* devices(naming) strating from Bus Number 0 540 * Therefore, /dev/sda1 will be the first disk, on Widget 15 of the lowest 541 * module id(Master Cnode) of the system. 542 * 543 */ 544static int 545pci_bus_map_create(devfs_handle_t xtalk) 546{ 547 548 devfs_handle_t master_node_vertex = NULL; 549 devfs_handle_t xwidget = NULL; 550 devfs_handle_t pci_bus = NULL; 551 hubinfo_t hubinfo = NULL; 552 xwidgetnum_t widgetnum; 553 char pathname[128]; 554 graph_error_t rv; 555 556 /* 557 * Loop throught this vertex and get the Xwidgets .. 558 */ 559 for (widgetnum = HUB_WIDGET_ID_MAX; widgetnum >= HUB_WIDGET_ID_MIN; widgetnum--) { 560 561 sprintf(pathname, "%d", widgetnum); 562 xwidget = NULL; 563 564 /* 565 * Example - /hw/module/001c16/Pbrick/xtalk/8 is the xwidget 566 * /hw/module/001c16/Pbrick/xtalk/8/pci/1 is device 567 */ 568 rv = hwgraph_traverse(xtalk, pathname, &xwidget); 569 if ( (rv != GRAPH_SUCCESS) ) { 570 if (!xwidget) 571 continue; 572 } 573 574 sprintf(pathname, "%d/"EDGE_LBL_PCI, widgetnum); 575 pci_bus = NULL; 576 if (hwgraph_traverse(xtalk, pathname, &pci_bus) != GRAPH_SUCCESS) 577 if (!pci_bus) 578 continue; 579 580 /* 581 * Assign the correct bus number and also the nasid of this 582 * pci Xwidget. 583 * 584 * Should not be any race here ... 585 */ 586 num_bridges++; 587 busnum_to_pcibr_vhdl[num_bridges - 1] = pci_bus; 588 589 /* 590 * Get the master node and from there get the NASID. 591 */ 592 master_node_vertex = device_master_get(xwidget); 593 if (!master_node_vertex) { 594 printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", (void *)xwidget); 595 } 596 597 hubinfo_get(master_node_vertex, &hubinfo); 598 if (!hubinfo) { 599 printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", (void *)master_node_vertex); 600 return(1); 601 } else { 602 busnum_to_nid[num_bridges - 1] = hubinfo->h_nasid; 603 } 604 605 /* 606 * Pre assign DMA maps needed for 32 Bits Page Map DMA. 607 */ 608 busnum_to_atedmamaps[num_bridges - 1] = (void *) kmalloc( 609 sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS, GFP_KERNEL); 610 if (!busnum_to_atedmamaps[num_bridges - 1]) 611 printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, (void *)xwidget); 612 613 memset(busnum_to_atedmamaps[num_bridges - 1], 0x0, 614 sizeof(struct sn_dma_maps_s) * MAX_ATE_MAPS); 615 616 } 617 618 return(0); 619} 620 621/* 622 * pci_bus_to_hcl_cvlink() - This routine is called after SGI IO Infrastructure 623 * initialization has completed to set up the mappings between Xbridge 624 * and logical pci bus numbers. We also set up the NASID for each of these 625 * xbridges. 626 * 627 * Must be called before pci_init() is invoked. 628 */ 629int 630pci_bus_to_hcl_cvlink(void) 631{ 632 633 devfs_handle_t devfs_hdl = NULL; 634 devfs_handle_t xtalk = NULL; 635 int rv = 0; 636 char name[256]; 637 int master_iobrick; 638 int i; 639 640 /* 641 * Iterate throught each xtalk links in the system .. 642 * /hw/module/001c01/node/xtalk/ 8|9|10|11|12|13|14|15 643 * 644 * /hw/module/001c01/node/xtalk/15 -> /hw/module/001c01/Ibrick/xtalk/15 645 * 646 * What if it is not pci? 647 */ 648 devfs_hdl = hwgraph_path_to_vertex("/dev/hw/module"); 649 650 /* 651 * To provide consistent(not persistent) device naming, we need to start 652 * bus number allocation from the C-Brick with the lowest module id e.g. 001c01 653 * with an attached I-Brick. Find the master_iobrick. 654 */ 655 master_iobrick = -1; 656 for (i = 0; i < nummodules; i++) { 657 moduleid_t iobrick_id; 658 iobrick_id = iobrick_module_get(&modules[i]->elsc); 659 if (iobrick_id > 0) { /* Valid module id */ 660 if (MODULE_GET_BTYPE(iobrick_id) == MODULE_IBRICK) { 661 master_iobrick = i; 662 break; 663 } 664 } 665 } 666 667 /* 668 * The master_iobrick gets bus 0 and 1. 669 */ 670 if (master_iobrick >= 0) { 671 memset(name, 0, 256); 672 format_module_id(name, modules[master_iobrick]->id, MODULE_FORMAT_BRIEF); 673 strcat(name, "/node/xtalk"); 674 xtalk = NULL; 675 rv = hwgraph_edge_get(devfs_hdl, name, &xtalk); 676 pci_bus_map_create(xtalk); 677 } 678 679 /* 680 * Now go do the rest of the modules, starting from the C-Brick with the lowest 681 * module id, remembering to skip the master_iobrick, which was done above. 682 */ 683 for (i = 0; i < nummodules; i++) { 684 if (i == master_iobrick) { 685 continue; /* Did the master_iobrick already. */ 686 } 687 688 memset(name, 0, 256); 689 format_module_id(name, modules[i]->id, MODULE_FORMAT_BRIEF); 690 strcat(name, "/node/xtalk"); 691 xtalk = NULL; 692 rv = hwgraph_edge_get(devfs_hdl, name, &xtalk); 693 pci_bus_map_create(xtalk); 694 } 695 696 return(0); 697} 698