1/* 2 * linux/arch/arm/kernel/head-armv.S 3 * 4 * Copyright (C) 1994-1999 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * 32-bit kernel startup code for all architectures 11 */ 12#include <linux/config.h> 13#include <linux/linkage.h> 14 15#include <asm/assembler.h> 16#include <asm/mach-types.h> 17#include <asm/mach/arch.h> 18 19#define K(a,b,c) ((a) << 24 | (b) << 12 | (c)) 20 21/* 22 * We place the page tables 16K below TEXTADDR. Therefore, we must make sure 23 * that TEXTADDR is correctly set. Currently, we expect the least significant 24 * "short" to be 0x8000, but we could probably relax this restriction to 25 * TEXTADDR > PAGE_OFFSET + 0x4000 26 * 27 * Note that swapper_pg_dir is the virtual address of the page tables, and 28 * pgtbl gives us a position-independent reference to these tables. We can 29 * do this because stext == TEXTADDR 30 * 31 * swapper_pg_dir, pgtbl and krnladr are all closely related. 32 */ 33#if (TEXTADDR & 0xffff) != 0x8000 34#error TEXTADDR must start at 0xXXXX8000 35#endif 36 37 .globl SYMBOL_NAME(swapper_pg_dir) 38 .equ SYMBOL_NAME(swapper_pg_dir), TEXTADDR - 0x4000 39 40 .macro pgtbl, reg, rambase 41 adr \reg, stext 42 sub \reg, \reg, #0x4000 43 .endm 44 45/* 46 * Since the page table is closely related to the kernel start address, we 47 * can convert the page table base address to the base address of the section 48 * containing both. 49 */ 50 .macro krnladr, rd, pgtable, rambase 51 bic \rd, \pgtable, #0x000ff000 52 .endm 53 54/* 55 * Kernel startup entry point. 56 * 57 * The rules are: 58 * r0 - should be 0 59 * r1 - unique architecture number 60 * MMU - off 61 * I-cache - on or off 62 * D-cache - off 63 * 64 * See linux/arch/arm/tools/mach-types for the complete list of numbers 65 * for r1. 66 */ 67 .section ".text.init",#alloc,#execinstr 68 .type stext, #function 69ENTRY(stext) 70 mov r12, r0 71/* 72 * NOTE! Any code which is placed here should be done for one of 73 * the following reasons: 74 * 75 * 1. Compatability with old production boot firmware (ie, users 76 * actually have and are booting the kernel with the old firmware) 77 * and therefore will be eventually removed. 78 * 2. Cover the case when there is no boot firmware. This is not 79 * ideal, but in this case, it should ONLY set r0 and r1 to the 80 * appropriate value. 81 */ 82#if defined(CONFIG_ARCH_NETWINDER) 83/* 84 * Compatability cruft for old NetWinder NeTTroms. This 85 * code is currently scheduled for destruction in 2.5.xx 86 */ 87 .rept 8 88 mov r0, r0 89 .endr 90 91 adr r2, 1f 92 ldmdb r2, {r7, r8} 93 and r3, r2, #0xc000 94 teq r3, #0x8000 95 beq __entry 96 bic r3, r2, #0xc000 97 orr r3, r3, #0x8000 98 mov r0, r3 99 mov r4, #64 100 sub r5, r8, r7 101 b 1f 102 103 .word _stext 104 .word __bss_start 105 1061: 107 .rept 4 108 ldmia r2!, {r6, r7, r8, r9} 109 stmia r3!, {r6, r7, r8, r9} 110 .endr 111 subs r4, r4, #64 112 bcs 1b 113 movs r4, r5 114 mov r5, #0 115 movne pc, r0 116 117 mov r1, #MACH_TYPE_NETWINDER @ (will go in 2.5) 118 mov r12, #2 << 24 @ scheduled for removal in 2.5.xx 119 orr r12, r12, #5 << 12 120__entry: 121#endif 122#if defined(CONFIG_ARCH_L7200) 123 mov r1, #MACH_TYPE_L7200 124#endif 125 126 mov r0, #F_BIT | I_BIT | MODE_SVC @ make sure svc mode 127 msr cpsr_c, r0 @ and all irqs disabled 128 bl __lookup_processor_type 129 teq r10, #0 @ invalid processor? 130 moveq r0, #'p' @ yes, error 'p' 131 beq __error 132 bl __lookup_architecture_type 133 teq r7, #0 @ invalid architecture? 134 moveq r0, #'a' @ yes, error 'a' 135 beq __error 136 bl __create_page_tables 137 adr lr, __ret @ return address 138 add pc, r10, #12 @ initialise processor 139 @ (return control reg) 140 141 .type __switch_data, %object 142__switch_data: .long __mmap_switched 143 .long SYMBOL_NAME(compat) 144 .long SYMBOL_NAME(__bss_start) 145 .long SYMBOL_NAME(_end) 146 .long SYMBOL_NAME(processor_id) 147 .long SYMBOL_NAME(__machine_arch_type) 148 .long SYMBOL_NAME(cr_alignment) 149 .long SYMBOL_NAME(init_task_union)+8192 150 151 .type __ret, %function 152__ret: ldr lr, __switch_data 153 mcr p15, 0, r0, c1, c0 154 mov r0, r0 155 mov r0, r0 156 mov r0, r0 157 mov pc, lr 158 159 /* 160 * This code follows on after the page 161 * table switch and jump above. 162 * 163 * r0 = processor control register 164 * r1 = machine ID 165 * r9 = processor ID 166 */ 167 .align 5 168__mmap_switched: 169 adr r3, __switch_data + 4 170 ldmia r3, {r2, r4, r5, r6, r7, r8, sp}@ r2 = compat 171 @ sp = stack pointer 172 str r12, [r2] 173 174 mov fp, #0 @ Clear BSS (and zero fp) 1751: cmp r4, r5 176 strcc fp, [r4],#4 177 bcc 1b 178 179 str r9, [r6] @ Save processor ID 180 str r1, [r7] @ Save machine type 181#ifdef CONFIG_ALIGNMENT_TRAP 182 orr r0, r0, #2 @ ...........A. 183#endif 184 bic r2, r0, #2 @ Clear 'A' bit 185 stmia r8, {r0, r2} @ Save control register values 186 b SYMBOL_NAME(start_kernel) 187 188 189 190/* 191 * Setup the initial page tables. We only setup the barest 192 * amount which are required to get the kernel running, which 193 * generally means mapping in the kernel code. 194 * 195 * We only map in 4MB of RAM, which should be sufficient in 196 * all cases. 197 * 198 * r5 = physical address of start of RAM 199 * r6 = physical IO address 200 * r7 = byte offset into page tables for IO 201 * r8 = page table flags 202 */ 203__create_page_tables: 204 pgtbl r4, r5 @ page table address 205 206 /* 207 * Clear the 16K level 1 swapper page table 208 */ 209 mov r0, r4 210 mov r3, #0 211 add r2, r0, #0x4000 2121: str r3, [r0], #4 213 str r3, [r0], #4 214 str r3, [r0], #4 215 str r3, [r0], #4 216 teq r0, r2 217 bne 1b 218 219 /* 220 * Create identity mapping for first MB of kernel to 221 * cater for the MMU enable. This identity mapping 222 * will be removed by paging_init() 223 */ 224 krnladr r2, r4, r5 @ start of kernel 225 add r3, r8, r2 @ flags + kernel base 226 str r3, [r4, r2, lsr #18] @ identity mapping 227 228 /* 229 * Now setup the pagetables for our kernel direct 230 * mapped region. We round TEXTADDR down to the 231 * nearest megabyte boundary. 232 */ 233 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel 234 bic r2, r3, #0x00f00000 235 str r2, [r0] @ PAGE_OFFSET + 0MB 236 add r0, r0, #(TEXTADDR & 0x00f00000) >> 18 237 str r3, [r0], #4 @ KERNEL + 0MB 238 add r3, r3, #1 << 20 239 str r3, [r0], #4 @ KERNEL + 1MB 240 add r3, r3, #1 << 20 241 str r3, [r0], #4 @ KERNEL + 2MB 242 add r3, r3, #1 << 20 243 str r3, [r0], #4 @ KERNEL + 3MB 244 245 /* 246 * Ensure that the first section of RAM is present. 247 * we assume that: 248 * 1. the RAM is aligned to a 32MB boundary 249 * 2. the kernel is executing in the same 32MB chunk 250 * as the start of RAM. 251 */ 252 bic r0, r0, #0x01f00000 >> 18 @ round down 253 and r2, r5, #0xfe000000 @ round down 254 add r3, r8, r2 @ flags + rambase 255 str r3, [r0] 256 257 bic r8, r8, #0x0c @ turn off cacheable 258 @ and bufferable bits 259#ifdef CONFIG_DEBUG_LL 260 /* 261 * Map in IO space for serial debugging. 262 * This allows debug messages to be output 263 * via a serial console before paging_init. 264 */ 265 add r0, r4, r7 266 rsb r3, r7, #0x4000 @ PTRS_PER_PGD*sizeof(long) 267 cmp r3, #0x0800 268 addge r2, r0, #0x0800 269 addlt r2, r0, r3 270 orr r3, r6, r8 2711: str r3, [r0], #4 272 add r3, r3, #1 << 20 273 teq r0, r2 274 bne 1b 275#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 276 /* 277 * If we're using the NetWinder, we need to map in 278 * the 16550-type serial port for the debug messages 279 */ 280 teq r1, #MACH_TYPE_NETWINDER 281 teqne r1, #MACH_TYPE_CATS 282 bne 1f 283 add r0, r4, #0x3fc0 284 mov r3, #0x7c000000 285 orr r3, r3, r8 286 str r3, [r0], #4 287 add r3, r3, #1 << 20 288 str r3, [r0], #4 2891: 290#endif 291#endif 292#ifdef CONFIG_ARCH_RPC 293 /* 294 * Map in screen at 0x02000000 & SCREEN2_BASE 295 * Similar reasons here - for debug. This is 296 * only for Acorn RiscPC architectures. 297 */ 298 add r0, r4, #0x80 @ 02000000 299 mov r3, #0x02000000 300 orr r3, r3, r8 301 str r3, [r0] 302 add r0, r4, #0x3600 @ d8000000 303 str r3, [r0] 304#endif 305 mov pc, lr 306 307 308 309/* 310 * Exception handling. Something went wrong and we can't 311 * proceed. We ought to tell the user, but since we 312 * don't have any guarantee that we're even running on 313 * the right architecture, we do virtually nothing. 314 * r0 = ascii error character: 315 * a = invalid architecture 316 * p = invalid processor 317 * i = invalid calling convention 318 * 319 * Generally, only serious errors cause this. 320 */ 321__error: 322#ifdef CONFIG_DEBUG_LL 323 mov r8, r0 @ preserve r0 324 adr r0, err_str 325 bl printascii 326 mov r0, r8 327 bl printch 328#endif 329#ifdef CONFIG_ARCH_RPC 330/* 331 * Turn the screen red on a error - RiscPC only. 332 */ 333 mov r0, #0x02000000 334 mov r3, #0x11 335 orr r3, r3, r3, lsl #8 336 orr r3, r3, r3, lsl #16 337 str r3, [r0], #4 338 str r3, [r0], #4 339 str r3, [r0], #4 340 str r3, [r0], #4 341#endif 3421: mov r0, r0 343 b 1b 344 345#ifdef CONFIG_DEBUG_LL 346err_str: .asciz "\nError: " 347 .align 348#endif 349 350/* 351 * Read processor ID register (CP#15, CR0), and look up in the linker-built 352 * supported processor list. Note that we can't use the absolute addresses 353 * for the __proc_info lists since we aren't running with the MMU on 354 * (and therefore, we are not in the correct address space). We have to 355 * calculate the offset. 356 * 357 * Returns: 358 * r5, r6, r7 corrupted 359 * r8 = page table flags 360 * r9 = processor ID 361 * r10 = pointer to processor structure 362 */ 363__lookup_processor_type: 364 adr r5, 2f 365 ldmia r5, {r7, r9, r10} 366 sub r5, r5, r10 @ convert addresses 367 add r7, r7, r5 @ to our address space 368 add r10, r9, r5 369 mrc p15, 0, r9, c0, c0 @ get processor id 3701: ldmia r10, {r5, r6, r8} @ value, mask, mmuflags 371 and r6, r6, r9 @ mask wanted bits 372 teq r5, r6 373 moveq pc, lr 374 add r10, r10, #36 @ sizeof(proc_info_list) 375 cmp r10, r7 376 blt 1b 377 mov r10, #0 @ unknown processor 378 mov pc, lr 379 380/* 381 * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for 382 * more information about the __proc_info and __arch_info structures. 383 */ 3842: .long __proc_info_end 385 .long __proc_info_begin 386 .long 2b 387 .long __arch_info_begin 388 .long __arch_info_end 389 390/* 391 * Lookup machine architecture in the linker-build list of architectures. 392 * Note that we can't use the absolute addresses for the __arch_info 393 * lists since we aren't running with the MMU on (and therefore, we are 394 * not in the correct address space). We have to calculate the offset. 395 * 396 * r1 = machine architecture number 397 * Returns: 398 * r2, r3, r4 corrupted 399 * r5 = physical start address of RAM 400 * r6 = physical address of IO 401 * r7 = byte offset into page tables for IO 402 */ 403__lookup_architecture_type: 404 adr r4, 2b 405 ldmia r4, {r2, r3, r5, r6, r7} @ throw away r2, r3 406 sub r5, r4, r5 @ convert addresses 407 add r4, r6, r5 @ to our address space 408 add r7, r7, r5 4091: ldr r5, [r4] @ get machine type 410 teq r5, r1 411 beq 2f 412 add r4, r4, #SIZEOF_MACHINE_DESC 413 cmp r4, r7 414 blt 1b 415 mov r7, #0 @ unknown architecture 416 mov pc, lr 4172: ldmib r4, {r5, r6, r7} @ found, get results 418 mov pc, lr 419