1/* 2 * linux/arch/alpha/kernel/sys_titan.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996, 1999 Jay A Estabrook 6 * Copyright (C) 1998, 1999 Richard Henderson 7 * Copyright (C) 1999, 2000 Jeff Wiedemeier 8 * 9 * Code supporting TITAN systems (EV6+TITAN), currently: 10 * Privateer 11 */ 12 13#include <linux/config.h> 14#include <linux/kernel.h> 15#include <linux/types.h> 16#include <linux/mm.h> 17#include <linux/sched.h> 18#include <linux/pci.h> 19#include <linux/init.h> 20 21#include <asm/ptrace.h> 22#include <asm/system.h> 23#include <asm/dma.h> 24#include <asm/irq.h> 25#include <asm/bitops.h> 26#include <asm/mmu_context.h> 27#include <asm/io.h> 28#include <asm/pgtable.h> 29#include <asm/core_titan.h> 30#include <asm/hwrpb.h> 31 32#include "proto.h" 33#include "irq_impl.h" 34#include "pci_impl.h" 35#include "machvec_impl.h" 36 37/* Note mask bit is true for ENABLED irqs. */ 38static unsigned long cached_irq_mask; 39/* Titan boards handle at most four CPUs. */ 40static unsigned long cpu_irq_affinity[4] = { ~0UL, ~0UL, ~0UL, ~0UL }; 41 42spinlock_t titan_irq_lock = SPIN_LOCK_UNLOCKED; 43 44static void 45titan_update_irq_hw(unsigned long mask) 46{ 47 register titan_cchip *cchip = TITAN_cchip; 48 unsigned long isa_enable = 1UL << 55; 49 register int bcpu = boot_cpuid; 50 51#ifdef CONFIG_SMP 52 register unsigned long cpm = cpu_present_mask; 53 volatile unsigned long *dim0, *dim1, *dim2, *dim3; 54 unsigned long mask0, mask1, mask2, mask3, dummy; 55 56 mask &= ~isa_enable; 57 mask0 = mask & cpu_irq_affinity[0]; 58 mask1 = mask & cpu_irq_affinity[1]; 59 mask2 = mask & cpu_irq_affinity[2]; 60 mask3 = mask & cpu_irq_affinity[3]; 61 62 if (bcpu == 0) mask0 |= isa_enable; 63 else if (bcpu == 1) mask1 |= isa_enable; 64 else if (bcpu == 2) mask2 |= isa_enable; 65 else mask3 |= isa_enable; 66 67 dim0 = &cchip->dim0.csr; 68 dim1 = &cchip->dim1.csr; 69 dim2 = &cchip->dim2.csr; 70 dim3 = &cchip->dim3.csr; 71 if ((cpm & 1) == 0) dim0 = &dummy; 72 if ((cpm & 2) == 0) dim1 = &dummy; 73 if ((cpm & 4) == 0) dim2 = &dummy; 74 if ((cpm & 8) == 0) dim3 = &dummy; 75 76 *dim0 = mask0; 77 *dim1 = mask1; 78 *dim2 = mask2; 79 *dim3 = mask3; 80 mb(); 81 *dim0; 82 *dim1; 83 *dim2; 84 *dim3; 85#else 86 volatile unsigned long *dimB; 87 if (bcpu == 0) dimB = &cchip->dim0.csr; 88 else if (bcpu == 1) dimB = &cchip->dim1.csr; 89 else if (bcpu == 2) dimB = &cchip->dim2.csr; 90 else if (bcpu == 3) dimB = &cchip->dim3.csr; 91 92 *dimB = mask | isa_enable; 93 mb(); 94 *dimB; 95#endif 96} 97 98static inline void 99privateer_enable_irq(unsigned int irq) 100{ 101 spin_lock(&titan_irq_lock); 102 cached_irq_mask |= 1UL << (irq - 16); 103 titan_update_irq_hw(cached_irq_mask); 104 spin_unlock(&titan_irq_lock); 105} 106 107static inline void 108privateer_disable_irq(unsigned int irq) 109{ 110 spin_lock(&titan_irq_lock); 111 cached_irq_mask &= ~(1UL << (irq - 16)); 112 titan_update_irq_hw(cached_irq_mask); 113 spin_unlock(&titan_irq_lock); 114} 115 116static unsigned int 117privateer_startup_irq(unsigned int irq) 118{ 119 privateer_enable_irq(irq); 120 return 0; /* never anything pending */ 121} 122 123static void 124privateer_end_irq(unsigned int irq) 125{ 126 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 127 privateer_enable_irq(irq); 128} 129 130static void 131cpu_set_irq_affinity(unsigned int irq, unsigned long affinity) 132{ 133 int cpu; 134 135 for (cpu = 0; cpu < 4; cpu++) { 136 if (affinity & (1UL << cpu)) 137 cpu_irq_affinity[cpu] |= 1UL << irq; 138 else 139 cpu_irq_affinity[cpu] &= ~(1UL << irq); 140 } 141 142} 143 144static void 145privateer_set_affinity(unsigned int irq, unsigned long affinity) 146{ 147 spin_lock(&titan_irq_lock); 148 cpu_set_irq_affinity(irq - 16, affinity); 149 titan_update_irq_hw(cached_irq_mask); 150 spin_unlock(&titan_irq_lock); 151} 152 153static struct hw_interrupt_type privateer_irq_type = { 154 typename: "PRIVATEER", 155 startup: privateer_startup_irq, 156 shutdown: privateer_disable_irq, 157 enable: privateer_enable_irq, 158 disable: privateer_disable_irq, 159 ack: privateer_disable_irq, 160 end: privateer_end_irq, 161 set_affinity: privateer_set_affinity, 162}; 163 164static void 165privateer_device_interrupt(unsigned long vector, struct pt_regs * regs) 166{ 167 printk("privateer_device_interrupt: NOT IMPLEMENTED YET!! \n"); 168} 169 170static void 171privateer_srm_device_interrupt(unsigned long vector, struct pt_regs * regs) 172{ 173 int irq; 174 175 irq = (vector - 0x800) >> 4; 176 handle_irq(irq, regs); 177} 178 179 180static void __init 181init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax) 182{ 183 long i; 184 for(i = imin; i <= imax; ++i) { 185 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 186 irq_desc[i].handler = ops; 187 } 188} 189 190static void __init 191privateer_init_irq(void) 192{ 193 extern asmlinkage void entInt(void); 194 int cpu; 195 196 outb(0, DMA1_RESET_REG); 197 outb(0, DMA2_RESET_REG); 198 outb(DMA_MODE_CASCADE, DMA2_MODE_REG); 199 outb(0, DMA2_MASK_REG); 200 201 if (alpha_using_srm) 202 alpha_mv.device_interrupt = privateer_srm_device_interrupt; 203 204 titan_update_irq_hw(0UL); 205 206 init_i8259a_irqs(); 207 init_titan_irqs(&privateer_irq_type, 16, 63 + 16); 208} 209 210/* 211 * Privateer PCI Fixup configuration. 212 * 213 * PCHIP 0 BUS 0 (Hose 0) 214 * 215 * IDSEL Dev What 216 * ----- --- ---- 217 * 18 7 Embedded Southbridge 218 * 19 8 Slot 0 219 * 20 9 Slot 1 220 * 21 10 Slot 2 221 * 22 11 Slot 3 222 * 23 12 Embedded HotPlug controller 223 * 27 16 Embedded Southbridge IDE 224 * 29 18 Embedded Southbridge PMU 225 * 31 20 Embedded Southbridge USB 226 * 227 * PCHIP 1 BUS 0 (Hose 1) 228 * 229 * IDSEL Dev What 230 * ----- --- ---- 231 * 12 1 Slot 0 232 * 13 2 Slot 1 233 * 17 6 Embedded hotPlug controller 234 * 235 * PCHIP 0 BUS 1 (Hose 2) 236 * 237 * IDSEL What 238 * ----- ---- 239 * NONE AGP 240 * 241 * PCHIP 1 BUS 1 (Hose 3) 242 * 243 * IDSEL Dev What 244 * ----- --- ---- 245 * 12 1 Slot 0 246 * 13 2 Slot 1 247 * 17 6 Embedded hotPlug controller 248 * 249 * Summary @ TITAN_CSR_DIM0: 250 * Bit Meaning 251 * 0-7 Unused 252 * 8 PCHIP 0 BUS 1 YUKON (if present) 253 * 9 PCHIP 1 BUS 1 YUKON 254 * 10 PCHIP 1 BUS 0 YUKON 255 * 11 PCHIP 0 BUS 0 YUKON 256 * 12 PCHIP 0 BUS 0 SLOT 2 INT A 257 * 13 PCHIP 0 BUS 0 SLOT 2 INT B 258 * 14 PCHIP 0 BUS 0 SLOT 2 INT C 259 * 15 PCHIP 0 BUS 0 SLOT 2 INT D 260 * 16 PCHIP 0 BUS 0 SLOT 3 INT A 261 * 17 PCHIP 0 BUS 0 SLOT 3 INT B 262 * 18 PCHIP 0 BUS 0 SLOT 3 INT C 263 * 19 PCHIP 0 BUS 0 SLOT 3 INT D 264 * 20 PCHIP 0 BUS 0 SLOT 0 INT A 265 * 21 PCHIP 0 BUS 0 SLOT 0 INT B 266 * 22 PCHIP 0 BUS 0 SLOT 0 INT C 267 * 23 PCHIP 0 BUS 0 SLOT 0 INT D 268 * 24 PCHIP 0 BUS 0 SLOT 1 INT A 269 * 25 PCHIP 0 BUS 0 SLOT 1 INT B 270 * 26 PCHIP 0 BUS 0 SLOT 1 INT C 271 * 27 PCHIP 0 BUS 0 SLOT 1 INT D 272 * 28 PCHIP 1 BUS 0 SLOT 0 INT A 273 * 29 PCHIP 1 BUS 0 SLOT 0 INT B 274 * 30 PCHIP 1 BUS 0 SLOT 0 INT C 275 * 31 PCHIP 1 BUS 0 SLOT 0 INT D 276 * 32 PCHIP 1 BUS 0 SLOT 1 INT A 277 * 33 PCHIP 1 BUS 0 SLOT 1 INT B 278 * 34 PCHIP 1 BUS 0 SLOT 1 INT C 279 * 35 PCHIP 1 BUS 0 SLOT 1 INT D 280 * 36 PCHIP 1 BUS 1 SLOT 0 INT A 281 * 37 PCHIP 1 BUS 1 SLOT 0 INT B 282 * 38 PCHIP 1 BUS 1 SLOT 0 INT C 283 * 39 PCHIP 1 BUS 1 SLOT 0 INT D 284 * 40 PCHIP 1 BUS 1 SLOT 1 INT A 285 * 41 PCHIP 1 BUS 1 SLOT 1 INT B 286 * 42 PCHIP 1 BUS 1 SLOT 1 INT C 287 * 43 PCHIP 1 BUS 1 SLOT 1 INT D 288 * 44 AGP INT A 289 * 45 AGP INT B 290 * 46-47 Unused 291 * 49 Reserved for Sleep mode 292 * 50 Temperature Warning (optional) 293 * 51 Power Warning (optional) 294 * 52 Reserved 295 * 53 South Bridge NMI 296 * 54 South Bridge SMI INT 297 * 55 South Bridge ISA Interrupt 298 * 56-58 Unused 299 * 59 PCHIP1_C_ERROR 300 * 60 PCHIP0_C_ERROR 301 * 61 PCHIP1_H_ERROR 302 * 62 PCHIP0_H_ERROR 303 * 63 Reserved 304 * 305 */ 306static int __init 307privateer_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 308{ 309 u8 irq; 310 311 pcibios_read_config_byte(dev->bus->number, 312 dev->devfn, 313 PCI_INTERRUPT_LINE, 314 &irq); 315 316 /* is it routed through ISA? */ 317 if ((irq & 0xF0) == 0xE0) 318 return (int)irq; 319 320 return (int)irq + 16; /* HACK -- this better only be called once */ 321} 322 323#ifdef CONFIG_VGA_HOSE 324static struct pci_controller * __init 325privateer_vga_hose_select(struct pci_controller *h1, struct pci_controller *h2) 326{ 327 struct pci_controller *hose = h1; 328 int agp1, agp2; 329 330 /* which hose(s) are agp? */ 331 agp1 = (0 != (TITAN_agp & (1 << h1->index))); 332 agp2 = (0 != (TITAN_agp & (1 << h2->index))); 333 334 hose = h1; /* default to h1 */ 335 if (agp1 ^ agp2) { 336 if (agp2) hose = h2; /* take agp if only one */ 337 } else if (h2->index < h1->index) 338 hose = h2; /* first hose if 2xpci or 2xagp */ 339 340 return hose; 341} 342#endif 343 344static void __init 345privateer_init_pci(void) 346{ 347 common_init_pci(); 348 SMC669_Init(0); 349#ifdef CONFIG_VGA_HOSE 350 locate_and_init_vga(privateer_vga_hose_select); 351#endif 352} 353 354void 355privateer_machine_check(unsigned long vector, unsigned long la_ptr, 356 struct pt_regs * regs) 357{ 358 /* only handle system events here */ 359 if (vector != SCB_Q_SYSEVENT) 360 return titan_machine_check(vector, la_ptr, regs); 361 362 /* it's a system event, handle it here */ 363 printk("PRIVATEER 680 Machine Check on CPU %d\n", smp_processor_id()); 364} 365 366 367/* 368 * The System Vectors 369 */ 370 371struct alpha_machine_vector privateer_mv __initmv = { 372 vector_name: "PRIVATEER", 373 DO_EV6_MMU, 374 DO_DEFAULT_RTC, 375 DO_TITAN_IO, 376 DO_TITAN_BUS, 377 machine_check: privateer_machine_check, 378 max_dma_address: ALPHA_MAX_DMA_ADDRESS, 379 min_io_address: DEFAULT_IO_BASE, 380 min_mem_address: DEFAULT_MEM_BASE, 381 pci_dac_offset: TITAN_DAC_OFFSET, 382 383 nr_irqs: 80, /* 64 + 16 */ 384 device_interrupt: privateer_device_interrupt, 385 386 init_arch: titan_init_arch, 387 init_irq: privateer_init_irq, 388 init_rtc: common_init_rtc, 389 init_pci: privateer_init_pci, 390 kill_arch: titan_kill_arch, 391 pci_map_irq: privateer_map_irq, 392 pci_swizzle: common_swizzle, 393}; 394ALIAS_MV(privateer) 395