1/* 2 * linux/arch/alpha/kernel/core_cia.c 3 * 4 * Written by David A Rusling (david.rusling@reo.mts.dec.com). 5 * December 1995. 6 * 7 * Copyright (C) 1995 David A Rusling 8 * Copyright (C) 1997, 1998 Jay Estabrook 9 * Copyright (C) 1998, 1999, 2000 Richard Henderson 10 * 11 * Code common to all CIA core logic chips. 12 */ 13 14#include <linux/kernel.h> 15#include <linux/types.h> 16#include <linux/pci.h> 17#include <linux/sched.h> 18#include <linux/init.h> 19 20#include <asm/system.h> 21#include <asm/ptrace.h> 22#include <asm/hwrpb.h> 23 24#define __EXTERN_INLINE inline 25#include <asm/io.h> 26#include <asm/core_cia.h> 27#undef __EXTERN_INLINE 28 29#include <linux/bootmem.h> 30 31#include "proto.h" 32#include "pci_impl.h" 33 34 35/* 36 * NOTE: Herein lie back-to-back mb instructions. They are magic. 37 * One plausible explanation is that the i/o controller does not properly 38 * handle the system transaction. Another involves timing. Ho hum. 39 */ 40 41#define DEBUG_CONFIG 0 42#if DEBUG_CONFIG 43# define DBGC(args) printk args 44#else 45# define DBGC(args) 46#endif 47 48#define vip volatile int * 49 50/* 51 * Given a bus, device, and function number, compute resulting 52 * configuration space address. It is therefore not safe to have 53 * concurrent invocations to configuration space access routines, but 54 * there really shouldn't be any need for this. 55 * 56 * Type 0: 57 * 58 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 59 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 60 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 61 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| 62 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 63 * 64 * 31:11 Device select bit. 65 * 10:8 Function number 66 * 7:2 Register number 67 * 68 * Type 1: 69 * 70 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 71 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 72 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 73 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| 74 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 75 * 76 * 31:24 reserved 77 * 23:16 bus number (8 bits = 128 possible buses) 78 * 15:11 Device number (5 bits) 79 * 10:8 function number 80 * 7:2 register number 81 * 82 * Notes: 83 * The function number selects which function of a multi-function device 84 * (e.g., SCSI and Ethernet). 85 * 86 * The register selects a DWORD (32 bit) register offset. Hence it 87 * doesn't get shifted by 2 bits as we want to "drop" the bottom two 88 * bits. 89 */ 90 91static int 92mk_conf_addr(struct pci_dev *dev, int where, unsigned long *pci_addr, 93 unsigned char *type1) 94{ 95 u8 bus = dev->bus->number; 96 u8 device_fn = dev->devfn; 97 98 *type1 = (bus != 0); 99 *pci_addr = (bus << 16) | (device_fn << 8) | where; 100 101 DBGC(("mk_conf_addr(bus=%d ,device_fn=0x%x, where=0x%x," 102 " returning address 0x%p\n" 103 bus, device_fn, where, *pci_addr)); 104 105 return 0; 106} 107 108static unsigned int 109conf_read(unsigned long addr, unsigned char type1) 110{ 111 unsigned long flags; 112 int stat0, value; 113 int cia_cfg = 0; 114 115 DBGC(("conf_read(addr=0x%lx, type1=%d) ", addr, type1)); 116 __save_and_cli(flags); 117 118 /* Reset status register to avoid losing errors. */ 119 stat0 = *(vip)CIA_IOC_CIA_ERR; 120 *(vip)CIA_IOC_CIA_ERR = stat0; 121 mb(); 122 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ 123 124 /* If Type1 access, must set CIA CFG. */ 125 if (type1) { 126 cia_cfg = *(vip)CIA_IOC_CFG; 127 *(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1; 128 mb(); 129 *(vip)CIA_IOC_CFG; 130 } 131 132 mb(); 133 draina(); 134 mcheck_expected(0) = 1; 135 mcheck_taken(0) = 0; 136 mb(); 137 138 /* Access configuration space. */ 139 value = *(vip)addr; 140 mb(); 141 mb(); /* magic */ 142 if (mcheck_taken(0)) { 143 mcheck_taken(0) = 0; 144 value = 0xffffffff; 145 mb(); 146 } 147 mcheck_expected(0) = 0; 148 mb(); 149 150 /* If Type1 access, must reset IOC CFG so normal IO space ops work. */ 151 if (type1) { 152 *(vip)CIA_IOC_CFG = cia_cfg; 153 mb(); 154 *(vip)CIA_IOC_CFG; 155 } 156 157 __restore_flags(flags); 158 DBGC(("done\n")); 159 160 return value; 161} 162 163static void 164conf_write(unsigned long addr, unsigned int value, unsigned char type1) 165{ 166 unsigned long flags; 167 int stat0, cia_cfg = 0; 168 169 DBGC(("conf_write(addr=0x%lx, type1=%d) ", addr, type1)); 170 __save_and_cli(flags); 171 172 /* Reset status register to avoid losing errors. */ 173 stat0 = *(vip)CIA_IOC_CIA_ERR; 174 *(vip)CIA_IOC_CIA_ERR = stat0; 175 mb(); 176 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write */ 177 178 /* If Type1 access, must set CIA CFG. */ 179 if (type1) { 180 cia_cfg = *(vip)CIA_IOC_CFG; 181 *(vip)CIA_IOC_CFG = (cia_cfg & ~3) | 1; 182 mb(); 183 *(vip)CIA_IOC_CFG; 184 } 185 186 mb(); 187 draina(); 188 mcheck_expected(0) = 1; 189 mcheck_taken(0) = 0; 190 mb(); 191 192 /* Access configuration space. */ 193 *(vip)addr = value; 194 mb(); 195 *(vip)addr; /* read back to force the write */ 196 197 mcheck_expected(0) = 0; 198 mb(); 199 200 /* If Type1 access, must reset IOC CFG so normal IO space ops work. */ 201 if (type1) { 202 *(vip)CIA_IOC_CFG = cia_cfg; 203 mb(); 204 *(vip)CIA_IOC_CFG; 205 } 206 207 __restore_flags(flags); 208 DBGC(("done\n")); 209} 210 211static int 212cia_read_config_byte(struct pci_dev *dev, int where, u8 *value) 213{ 214 unsigned long addr, pci_addr; 215 unsigned char type1; 216 217 if (mk_conf_addr(dev, where, &pci_addr, &type1)) 218 return PCIBIOS_DEVICE_NOT_FOUND; 219 220 addr = (pci_addr << 5) + 0x00 + CIA_CONF; 221 *value = conf_read(addr, type1) >> ((where & 3) * 8); 222 return PCIBIOS_SUCCESSFUL; 223} 224 225static int 226cia_read_config_word(struct pci_dev *dev, int where, u16 *value) 227{ 228 unsigned long addr, pci_addr; 229 unsigned char type1; 230 231 if (mk_conf_addr(dev, where, &pci_addr, &type1)) 232 return PCIBIOS_DEVICE_NOT_FOUND; 233 234 addr = (pci_addr << 5) + 0x08 + CIA_CONF; 235 *value = conf_read(addr, type1) >> ((where & 3) * 8); 236 return PCIBIOS_SUCCESSFUL; 237} 238 239static int 240cia_read_config_dword(struct pci_dev *dev, int where, u32 *value) 241{ 242 unsigned long addr, pci_addr; 243 unsigned char type1; 244 245 if (mk_conf_addr(dev, where, &pci_addr, &type1)) 246 return PCIBIOS_DEVICE_NOT_FOUND; 247 248 addr = (pci_addr << 5) + 0x18 + CIA_CONF; 249 *value = conf_read(addr, type1); 250 return PCIBIOS_SUCCESSFUL; 251} 252 253static int 254cia_write_config(struct pci_dev *dev, int where, u32 value, long mask) 255{ 256 unsigned long addr, pci_addr; 257 unsigned char type1; 258 259 if (mk_conf_addr(dev, where, &pci_addr, &type1)) 260 return PCIBIOS_DEVICE_NOT_FOUND; 261 262 addr = (pci_addr << 5) + mask + CIA_CONF; 263 conf_write(addr, value << ((where & 3) * 8), type1); 264 return PCIBIOS_SUCCESSFUL; 265} 266 267static int 268cia_write_config_byte(struct pci_dev *dev, int where, u8 value) 269{ 270 return cia_write_config(dev, where, value, 0x00); 271} 272 273static int 274cia_write_config_word(struct pci_dev *dev, int where, u16 value) 275{ 276 return cia_write_config(dev, where, value, 0x08); 277} 278 279static int 280cia_write_config_dword(struct pci_dev *dev, int where, u32 value) 281{ 282 return cia_write_config(dev, where, value, 0x18); 283} 284 285struct pci_ops cia_pci_ops = 286{ 287 read_byte: cia_read_config_byte, 288 read_word: cia_read_config_word, 289 read_dword: cia_read_config_dword, 290 write_byte: cia_write_config_byte, 291 write_word: cia_write_config_word, 292 write_dword: cia_write_config_dword 293}; 294 295/* 296 * CIA Pass 1 and PYXIS Pass 1 and 2 have a broken scatter-gather tlb. 297 * It cannot be invalidated. Rather than hard code the pass numbers, 298 * actually try the tbia to see if it works. 299 */ 300 301void 302cia_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end) 303{ 304 wmb(); 305 *(vip)CIA_IOC_PCI_TBIA = 3; /* Flush all locked and unlocked. */ 306 mb(); 307 *(vip)CIA_IOC_PCI_TBIA; 308} 309 310/* 311 * On PYXIS, even if the tbia works, we cannot use it. It effectively locks 312 * the chip (as well as direct write to the tag registers) if there is a 313 * SG DMA operation in progress. This is true at least for PYXIS rev. 1, 314 * so always use the method below. 315 */ 316/* 317 * This is the method NT and NetBSD use. 318 * 319 * Allocate mappings, and put the chip into DMA loopback mode to read a 320 * garbage page. This works by causing TLB misses, causing old entries to 321 * be purged to make room for the new entries coming in for the garbage page. 322 */ 323 324#define CIA_BROKEN_TBIA_BASE 0x30000000 325#define CIA_BROKEN_TBIA_SIZE 1024 326 327/* Always called with interrupts disabled */ 328void 329cia_pci_tbi_try2(struct pci_controller *hose, 330 dma_addr_t start, dma_addr_t end) 331{ 332 unsigned long bus_addr; 333 int ctrl; 334 335 /* Put the chip into PCI loopback mode. */ 336 mb(); 337 ctrl = *(vip)CIA_IOC_CIA_CTRL; 338 *(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN; 339 mb(); 340 *(vip)CIA_IOC_CIA_CTRL; 341 mb(); 342 343 /* Read from PCI dense memory space at TBI_ADDR, skipping 32k on 344 each read. This forces SG TLB misses. NetBSD claims that the 345 TLB entries are not quite LRU, meaning that we need to read more 346 times than there are actual tags. The 2117x docs claim strict 347 round-robin. Oh well, we've come this far... */ 348 /* Even better - as seen on the PYXIS rev 1 the TLB tags 0-3 can 349 be filled by the TLB misses *only once* after being invalidated 350 (by tbia or direct write). Next misses won't update them even 351 though the lock bits are cleared. Tags 4-7 are "quite LRU" though, 352 so use them and read at window 3 base exactly 4 times. Reading 353 more sometimes makes the chip crazy. -ink */ 354 355 bus_addr = cia_ioremap(CIA_BROKEN_TBIA_BASE, 32768 * 4); 356 357 cia_readl(bus_addr + 0x00000); 358 cia_readl(bus_addr + 0x08000); 359 cia_readl(bus_addr + 0x10000); 360 cia_readl(bus_addr + 0x18000); 361 362 cia_iounmap(bus_addr); 363 364 /* Restore normal PCI operation. */ 365 mb(); 366 *(vip)CIA_IOC_CIA_CTRL = ctrl; 367 mb(); 368 *(vip)CIA_IOC_CIA_CTRL; 369 mb(); 370} 371 372static inline void 373cia_prepare_tbia_workaround(void) 374{ 375 unsigned long *ppte, pte; 376 long i; 377 378 /* Use minimal 1K map. */ 379 ppte = __alloc_bootmem(CIA_BROKEN_TBIA_SIZE, 32768, 0); 380 pte = (virt_to_phys(ppte) >> (PAGE_SHIFT - 1)) | 1; 381 382 for (i = 0; i < CIA_BROKEN_TBIA_SIZE / sizeof(unsigned long); ++i) 383 ppte[i] = pte; 384 385 *(vip)CIA_IOC_PCI_W1_BASE = CIA_BROKEN_TBIA_BASE | 3; 386 *(vip)CIA_IOC_PCI_W1_MASK = (CIA_BROKEN_TBIA_SIZE*1024 - 1) 387 & 0xfff00000; 388 *(vip)CIA_IOC_PCI_T1_BASE = virt_to_phys(ppte) >> 2; 389} 390 391static void __init 392verify_tb_operation(void) 393{ 394 static int page[PAGE_SIZE/4] 395 __attribute__((aligned(PAGE_SIZE))) 396 __initdata = { 0 }; 397 398 struct pci_iommu_arena *arena = pci_isa_hose->sg_isa; 399 int ctrl, addr0, tag0, pte0, data0; 400 int temp, use_tbia_try2 = 0; 401 unsigned long bus_addr; 402 403 /* pyxis -- tbia is broken */ 404 if (pci_isa_hose->dense_io_base) 405 use_tbia_try2 = 1; 406 407 /* Put the chip into PCI loopback mode. */ 408 mb(); 409 ctrl = *(vip)CIA_IOC_CIA_CTRL; 410 *(vip)CIA_IOC_CIA_CTRL = ctrl | CIA_CTRL_PCI_LOOP_EN; 411 mb(); 412 *(vip)CIA_IOC_CIA_CTRL; 413 mb(); 414 415 /* Write a valid entry directly into the TLB registers. */ 416 417 addr0 = arena->dma_base; 418 tag0 = addr0 | 1; 419 pte0 = (virt_to_phys(page) >> (PAGE_SHIFT - 1)) | 1; 420 421 *(vip)CIA_IOC_TB_TAGn(0) = tag0; 422 *(vip)CIA_IOC_TB_TAGn(1) = 0; 423 *(vip)CIA_IOC_TB_TAGn(2) = 0; 424 *(vip)CIA_IOC_TB_TAGn(3) = 0; 425 *(vip)CIA_IOC_TB_TAGn(4) = 0; 426 *(vip)CIA_IOC_TB_TAGn(5) = 0; 427 *(vip)CIA_IOC_TB_TAGn(6) = 0; 428 *(vip)CIA_IOC_TB_TAGn(7) = 0; 429 *(vip)CIA_IOC_TBn_PAGEm(0,0) = pte0; 430 *(vip)CIA_IOC_TBn_PAGEm(0,1) = 0; 431 *(vip)CIA_IOC_TBn_PAGEm(0,2) = 0; 432 *(vip)CIA_IOC_TBn_PAGEm(0,3) = 0; 433 mb(); 434 435 /* Get a usable bus address */ 436 bus_addr = cia_ioremap(addr0, 8*PAGE_SIZE); 437 438 /* First, verify we can read back what we've written. If 439 this fails, we can't be sure of any of the other testing 440 we're going to do, so bail. */ 441 /* ??? Actually, we could do the work with machine checks. 442 By passing this register update test, we pretty much 443 guarantee that cia_pci_tbi_try1 works. If this test 444 fails, cia_pci_tbi_try2 might still work. */ 445 446 temp = *(vip)CIA_IOC_TB_TAGn(0); 447 if (temp != tag0) { 448 printk("pci: failed tb register update test " 449 "(tag0 %#x != %#x)\n", temp, tag0); 450 goto failed; 451 } 452 temp = *(vip)CIA_IOC_TB_TAGn(1); 453 if (temp != 0) { 454 printk("pci: failed tb register update test " 455 "(tag1 %#x != 0)\n", temp); 456 goto failed; 457 } 458 temp = *(vip)CIA_IOC_TBn_PAGEm(0,0); 459 if (temp != pte0) { 460 printk("pci: failed tb register update test " 461 "(pte0 %#x != %#x)\n", temp, pte0); 462 goto failed; 463 } 464 printk("pci: passed tb register update test\n"); 465 466 /* Second, verify we can actually do I/O through this entry. */ 467 468 data0 = 0xdeadbeef; 469 page[0] = data0; 470 mcheck_expected(0) = 1; 471 mcheck_taken(0) = 0; 472 mb(); 473 temp = cia_readl(bus_addr); 474 mb(); 475 mcheck_expected(0) = 0; 476 mb(); 477 if (mcheck_taken(0)) { 478 printk("pci: failed sg loopback i/o read test (mcheck)\n"); 479 goto failed; 480 } 481 if (temp != data0) { 482 printk("pci: failed sg loopback i/o read test " 483 "(%#x != %#x)\n", temp, data0); 484 goto failed; 485 } 486 printk("pci: passed sg loopback i/o read test\n"); 487 488 /* Third, try to invalidate the TLB. */ 489 490 if (! use_tbia_try2) { 491 cia_pci_tbi(arena->hose, 0, -1); 492 temp = *(vip)CIA_IOC_TB_TAGn(0); 493 if (temp & 1) { 494 use_tbia_try2 = 1; 495 printk("pci: failed tbia test; workaround available\n"); 496 } else { 497 printk("pci: passed tbia test\n"); 498 } 499 } 500 501 /* Fourth, verify the TLB snoops the EV5's caches when 502 doing a tlb fill. */ 503 504 data0 = 0x5adda15e; 505 page[0] = data0; 506 arena->ptes[4] = pte0; 507 mcheck_expected(0) = 1; 508 mcheck_taken(0) = 0; 509 mb(); 510 temp = cia_readl(bus_addr + 4*PAGE_SIZE); 511 mb(); 512 mcheck_expected(0) = 0; 513 mb(); 514 if (mcheck_taken(0)) { 515 printk("pci: failed pte write cache snoop test (mcheck)\n"); 516 goto failed; 517 } 518 if (temp != data0) { 519 printk("pci: failed pte write cache snoop test " 520 "(%#x != %#x)\n", temp, data0); 521 goto failed; 522 } 523 printk("pci: passed pte write cache snoop test\n"); 524 525 /* Fifth, verify that a previously invalid PTE entry gets 526 filled from the page table. */ 527 528 data0 = 0xabcdef12; 529 page[0] = data0; 530 arena->ptes[5] = pte0; 531 mcheck_expected(0) = 1; 532 mcheck_taken(0) = 0; 533 mb(); 534 temp = cia_readl(bus_addr + 5*PAGE_SIZE); 535 mb(); 536 mcheck_expected(0) = 0; 537 mb(); 538 if (mcheck_taken(0)) { 539 printk("pci: failed valid tag invalid pte reload test " 540 "(mcheck; workaround available)\n"); 541 /* Work around this bug by aligning new allocations 542 on 4 page boundaries. */ 543 arena->align_entry = 4; 544 } else if (temp != data0) { 545 printk("pci: failed valid tag invalid pte reload test " 546 "(%#x != %#x)\n", temp, data0); 547 goto failed; 548 } else { 549 printk("pci: passed valid tag invalid pte reload test\n"); 550 } 551 552 /* Sixth, verify machine checks are working. Test invalid 553 pte under the same valid tag as we used above. */ 554 555 mcheck_expected(0) = 1; 556 mcheck_taken(0) = 0; 557 mb(); 558 temp = cia_readl(bus_addr + 6*PAGE_SIZE); 559 mb(); 560 mcheck_expected(0) = 0; 561 mb(); 562 printk("pci: %s pci machine check test\n", 563 mcheck_taken(0) ? "passed" : "failed"); 564 565 /* Clean up after the tests. */ 566 arena->ptes[4] = 0; 567 arena->ptes[5] = 0; 568 569 if (use_tbia_try2) { 570 alpha_mv.mv_pci_tbi = cia_pci_tbi_try2; 571 572 /* Tags 0-3 must be disabled if we use this workaraund. */ 573 wmb(); 574 *(vip)CIA_IOC_TB_TAGn(0) = 2; 575 *(vip)CIA_IOC_TB_TAGn(1) = 2; 576 *(vip)CIA_IOC_TB_TAGn(2) = 2; 577 *(vip)CIA_IOC_TB_TAGn(3) = 2; 578 579 printk("pci: tbia workaround enabled\n"); 580 } 581 alpha_mv.mv_pci_tbi(arena->hose, 0, -1); 582 583exit: 584 /* unmap the bus addr */ 585 cia_iounmap(bus_addr); 586 587 /* Restore normal PCI operation. */ 588 mb(); 589 *(vip)CIA_IOC_CIA_CTRL = ctrl; 590 mb(); 591 *(vip)CIA_IOC_CIA_CTRL; 592 mb(); 593 return; 594 595failed: 596 printk("pci: disabling sg translation window\n"); 597 *(vip)CIA_IOC_PCI_W0_BASE = 0; 598 *(vip)CIA_IOC_PCI_W1_BASE = 0; 599 pci_isa_hose->sg_isa = NULL; 600 alpha_mv.mv_pci_tbi = NULL; 601 goto exit; 602} 603 604static void __init 605do_init_arch(int is_pyxis) 606{ 607 struct pci_controller *hose; 608 int temp; 609 int cia_rev; 610 611 cia_rev = *(vip)CIA_IOC_CIA_REV & CIA_REV_MASK; 612 printk("pci: cia revision %d%s\n", 613 cia_rev, is_pyxis ? " (pyxis)" : ""); 614 615 /* Set up error reporting. */ 616 temp = *(vip)CIA_IOC_ERR_MASK; 617 temp &= ~(CIA_ERR_CPU_PE | CIA_ERR_MEM_NEM | CIA_ERR_PA_PTE_INV 618 | CIA_ERR_RCVD_MAS_ABT | CIA_ERR_RCVD_TAR_ABT); 619 *(vip)CIA_IOC_ERR_MASK = temp; 620 621 /* Clear all currently pending errors. */ 622 temp = *(vip)CIA_IOC_CIA_ERR; 623 *(vip)CIA_IOC_CIA_ERR = temp; 624 625 /* Turn on mchecks. */ 626 temp = *(vip)CIA_IOC_CIA_CTRL; 627 temp |= CIA_CTRL_FILL_ERR_EN | CIA_CTRL_MCHK_ERR_EN; 628 *(vip)CIA_IOC_CIA_CTRL = temp; 629 630 /* Clear the CFG register, which gets used for PCI config space 631 accesses. That is the way we want to use it, and we do not 632 want to depend on what ARC or SRM might have left behind. */ 633 *(vip)CIA_IOC_CFG = 0; 634 635 /* Zero the HAEs. */ 636 *(vip)CIA_IOC_HAE_MEM = 0; 637 *(vip)CIA_IOC_HAE_IO = 0; 638 639 /* For PYXIS, we always use BWX bus and i/o accesses. To that end, 640 make sure they're enabled on the controller. At the same time, 641 enable the monster window. */ 642 if (is_pyxis) { 643 temp = *(vip)CIA_IOC_CIA_CNFG; 644 temp |= CIA_CNFG_IOA_BWEN | CIA_CNFG_PCI_MWEN; 645 *(vip)CIA_IOC_CIA_CNFG = temp; 646 } 647 648 /* Syncronize with all previous changes. */ 649 mb(); 650 *(vip)CIA_IOC_CIA_REV; 651 652 /* 653 * Create our single hose. 654 */ 655 656 pci_isa_hose = hose = alloc_pci_controller(); 657 hose->io_space = &ioport_resource; 658 hose->mem_space = &iomem_resource; 659 hose->index = 0; 660 661 if (! is_pyxis) { 662 struct resource *hae_mem = alloc_resource(); 663 hose->mem_space = hae_mem; 664 665 hae_mem->start = 0; 666 hae_mem->end = CIA_MEM_R1_MASK; 667 hae_mem->name = pci_hae0_name; 668 hae_mem->flags = IORESOURCE_MEM; 669 670 if (request_resource(&iomem_resource, hae_mem) < 0) 671 printk(KERN_ERR "Failed to request HAE_MEM\n"); 672 673 hose->sparse_mem_base = CIA_SPARSE_MEM - IDENT_ADDR; 674 hose->dense_mem_base = CIA_DENSE_MEM - IDENT_ADDR; 675 hose->sparse_io_base = CIA_IO - IDENT_ADDR; 676 hose->dense_io_base = 0; 677 } else { 678 hose->sparse_mem_base = 0; 679 hose->dense_mem_base = CIA_BW_MEM - IDENT_ADDR; 680 hose->sparse_io_base = 0; 681 hose->dense_io_base = CIA_BW_IO - IDENT_ADDR; 682 } 683 684 /* 685 * Set up the PCI to main memory translation windows. 686 * 687 * Window 0 is scatter-gather 8MB at 8MB (for isa) 688 * Window 1 is scatter-gather 1MB at 768MB (for tbia) 689 * Window 2 is direct access 2GB at 2GB 690 * Window 3 is DAC access 4GB at 8GB 691 * 692 * ??? NetBSD hints that page tables must be aligned to 32K, 693 * possibly due to a hardware bug. This is over-aligned 694 * from the 8K alignment one would expect for an 8MB window. 695 * No description of what revisions affected. 696 */ 697 698 hose->sg_pci = NULL; 699 hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 32768); 700 __direct_map_base = 0x80000000; 701 __direct_map_size = 0x80000000; 702 703 *(vip)CIA_IOC_PCI_W0_BASE = hose->sg_isa->dma_base | 3; 704 *(vip)CIA_IOC_PCI_W0_MASK = (hose->sg_isa->size - 1) & 0xfff00000; 705 *(vip)CIA_IOC_PCI_T0_BASE = virt_to_phys(hose->sg_isa->ptes) >> 2; 706 707 *(vip)CIA_IOC_PCI_W2_BASE = __direct_map_base | 1; 708 *(vip)CIA_IOC_PCI_W2_MASK = (__direct_map_size - 1) & 0xfff00000; 709 *(vip)CIA_IOC_PCI_T2_BASE = 0 >> 2; 710 711 /* On PYXIS we have the monster window, selected by bit 40, so 712 there is no need for window3 to be enabled. 713 714 On CIA, we don't have true arbitrary addressing -- bits <39:32> 715 are compared against W_DAC. We can, however, directly map 4GB, 716 which is better than before. However, due to assumptions made 717 elsewhere, we should not claim that we support DAC unless that 718 4GB covers all of physical memory. */ 719 if (is_pyxis || max_low_pfn > (0x100000000 >> PAGE_SHIFT)) { 720 *(vip)CIA_IOC_PCI_W3_BASE = 0; 721 } else { 722 *(vip)CIA_IOC_PCI_W3_BASE = 0x00000000 | 1 | 8; 723 *(vip)CIA_IOC_PCI_W3_MASK = 0xfff00000; 724 *(vip)CIA_IOC_PCI_T3_BASE = 0 >> 2; 725 726 alpha_mv.pci_dac_offset = 0x200000000; 727 *(vip)CIA_IOC_PCI_W_DAC = alpha_mv.pci_dac_offset >> 32; 728 } 729 730 cia_prepare_tbia_workaround(); 731} 732 733void __init 734cia_init_arch(void) 735{ 736 do_init_arch(0); 737} 738 739void __init 740pyxis_init_arch(void) 741{ 742 /* On pyxis machines we can precisely calculate the 743 CPU clock frequency using pyxis real time counter. 744 It's especially useful for SX164 with broken RTC. 745 746 Both CPU and chipset are driven by the single 16.666M 747 or 16.667M crystal oscillator. PYXIS_RT_COUNT clock is 748 66.66 MHz. -ink */ 749 750 unsigned int cc0, cc1; 751 unsigned long pyxis_cc; 752 753 __asm__ __volatile__ ("rpcc %0" : "=r"(cc0)); 754 pyxis_cc = *(vulp)PYXIS_RT_COUNT; 755 do { } while(*(vulp)PYXIS_RT_COUNT - pyxis_cc < 4096); 756 __asm__ __volatile__ ("rpcc %0" : "=r"(cc1)); 757 cc1 -= cc0; 758 hwrpb->cycle_freq = ((cc1 >> 11) * 100000000UL) / 3; 759 hwrpb_update_checksum(hwrpb); 760 761 do_init_arch(1); 762} 763 764void __init 765cia_init_pci(void) 766{ 767 /* Must delay this from init_arch, as we need machine checks. */ 768 verify_tb_operation(); 769 common_init_pci(); 770} 771 772static inline void 773cia_pci_clr_err(void) 774{ 775 int jd; 776 777 jd = *(vip)CIA_IOC_CIA_ERR; 778 *(vip)CIA_IOC_CIA_ERR = jd; 779 mb(); 780 *(vip)CIA_IOC_CIA_ERR; /* re-read to force write. */ 781} 782 783static void 784cia_decode_pci_error(struct el_CIA_sysdata_mcheck *cia, const char *msg) 785{ 786 static const char * const pci_cmd_desc[16] = { 787 "Interrupt Acknowledge", "Special Cycle", "I/O Read", 788 "I/O Write", "Reserved 0x4", "Reserved 0x5", "Memory Read", 789 "Memory Write", "Reserved 0x8", "Reserved 0x9", 790 "Configuration Read", "Configuration Write", 791 "Memory Read Multiple", "Dual Address Cycle", 792 "Memory Read Line", "Memory Write and Invalidate" 793 }; 794 795 if (cia->cia_err & (CIA_ERR_COR_ERR 796 | CIA_ERR_UN_COR_ERR 797 | CIA_ERR_MEM_NEM 798 | CIA_ERR_PA_PTE_INV)) { 799 static const char * const window_desc[6] = { 800 "No window active", "Window 0 hit", "Window 1 hit", 801 "Window 2 hit", "Window 3 hit", "Monster window hit" 802 }; 803 804 const char *window; 805 const char *cmd; 806 unsigned long addr, tmp; 807 int lock, dac; 808 809 cmd = pci_cmd_desc[cia->pci_err0 & 0x7]; 810 lock = (cia->pci_err0 >> 4) & 1; 811 dac = (cia->pci_err0 >> 5) & 1; 812 813 tmp = (cia->pci_err0 >> 8) & 0x1F; 814 tmp = ffs(tmp); 815 window = window_desc[tmp]; 816 817 addr = cia->pci_err1; 818 if (dac) { 819 tmp = *(vip)CIA_IOC_PCI_W_DAC & 0xFFUL; 820 addr |= tmp << 32; 821 } 822 823 printk(KERN_CRIT "CIA machine check: %s\n", msg); 824 printk(KERN_CRIT " DMA command: %s\n", cmd); 825 printk(KERN_CRIT " PCI address: %#010lx\n", addr); 826 printk(KERN_CRIT " %s, Lock: %d, DAC: %d\n", 827 window, lock, dac); 828 } else if (cia->cia_err & (CIA_ERR_PERR 829 | CIA_ERR_PCI_ADDR_PE 830 | CIA_ERR_RCVD_MAS_ABT 831 | CIA_ERR_RCVD_TAR_ABT 832 | CIA_ERR_IOA_TIMEOUT)) { 833 static const char * const master_st_desc[16] = { 834 "Idle", "Drive bus", "Address step cycle", 835 "Address cycle", "Data cycle", "Last read data cycle", 836 "Last write data cycle", "Read stop cycle", 837 "Write stop cycle", "Read turnaround cycle", 838 "Write turnaround cycle", "Reserved 0xB", 839 "Reserved 0xC", "Reserved 0xD", "Reserved 0xE", 840 "Unknown state" 841 }; 842 static const char * const target_st_desc[16] = { 843 "Idle", "Busy", "Read data cycle", "Write data cycle", 844 "Read stop cycle", "Write stop cycle", 845 "Read turnaround cycle", "Write turnaround cycle", 846 "Read wait cycle", "Write wait cycle", 847 "Reserved 0xA", "Reserved 0xB", "Reserved 0xC", 848 "Reserved 0xD", "Reserved 0xE", "Unknown state" 849 }; 850 851 const char *cmd; 852 const char *master, *target; 853 unsigned long addr, tmp; 854 int dac; 855 856 master = master_st_desc[(cia->pci_err0 >> 16) & 0xF]; 857 target = target_st_desc[(cia->pci_err0 >> 20) & 0xF]; 858 cmd = pci_cmd_desc[(cia->pci_err0 >> 24) & 0xF]; 859 dac = (cia->pci_err0 >> 28) & 1; 860 861 addr = cia->pci_err2; 862 if (dac) { 863 tmp = *(volatile int *)CIA_IOC_PCI_W_DAC & 0xFFUL; 864 addr |= tmp << 32; 865 } 866 867 printk(KERN_CRIT "CIA machine check: %s\n", msg); 868 printk(KERN_CRIT " PCI command: %s\n", cmd); 869 printk(KERN_CRIT " Master state: %s, Target state: %s\n", 870 master, target); 871 printk(KERN_CRIT " PCI address: %#010lx, DAC: %d\n", 872 addr, dac); 873 } else { 874 printk(KERN_CRIT "CIA machine check: %s\n", msg); 875 printk(KERN_CRIT " Unknown PCI error\n"); 876 printk(KERN_CRIT " PCI_ERR0 = %#08lx", cia->pci_err0); 877 printk(KERN_CRIT " PCI_ERR1 = %#08lx", cia->pci_err1); 878 printk(KERN_CRIT " PCI_ERR2 = %#08lx", cia->pci_err2); 879 } 880} 881 882static void 883cia_decode_mem_error(struct el_CIA_sysdata_mcheck *cia, const char *msg) 884{ 885 unsigned long mem_port_addr; 886 unsigned long mem_port_mask; 887 const char *mem_port_cmd; 888 const char *seq_state; 889 const char *set_select; 890 unsigned long tmp; 891 892 /* If this is a DMA command, also decode the PCI bits. */ 893 if ((cia->mem_err1 >> 20) & 1) 894 cia_decode_pci_error(cia, msg); 895 else 896 printk(KERN_CRIT "CIA machine check: %s\n", msg); 897 898 mem_port_addr = cia->mem_err0 & 0xfffffff0; 899 mem_port_addr |= (cia->mem_err1 & 0x83UL) << 32; 900 901 mem_port_mask = (cia->mem_err1 >> 12) & 0xF; 902 903 tmp = (cia->mem_err1 >> 8) & 0xF; 904 tmp |= ((cia->mem_err1 >> 20) & 1) << 4; 905 if ((tmp & 0x1E) == 0x06) 906 mem_port_cmd = "WRITE BLOCK or WRITE BLOCK LOCK"; 907 else if ((tmp & 0x1C) == 0x08) 908 mem_port_cmd = "READ MISS or READ MISS MODIFY"; 909 else if (tmp == 0x1C) 910 mem_port_cmd = "BC VICTIM"; 911 else if ((tmp & 0x1E) == 0x0E) 912 mem_port_cmd = "READ MISS MODIFY"; 913 else if ((tmp & 0x1C) == 0x18) 914 mem_port_cmd = "DMA READ or DMA READ MODIFY"; 915 else if ((tmp & 0x1E) == 0x12) 916 mem_port_cmd = "DMA WRITE"; 917 else 918 mem_port_cmd = "Unknown"; 919 920 tmp = (cia->mem_err1 >> 16) & 0xF; 921 switch (tmp) { 922 case 0x0: 923 seq_state = "Idle"; 924 break; 925 case 0x1: 926 seq_state = "DMA READ or DMA WRITE"; 927 break; 928 case 0x2: case 0x3: 929 seq_state = "READ MISS (or READ MISS MODIFY) with victim"; 930 break; 931 case 0x4: case 0x5: case 0x6: 932 seq_state = "READ MISS (or READ MISS MODIFY) with no victim"; 933 break; 934 case 0x8: case 0x9: case 0xB: 935 seq_state = "Refresh"; 936 break; 937 case 0xC: 938 seq_state = "Idle, waiting for DMA pending read"; 939 break; 940 case 0xE: case 0xF: 941 seq_state = "Idle, ras precharge"; 942 break; 943 default: 944 seq_state = "Unknown"; 945 break; 946 } 947 948 tmp = (cia->mem_err1 >> 24) & 0x1F; 949 switch (tmp) { 950 case 0x00: set_select = "Set 0 selected"; break; 951 case 0x01: set_select = "Set 1 selected"; break; 952 case 0x02: set_select = "Set 2 selected"; break; 953 case 0x03: set_select = "Set 3 selected"; break; 954 case 0x04: set_select = "Set 4 selected"; break; 955 case 0x05: set_select = "Set 5 selected"; break; 956 case 0x06: set_select = "Set 6 selected"; break; 957 case 0x07: set_select = "Set 7 selected"; break; 958 case 0x08: set_select = "Set 8 selected"; break; 959 case 0x09: set_select = "Set 9 selected"; break; 960 case 0x0A: set_select = "Set A selected"; break; 961 case 0x0B: set_select = "Set B selected"; break; 962 case 0x0C: set_select = "Set C selected"; break; 963 case 0x0D: set_select = "Set D selected"; break; 964 case 0x0E: set_select = "Set E selected"; break; 965 case 0x0F: set_select = "Set F selected"; break; 966 case 0x10: set_select = "No set selected"; break; 967 case 0x1F: set_select = "Refresh cycle"; break; 968 default: set_select = "Unknown"; break; 969 } 970 971 printk(KERN_CRIT " Memory port command: %s\n", mem_port_cmd); 972 printk(KERN_CRIT " Memory port address: %#010lx, mask: %#lx\n", 973 mem_port_addr, mem_port_mask); 974 printk(KERN_CRIT " Memory sequencer state: %s\n", seq_state); 975 printk(KERN_CRIT " Memory set: %s\n", set_select); 976} 977 978static void 979cia_decode_ecc_error(struct el_CIA_sysdata_mcheck *cia, const char *msg) 980{ 981 long syn; 982 long i; 983 const char *fmt; 984 985 cia_decode_mem_error(cia, msg); 986 987 syn = cia->cia_syn & 0xff; 988 if (syn == (syn & -syn)) { 989 fmt = KERN_CRIT " ECC syndrome %#x -- check bit %d\n"; 990 i = ffs(syn) - 1; 991 } else { 992 static unsigned char const data_bit[64] = { 993 0xCE, 0xCB, 0xD3, 0xD5, 994 0xD6, 0xD9, 0xDA, 0xDC, 995 0x23, 0x25, 0x26, 0x29, 996 0x2A, 0x2C, 0x31, 0x34, 997 0x0E, 0x0B, 0x13, 0x15, 998 0x16, 0x19, 0x1A, 0x1C, 999 0xE3, 0xE5, 0xE6, 0xE9, 1000 0xEA, 0xEC, 0xF1, 0xF4, 1001 0x4F, 0x4A, 0x52, 0x54, 1002 0x57, 0x58, 0x5B, 0x5D, 1003 0xA2, 0xA4, 0xA7, 0xA8, 1004 0xAB, 0xAD, 0xB0, 0xB5, 1005 0x8F, 0x8A, 0x92, 0x94, 1006 0x97, 0x98, 0x9B, 0x9D, 1007 0x62, 0x64, 0x67, 0x68, 1008 0x6B, 0x6D, 0x70, 0x75 1009 }; 1010 1011 for (i = 0; i < 64; ++i) 1012 if (data_bit[i] == syn) 1013 break; 1014 1015 if (i < 64) 1016 fmt = KERN_CRIT " ECC syndrome %#x -- data bit %d\n"; 1017 else 1018 fmt = KERN_CRIT " ECC syndrome %#x -- unknown bit\n"; 1019 } 1020 1021 printk (fmt, syn, i); 1022} 1023 1024static void 1025cia_decode_parity_error(struct el_CIA_sysdata_mcheck *cia) 1026{ 1027 static const char * const cmd_desc[16] = { 1028 "NOP", "LOCK", "FETCH", "FETCH_M", "MEMORY BARRIER", 1029 "SET DIRTY", "WRITE BLOCK", "WRITE BLOCK LOCK", 1030 "READ MISS0", "READ MISS1", "READ MISS MOD0", 1031 "READ MISS MOD1", "BCACHE VICTIM", "Spare", 1032 "READ MISS MOD STC0", "READ MISS MOD STC1" 1033 }; 1034 1035 unsigned long addr; 1036 unsigned long mask; 1037 const char *cmd; 1038 int par; 1039 1040 addr = cia->cpu_err0 & 0xfffffff0; 1041 addr |= (cia->cpu_err1 & 0x83UL) << 32; 1042 cmd = cmd_desc[(cia->cpu_err1 >> 8) & 0xF]; 1043 mask = (cia->cpu_err1 >> 12) & 0xF; 1044 par = (cia->cpu_err1 >> 21) & 1; 1045 1046 printk(KERN_CRIT "CIA machine check: System bus parity error\n"); 1047 printk(KERN_CRIT " Command: %s, Parity bit: %d\n", cmd, par); 1048 printk(KERN_CRIT " Address: %#010lx, Mask: %#lx\n", addr, mask); 1049} 1050 1051static int 1052cia_decode_mchk(unsigned long la_ptr) 1053{ 1054 struct el_common *com; 1055 struct el_CIA_sysdata_mcheck *cia; 1056 int which; 1057 1058 com = (void *)la_ptr; 1059 cia = (void *)(la_ptr + com->sys_offset); 1060 1061 if ((cia->cia_err & CIA_ERR_VALID) == 0) 1062 return 0; 1063 1064 which = cia->cia_err & 0xfff; 1065 switch (ffs(which) - 1) { 1066 case 0: /* CIA_ERR_COR_ERR */ 1067 cia_decode_ecc_error(cia, "Corrected ECC error"); 1068 break; 1069 case 1: /* CIA_ERR_UN_COR_ERR */ 1070 cia_decode_ecc_error(cia, "Uncorrected ECC error"); 1071 break; 1072 case 2: /* CIA_ERR_CPU_PE */ 1073 cia_decode_parity_error(cia); 1074 break; 1075 case 3: /* CIA_ERR_MEM_NEM */ 1076 cia_decode_mem_error(cia, "Access to nonexistent memory"); 1077 break; 1078 case 4: /* CIA_ERR_PCI_SERR */ 1079 cia_decode_pci_error(cia, "PCI bus system error"); 1080 break; 1081 case 5: /* CIA_ERR_PERR */ 1082 cia_decode_pci_error(cia, "PCI data parity error"); 1083 break; 1084 case 6: /* CIA_ERR_PCI_ADDR_PE */ 1085 cia_decode_pci_error(cia, "PCI address parity error"); 1086 break; 1087 case 7: /* CIA_ERR_RCVD_MAS_ABT */ 1088 cia_decode_pci_error(cia, "PCI master abort"); 1089 break; 1090 case 8: /* CIA_ERR_RCVD_TAR_ABT */ 1091 cia_decode_pci_error(cia, "PCI target abort"); 1092 break; 1093 case 9: /* CIA_ERR_PA_PTE_INV */ 1094 cia_decode_pci_error(cia, "PCI invalid PTE"); 1095 break; 1096 case 10: /* CIA_ERR_FROM_WRT_ERR */ 1097 cia_decode_mem_error(cia, "Write to flash ROM attempted"); 1098 break; 1099 case 11: /* CIA_ERR_IOA_TIMEOUT */ 1100 cia_decode_pci_error(cia, "I/O timeout"); 1101 break; 1102 } 1103 1104 if (cia->cia_err & CIA_ERR_LOST_CORR_ERR) 1105 printk(KERN_CRIT "CIA lost machine check: " 1106 "Correctable ECC error\n"); 1107 if (cia->cia_err & CIA_ERR_LOST_UN_CORR_ERR) 1108 printk(KERN_CRIT "CIA lost machine check: " 1109 "Uncorrectable ECC error\n"); 1110 if (cia->cia_err & CIA_ERR_LOST_CPU_PE) 1111 printk(KERN_CRIT "CIA lost machine check: " 1112 "System bus parity error\n"); 1113 if (cia->cia_err & CIA_ERR_LOST_MEM_NEM) 1114 printk(KERN_CRIT "CIA lost machine check: " 1115 "Access to nonexistent memory\n"); 1116 if (cia->cia_err & CIA_ERR_LOST_PERR) 1117 printk(KERN_CRIT "CIA lost machine check: " 1118 "PCI data parity error\n"); 1119 if (cia->cia_err & CIA_ERR_LOST_PCI_ADDR_PE) 1120 printk(KERN_CRIT "CIA lost machine check: " 1121 "PCI address parity error\n"); 1122 if (cia->cia_err & CIA_ERR_LOST_RCVD_MAS_ABT) 1123 printk(KERN_CRIT "CIA lost machine check: " 1124 "PCI master abort\n"); 1125 if (cia->cia_err & CIA_ERR_LOST_RCVD_TAR_ABT) 1126 printk(KERN_CRIT "CIA lost machine check: " 1127 "PCI target abort\n"); 1128 if (cia->cia_err & CIA_ERR_LOST_PA_PTE_INV) 1129 printk(KERN_CRIT "CIA lost machine check: " 1130 "PCI invalid PTE\n"); 1131 if (cia->cia_err & CIA_ERR_LOST_FROM_WRT_ERR) 1132 printk(KERN_CRIT "CIA lost machine check: " 1133 "Write to flash ROM attempted\n"); 1134 if (cia->cia_err & CIA_ERR_LOST_IOA_TIMEOUT) 1135 printk(KERN_CRIT "CIA lost machine check: " 1136 "I/O timeout\n"); 1137 1138 return 1; 1139} 1140 1141void 1142cia_machine_check(unsigned long vector, unsigned long la_ptr, 1143 struct pt_regs * regs) 1144{ 1145 int expected; 1146 1147 /* Clear the error before any reporting. */ 1148 mb(); 1149 mb(); /* magic */ 1150 draina(); 1151 cia_pci_clr_err(); 1152 wrmces(rdmces()); /* reset machine check pending flag. */ 1153 mb(); 1154 1155 expected = mcheck_expected(0); 1156 if (!expected && vector == 0x660) 1157 expected = cia_decode_mchk(la_ptr); 1158 process_mcheck_info(vector, la_ptr, regs, "CIA", expected); 1159} 1160