1/* 2 * BCM47XX Sonics SiliconBackplane embedded ram core 3 * 4 * Copyright 2007, Broadcom Corporation 5 * All Rights Reserved. 6 * 7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY 8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM 9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS 10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE. 11 * 12 * $Id: sbsocram.h,v 1.1.1.1 2008/10/15 03:25:54 james26_jang Exp $ 13 */ 14 15#ifndef _SBSOCRAM_H 16#define _SBSOCRAM_H 17 18#ifndef _LANGUAGE_ASSEMBLY 19 20/* cpp contortions to concatenate w/arg prescan */ 21#ifndef PAD 22#define _PADLINE(line) pad ## line 23#define _XSTR(line) _PADLINE(line) 24#define PAD _XSTR(__LINE__) 25#endif /* PAD */ 26 27/* Memcsocram core registers */ 28typedef volatile struct sbsocramregs { 29 uint32 coreinfo; 30 uint32 bwalloc; 31 uint32 PAD; 32 uint32 biststat; 33 uint32 bankidx; 34 uint32 standbyctrl; 35 uint32 PAD[116]; 36 uint32 pwrctl; /* corerev >= 2 */ 37} sbsocramregs_t; 38 39#endif /* _LANGUAGE_ASSEMBLY */ 40 41/* Register offsets */ 42#define SR_COREINFO 0x00 43#define SR_BWALLOC 0x04 44#define SR_BISTSTAT 0x0c 45#define SR_BANKINDEX 0x10 46#define SR_BANKSTBYCTL 0x14 47#define SR_PWRCTL 0x1e8 48 49/* Coreinfo register */ 50#define SRCI_PT_MASK 0x00030000 51#define SRCI_PT_SHIFT 16 52/* corerev >= 3 */ 53#define SRCI_LSS_MASK 0x00f00000 54#define SRCI_LSS_SHIFT 20 55#define SRCI_LRS_MASK 0x0f000000 56#define SRCI_LRS_SHIFT 24 57 58/* In corerev 0, the memory size is 2 to the power of the 59 * base plus 16 plus to the contents of the memsize field plus 1. 60 */ 61#define SRCI_MS0_MASK 0xf 62#define SR_MS0_BASE 16 63 64/* 65 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 66 * the memory size is number of banks times bank size. 67 * The same applies to rom size. 68 */ 69#define SRCI_ROMNB_MASK 0xf000 70#define SRCI_ROMNB_SHIFT 12 71#define SRCI_ROMBSZ_MASK 0xf00 72#define SRCI_ROMBSZ_SHIFT 8 73#define SRCI_SRNB_MASK 0xf0 74#define SRCI_SRNB_SHIFT 4 75#define SRCI_SRBSZ_MASK 0xf 76#define SRCI_SRBSZ_SHIFT 0 77 78#define SR_BSZ_BASE 14 79 80/* Standby control register */ 81#define SRSC_SBYOVR_MASK 0x80000000 82#define SRSC_SBYOVR_SHIFT 31 83#define SRSC_SBYOVRVAL_MASK 0x60000000 84#define SRSC_SBYOVRVAL_SHIFT 29 85 86#endif /* _SBSOCRAM_H */ 87